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Reel/Frame:023786/0416   Pages: 274
Recorded: 01/04/2010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3434
Page 24 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
03/17/2009
Application #:
10334999
Filing Dt:
12/31/2002
Publication #:
Pub Dt:
01/24/2008
Title:
MEMORY ELEMENTS
2
Patent #:
Issue Dt:
05/17/2005
Application #:
10336094
Filing Dt:
01/03/2003
Publication #:
Pub Dt:
06/05/2003
Title:
WEB-FORMAT POLISHING PADS AND METHODS FOR MANUFACTURING AND USING WEB-FORMAT POLISHING PADS IN MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
3
Patent #:
Issue Dt:
06/15/2004
Application #:
10338191
Filing Dt:
01/07/2003
Publication #:
Pub Dt:
05/22/2003
Title:
VOLTAGE PUMP AND A LEVEL TRANSLATOR CIRCUIT
4
Patent #:
Issue Dt:
06/22/2004
Application #:
10338331
Filing Dt:
01/06/2003
Publication #:
Pub Dt:
05/29/2003
Title:
METHOD FOR WRITING TO MULTIPLE BANKS OF A MEMORY DEVICE
5
Patent #:
Issue Dt:
12/28/2004
Application #:
10339752
Filing Dt:
01/08/2003
Publication #:
Pub Dt:
07/08/2004
Title:
METHOD AND SYSTEM FOR DELAY CONTROL IN SYNCHRONIZATION CIRCUITS
6
Patent #:
Issue Dt:
01/27/2004
Application #:
10340104
Filing Dt:
01/10/2003
Publication #:
Pub Dt:
06/05/2003
Title:
HIGH SPEED DIGITAL SIGNAL BUFFER AND METHOD
7
Patent #:
Issue Dt:
07/03/2007
Application #:
10340331
Filing Dt:
01/09/2003
Publication #:
Pub Dt:
05/29/2003
Title:
PACKAGES FOR SEMICONDUCTOR DIE
8
Patent #:
Issue Dt:
02/15/2005
Application #:
10341057
Filing Dt:
01/13/2003
Publication #:
Pub Dt:
07/03/2003
Title:
MEMORY SYSTEM, METHOD AND PREDECODING CIRCUIT OPERABLE IN DIFFERENT MODES FOR SELECTIVELY ACCESSING MULTIPLE BLOCKS OF MEMORY CELLS FOR SIMULTANEOUS WRITING OR ERASURE
9
Patent #:
Issue Dt:
10/26/2004
Application #:
10341061
Filing Dt:
01/13/2003
Publication #:
Pub Dt:
07/03/2003
Title:
MEMORY SYSTEM, METHOD AND PREDECODING CIRCUIT OPERABLE IN DIFFERENT MODES FOR SELECTIVELY ACCESSING MULTIPLE BLOCKS OF MEMORY CELLS FOR SIMULTANEOUS WRITING OR ERASURE
10
Patent #:
Issue Dt:
11/01/2005
Application #:
10341068
Filing Dt:
01/13/2003
Publication #:
Pub Dt:
07/03/2003
Title:
MEMORY SYSTEM, METHOD AND PREDECODING CIRCUIT OPERABLE IN DIFFERENT MODES FOR SELECTIVELY ACCESSING MULTIPLE BLOCKS OF MEMORY CELLS FOR SIMULTANEOUS READING WRITING OR ERASURE
11
Patent #:
Issue Dt:
06/13/2006
Application #:
10341314
Filing Dt:
01/13/2003
Publication #:
Pub Dt:
09/18/2003
Title:
FLASH MEMORY PROGRAMMING
12
Patent #:
Issue Dt:
12/16/2003
Application #:
10345765
Filing Dt:
01/15/2003
Publication #:
Pub Dt:
07/03/2003
Title:
SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE
13
Patent #:
Issue Dt:
02/12/2008
Application #:
10346860
Filing Dt:
01/16/2003
Title:
MULTI-CHIP STACKED DEVICES
14
Patent #:
Issue Dt:
04/19/2005
Application #:
10346868
Filing Dt:
01/17/2003
Publication #:
Pub Dt:
07/10/2003
Title:
ELECTRICAL APPARATUSES, METHODS OF FORMING ELECTRICAL APPARATUSES, AND TERMITE SENSING METHODS
15
Patent #:
Issue Dt:
05/24/2005
Application #:
10346994
Filing Dt:
01/17/2003
Publication #:
Pub Dt:
07/10/2003
Title:
CONTROLLABLE OVANIC PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE
16
Patent #:
Issue Dt:
01/27/2004
Application #:
10349516
Filing Dt:
01/21/2003
Publication #:
Pub Dt:
06/12/2003
Title:
PORTABLE COMPUTER SUPPORTING PAGING INSTRUCTIONS
17
Patent #:
Issue Dt:
11/01/2005
Application #:
10351077
Filing Dt:
01/23/2003
Publication #:
Pub Dt:
07/29/2004
Title:
APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS
18
Patent #:
Issue Dt:
11/08/2005
Application #:
10352698
Filing Dt:
01/27/2003
Publication #:
Pub Dt:
06/19/2003
Title:
VERTICALLY MOUNTABLE AND ALIGNABLE SEMICONDUCTOR DEVICE ASSEMBLY
19
Patent #:
Issue Dt:
04/19/2005
Application #:
10355781
Filing Dt:
01/29/2003
Publication #:
Pub Dt:
07/29/2004
Title:
MULTIPLE CONFIGURATION MULTIPLE CHIP MEMORY DEVICE AND METHOD
20
Patent #:
Issue Dt:
03/02/2004
Application #:
10355790
Filing Dt:
01/31/2003
Publication #:
Pub Dt:
06/19/2003
Title:
METHOD AND APPARATUS FOR COUPLING A SEMICONDUCTOR DIE TO DIE TERMINALS
21
Patent #:
Issue Dt:
02/17/2004
Application #:
10356097
Filing Dt:
01/31/2003
Publication #:
Pub Dt:
07/17/2003
Title:
READ COMPRESSION IN A MEMORY
22
Patent #:
Issue Dt:
02/24/2004
Application #:
10357527
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
07/24/2003
Title:
INTEGRATED CIRCUIT INDUCTOR WITH A MAGNETIC CORE
23
Patent #:
Issue Dt:
06/29/2004
Application #:
10357528
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
07/24/2003
Title:
INTEGRATED CIRCUIT INDUCTOR WITH A MAGNETIC CORE
24
Patent #:
Issue Dt:
05/04/2004
Application #:
10357586
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
07/24/2003
Title:
TWO-STAGE TRANSFER MOLDING DEVICE TO ENCAPSULATE MMC MODULE
25
Patent #:
Issue Dt:
09/07/2004
Application #:
10357656
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
07/24/2003
Title:
METHODS OF WAFER LEVEL FABRICATION AND ASSEMBLY OF CHIP SCALE PACKAGES
26
Patent #:
Issue Dt:
11/23/2004
Application #:
10357670
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
06/26/2003
Title:
OUTPUT DATA PATH CAPABLE OF MULTIPLE DATA RATES
27
Patent #:
Issue Dt:
03/08/2005
Application #:
10357895
Filing Dt:
02/03/2003
Publication #:
Pub Dt:
06/19/2003
Title:
OUTPUT DATA PATH CAPABLE OF MULTIPLE DATA RATES
28
Patent #:
Issue Dt:
01/06/2004
Application #:
10365399
Filing Dt:
02/13/2003
Publication #:
Pub Dt:
07/03/2003
Title:
PREDICTIVE TIMING CALIBRATION FOR MEMORY DEVICES
29
Patent #:
Issue Dt:
04/05/2005
Application #:
10366836
Filing Dt:
02/14/2003
Publication #:
Pub Dt:
11/27/2003
Title:
FLASH WITH CONSISTENT LATENCY FOR READ OPERATIONS
30
Patent #:
Issue Dt:
04/13/2004
Application #:
10366902
Filing Dt:
02/14/2003
Publication #:
Pub Dt:
08/07/2003
Title:
METHODS OF ACCESSING FLOATING-GATE MEMORY CELLS HAVING UNDERLYING SOURCE-LINE CONNECTIONS
31
Patent #:
Issue Dt:
08/16/2005
Application #:
10367012
Filing Dt:
02/14/2003
Publication #:
Pub Dt:
08/07/2003
Title:
METHODS OF FORMING MEMORY CELLS AND ARRAYS HAVING UNDERLYING SOURCE-LINE CONNECTIONS
32
Patent #:
Issue Dt:
08/31/2004
Application #:
10367287
Filing Dt:
02/14/2003
Publication #:
Pub Dt:
07/10/2003
Title:
INTEGRATED CIRCUIT HAVING ALIGNED FUSES AND METHODS FOR FORMING AND PROGRAMMING THE FUSES
33
Patent #:
Issue Dt:
07/12/2005
Application #:
10367587
Filing Dt:
02/14/2003
Publication #:
Pub Dt:
04/15/2004
Title:
DUAL BUS MEMORY BURST ARCHITECTURE
34
Patent #:
Issue Dt:
12/23/2003
Application #:
10368874
Filing Dt:
02/19/2003
Publication #:
Pub Dt:
07/10/2003
Title:
SYNCHRONOUS FLASH MEMORY WITH VIRTUAL SEGMENT ARCHITECTURE
35
Patent #:
Issue Dt:
09/28/2004
Application #:
10369010
Filing Dt:
02/19/2003
Publication #:
Pub Dt:
07/03/2003
Title:
SYNCHRONOUS FLASH MEMORY WITH VIRTUAL SEGMENT ARCHITECTURE
36
Patent #:
Issue Dt:
03/27/2007
Application #:
10370674
Filing Dt:
02/21/2003
Publication #:
Pub Dt:
12/18/2003
Title:
METHODS FOR PACKAGING IMAGE SENSITIVE ELECTRONIC DEVICES
37
Patent #:
Issue Dt:
04/06/2004
Application #:
10371123
Filing Dt:
02/19/2003
Publication #:
Pub Dt:
07/10/2003
Title:
METHODS OF OPERATING MICROELECTRONIC DEVICES, AND METHODS OF PROVIDING MICROELECTRONIC DEVICES
38
Patent #:
Issue Dt:
07/04/2006
Application #:
10372594
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
08/14/2003
Title:
METHOD OF MAKING A FLEXIBLE SUBSTRATE WITH A FILLER MATERIAL
39
Patent #:
Issue Dt:
08/03/2004
Application #:
10373261
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
09/04/2003
Title:
COMPOSITE INTERPOSER FOR BGA PACKAGES
40
Patent #:
Issue Dt:
08/17/2004
Application #:
10373498
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
09/18/2003
Title:
METHODS OF STORING A TEMPERATURE IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT
41
Patent #:
Issue Dt:
05/11/2004
Application #:
10375160
Filing Dt:
02/27/2003
Publication #:
Pub Dt:
07/10/2003
Title:
METHOD AND ARCHITECTURE TO CALIBRATE READ OPERATIONS IN SYNCHRONOUS FLASH MEMORY
42
Patent #:
Issue Dt:
03/23/2004
Application #:
10375639
Filing Dt:
02/26/2003
Publication #:
Pub Dt:
07/10/2003
Title:
ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS
43
Patent #:
Issue Dt:
11/15/2005
Application #:
10375864
Filing Dt:
02/26/2003
Publication #:
Pub Dt:
03/04/2004
Title:
METHODS OF FABRICATION FOR FLIP-CHIP IMAGE SENSOR PACKAGES
44
Patent #:
Issue Dt:
01/06/2004
Application #:
10377064
Filing Dt:
02/28/2003
Publication #:
Pub Dt:
08/14/2003
Title:
FLASH MEMORY CIRCUITRY
45
Patent #:
Issue Dt:
01/04/2005
Application #:
10378019
Filing Dt:
02/27/2003
Publication #:
Pub Dt:
08/14/2003
Title:
INTEGRATED CAPACITOR BOTTOM ELECTRODE FOR USE WITH CONFORMAL DIELECTRIC
46
Patent #:
Issue Dt:
10/31/2006
Application #:
10379006
Filing Dt:
03/04/2003
Publication #:
Pub Dt:
09/09/2004
Title:
METHOD AND APPARATUS FOR CALIBRATING DRIVER IMPEDANCE
47
Patent #:
Issue Dt:
03/29/2005
Application #:
10379035
Filing Dt:
03/03/2003
Publication #:
Pub Dt:
09/09/2004
Title:
SYSTEMS AND METHODS FOR MONITORING CHARACTERISTICS OF A POLISHING PAD USED IN POLISHING MICRO-DEVICE WORKPIECES
48
Patent #:
Issue Dt:
08/16/2005
Application #:
10379759
Filing Dt:
03/04/2003
Publication #:
Pub Dt:
09/09/2004
Title:
METHOD AND APPARATUS FOR MULTI-FUNCTIONAL INPUTS OF A MEMORY DEVICE
49
Patent #:
Issue Dt:
12/28/2004
Application #:
10382594
Filing Dt:
03/06/2003
Publication #:
Pub Dt:
07/31/2003
Title:
METHOD OF IMPROVING COPPER INTERCONNECTS OF SEMICONDUCTOR DEVICES FOR BONDING
50
Patent #:
Issue Dt:
01/04/2005
Application #:
10383654
Filing Dt:
03/10/2003
Publication #:
Pub Dt:
08/07/2003
Title:
WIRELESS COMMUNICATIONS SYSTEM EMPLOYING A CHIP CARRIER
51
Patent #:
Issue Dt:
11/28/2006
Application #:
10383939
Filing Dt:
03/07/2003
Publication #:
Pub Dt:
05/20/2004
Title:
ACTIVE TERMINATION CONTROL THOUGH ON MODULE REGISTER
52
Patent #:
Issue Dt:
09/28/2004
Application #:
10384267
Filing Dt:
03/07/2003
Publication #:
Pub Dt:
09/18/2003
Title:
METHOD OF FABRICATING A SMALL ELECTRODE FOR CHALCOGENIDE MEMORY CELLS
53
Patent #:
Issue Dt:
07/13/2004
Application #:
10389807
Filing Dt:
03/18/2003
Title:
METHOD AND APPARATUS FOR ESTABLISHING AND MAINTAINING DESIRED READ LATENCY IN HIGH-SPEED DRAM
54
Patent #:
Issue Dt:
01/11/2005
Application #:
10403937
Filing Dt:
03/31/2003
Publication #:
Pub Dt:
12/23/2004
Title:
MULTI-DICE CHIP SCALE SEMICONDUCTOR COMPONENTS AND WAFER LEVEL METHODS OF FABRICATION
55
Patent #:
Issue Dt:
10/09/2007
Application #:
10404145
Filing Dt:
04/02/2003
Publication #:
Pub Dt:
10/07/2004
Title:
PASSIVATION PLANARIZATION
56
Patent #:
Issue Dt:
12/12/2006
Application #:
10405257
Filing Dt:
03/31/2003
Publication #:
Pub Dt:
09/30/2004
Title:
MEMORY DEVICES WITH BUFFERED COMMAND ADDRESS BUS
57
Patent #:
Issue Dt:
05/26/2009
Application #:
10406493
Filing Dt:
04/04/2003
Publication #:
Pub Dt:
09/11/2003
Title:
TWIN P-WELL CMOS IMAGER
58
Patent #:
Issue Dt:
07/12/2005
Application #:
10408183
Filing Dt:
04/07/2003
Publication #:
Pub Dt:
10/07/2004
Title:
CHIP SCALE IMAGE SENSOR PACKAGE
59
Patent #:
Issue Dt:
11/09/2004
Application #:
10408527
Filing Dt:
04/07/2003
Publication #:
Pub Dt:
10/30/2003
Title:
SEMICONDUCTOR DEVICE WITH SELF REFRESH TEST MODE
60
Patent #:
Issue Dt:
02/15/2005
Application #:
10408540
Filing Dt:
04/07/2003
Publication #:
Pub Dt:
11/13/2003
Title:
SEMICONDUCTOR DEVICE WITH SELF REFRESH TEST MODE
61
Patent #:
Issue Dt:
01/04/2005
Application #:
10410575
Filing Dt:
04/08/2003
Publication #:
Pub Dt:
02/19/2004
Title:
REFRESH CONTROLLER AND ADDRESS REMAPPING CIRCUIT AND METHOD FOR DUAL MODE FULL/REDUCED DENSITY DRAMS
62
Patent #:
Issue Dt:
06/29/2004
Application #:
10413750
Filing Dt:
04/15/2003
Publication #:
Pub Dt:
09/18/2003
Title:
THIN FILM STRUCTURE THAT MAY BE USED WITH AN ADHESION LAYER
63
Patent #:
Issue Dt:
10/12/2004
Application #:
10418540
Filing Dt:
04/17/2003
Publication #:
Pub Dt:
10/30/2003
Title:
METHOD OF FORMING A LOCAL INTERCONNECT
64
Patent #:
Issue Dt:
04/19/2005
Application #:
10419191
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
11/06/2003
Title:
METHOD OF FORMING A MIM CAPACITOR WITH METAL NITRIDE ELECTRODE
65
Patent #:
Issue Dt:
05/31/2011
Application #:
10421079
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
10/16/2003
Title:
SOLDER BALL LANDPAD DESIGN TO IMPROVE LAMINATE PERFORMANCE
66
Patent #:
Issue Dt:
07/05/2005
Application #:
10421132
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
11/06/2003
Title:
SOLDER BALL LANDPAD DESIGN TO IMPROVE LAMINATE PERFORMANCE
67
Patent #:
Issue Dt:
11/09/2004
Application #:
10423240
Filing Dt:
04/25/2003
Publication #:
Pub Dt:
10/16/2003
Title:
MASK REPATTERN PROCESS
68
Patent #:
Issue Dt:
08/24/2004
Application #:
10424508
Filing Dt:
04/28/2003
Publication #:
Pub Dt:
10/09/2003
Title:
METHOD AND APPARATUS FOR DETERMINING DIGITAL DELAY LINE ENTRY POINT
69
Patent #:
Issue Dt:
08/01/2006
Application #:
10427518
Filing Dt:
05/01/2003
Publication #:
Pub Dt:
10/23/2003
Title:
METHODS FOR MODIFYING A VERTICAL SURFACE MOUNT PACKAGE
70
Patent #:
Issue Dt:
08/15/2006
Application #:
10430102
Filing Dt:
05/05/2003
Publication #:
Pub Dt:
10/30/2003
Title:
CIRCUIT AND SUBSTRATE ENCAPSULATION METHODS
71
Patent #:
Issue Dt:
04/26/2005
Application #:
10431161
Filing Dt:
05/06/2003
Publication #:
Pub Dt:
10/30/2003
Title:
PROGRAMMABLE DUAL-DRIVE STRENGTH OUTPUT BUFFER WITH A SHARED BOOT CIRCUIT
72
Patent #:
Issue Dt:
12/13/2005
Application #:
10431862
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/11/2004
Title:
NAND FLASH MEMORY WITH IMPROVED READ AND VERIFICATION THRESHOLD UNIFORMITY
73
Patent #:
Issue Dt:
01/17/2006
Application #:
10440131
Filing Dt:
05/19/2003
Publication #:
Pub Dt:
11/25/2004
Title:
MAGNITUDE COMPARATOR BASED CONTENT ADDRESSABLE MEMORY FOR SEARCH AND SORTING
74
Patent #:
Issue Dt:
01/01/2008
Application #:
10443471
Filing Dt:
05/22/2003
Publication #:
Pub Dt:
10/23/2003
Title:
SEMICONDUCTOR DEVICE HAVING INTEGRATED CIRCUIT CONTACT
75
Patent #:
Issue Dt:
03/22/2005
Application #:
10446382
Filing Dt:
05/27/2003
Publication #:
Pub Dt:
09/18/2003
Title:
ASSEMBLIES INCLUDING STACKED SEMICONDUCTOR DEVICES SEPARATED A DISTANCE DEFINED BY ADHESIVE MATERIAL INTERPOSED THEREBETWEEN, PACKAGES INCLUDING THE ASSEMBLIES, AND METHODS
76
Patent #:
Issue Dt:
08/10/2004
Application #:
10452969
Filing Dt:
06/02/2003
Publication #:
Pub Dt:
10/23/2003
Title:
SECURE CARGO TRANSPORTATION SYSTEM
77
Patent #:
Issue Dt:
09/14/2004
Application #:
10454098
Filing Dt:
06/02/2003
Publication #:
Pub Dt:
11/06/2003
Title:
DUAL DEPTH TRENCH ISOLATION
78
Patent #:
Issue Dt:
06/15/2004
Application #:
10459595
Filing Dt:
06/12/2003
Publication #:
Pub Dt:
11/20/2003
Title:
LOCK IN PINNED PHOTODIODE PHOTODETECTOR
79
Patent #:
Issue Dt:
07/17/2007
Application #:
10460588
Filing Dt:
06/11/2003
Publication #:
Pub Dt:
12/16/2004
Title:
MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY
80
Patent #:
Issue Dt:
01/23/2007
Application #:
10461207
Filing Dt:
06/12/2003
Publication #:
Pub Dt:
01/06/2005
Title:
DYNAMIC SYNCHRONIZATION OF DATA CAPTURE ON AN OPTICAL OR OTHER HIGH SPEED COMMUNICATIONS LINK
81
Patent #:
Issue Dt:
06/01/2004
Application #:
10464234
Filing Dt:
06/17/2003
Publication #:
Pub Dt:
11/06/2003
Title:
PIPELINED MEMORY CONTROLLER
82
Patent #:
Issue Dt:
09/14/2004
Application #:
10600907
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
05/06/2004
Title:
SEMICONDUCTOR PROCESSING METHODS OF REMOVING CONDUCTIVE MATERIAL
83
Patent #:
Issue Dt:
10/10/2006
Application #:
10601104
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
12/23/2004
Title:
RECONFIGURABLE MEMORY MODULE AND METHOD
84
Patent #:
Issue Dt:
09/23/2008
Application #:
10601222
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/23/2004
Title:
SYSTEM AND METHOD FOR SELECTIVE MEMORY MODULE POWER MANAGEMENT
85
Patent #:
Issue Dt:
08/21/2007
Application #:
10601252
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/23/2004
Title:
MEMORY HUB AND ACCESS METHOD HAVING INTERNAL PREFETCH BUFFERS
86
Patent #:
Issue Dt:
09/12/2006
Application #:
10601253
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/23/2004
Title:
POSTED WRITE BUFFERS AND METHODS OF POSTING WRITE REQUESTS IN MEMORY MODULES
87
Patent #:
Issue Dt:
09/06/2005
Application #:
10602324
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
01/13/2005
Title:
METHODS OF FORMING MEMORY CELLS HAVING SELF-ALIGNED SILICIDE
88
Patent #:
Issue Dt:
11/22/2005
Application #:
10608644
Filing Dt:
06/27/2003
Publication #:
Pub Dt:
01/01/2004
Title:
BOTTOM ANTIREFLECTION COATING COLOR FILTER PROCESS FOR FABRICATING SOLID STATE IMAGE SENSORS
89
Patent #:
Issue Dt:
11/01/2005
Application #:
10608743
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
12/30/2004
Title:
MEMORY DEVICE HAVING DATA PATHS WITH MULTIPLE SPEEDS
90
Patent #:
Issue Dt:
04/17/2007
Application #:
10609089
Filing Dt:
06/27/2003
Publication #:
Pub Dt:
12/30/2004
Title:
CAPACITOR LAYOUT ORIENTATION
91
Patent #:
Issue Dt:
08/22/2006
Application #:
10610556
Filing Dt:
07/02/2003
Publication #:
Pub Dt:
05/20/2004
Title:
CIRCUIT SUBSTRATES, SEMICONDUCTOR PACKAGES, AND BALL GRID ARRAYS
92
Patent #:
Issue Dt:
11/15/2005
Application #:
10612839
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
05/20/2004
Title:
METHODS OF FORMING CONDUCTIVE CAPACITOR PLUGS, METHODS OF FORMING CAPACITOR CONTACT OPENINGS, AND METHODS OF FORMING MEMORY ARRAYS
93
Patent #:
Issue Dt:
04/25/2006
Application #:
10613236
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
01/06/2005
Title:
TEMPERATURE SENSING DEVICE IN AN INTEGRATED CIRCUIT
94
Patent #:
Issue Dt:
09/06/2005
Application #:
10613237
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
03/04/2004
Title:
FLIP-CHIP IMAGE SENSOR PACKAGES AND METHODS OF FABRICATION
95
Patent #:
Issue Dt:
12/21/2004
Application #:
10613274
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
03/04/2004
Title:
FLIP-CHIP IMAGE SENSOR PACKAGES AND METHODS OF FABRICATION
96
Patent #:
Issue Dt:
10/18/2005
Application #:
10613277
Filing Dt:
07/03/2003
Publication #:
Pub Dt:
03/25/2004
Title:
FLIP-CHIP IMAGE SENSOR PACKAGES
97
Patent #:
Issue Dt:
12/27/2005
Application #:
10615003
Filing Dt:
07/08/2003
Title:
CONTINUOUS INTERLEAVE BURST ACCESS
98
Patent #:
Issue Dt:
08/16/2005
Application #:
10615325
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/08/2004
Title:
METHOD FOR BUS CAPACITANCE REDUCTION
99
Patent #:
Issue Dt:
08/15/2006
Application #:
10615326
Filing Dt:
07/07/2003
Publication #:
Pub Dt:
01/08/2004
Title:
METHOD FOR BUS CAPACITANCE REDUCTION
100
Patent #:
Issue Dt:
01/18/2005
Application #:
10616206
Filing Dt:
07/10/2003
Publication #:
Pub Dt:
06/03/2004
Title:
METHOD OF FORMING MINIMALLY SPACED WORD LINES
Assignor
1
Exec Dt:
12/23/2009
Assignee
1
26 DEER CREEK LANE
MT. KISCO, NEW YORK 10549
Correspondence name and address
CHRISTOPHER C. HENRY
ROPES & GRAY LLP
1211 AVENUE OF THE AMERICAS
NEW YORK, NEW YORK 10036

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