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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	023848/0183			Pages:	20
		Recorded:	01/26/2010
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 83

Patent #:	6503773	Issue Dt:	01/07/2003	Application #:	09761497	Filing Dt:	01/16/2001
Publication #:	US20010024884	Pub Dt:	09/27/2001
Title:	LOW THREADING DISLOCATION DENSITY RELAXED MISMATCHED EPILAYERS WITHOUT HIGH TEMPERATURE GROWTH

Patent #:	6518644	Issue Dt:	02/11/2003	Application #:	09761508	Filing Dt:	01/16/2001
Publication #:	US20020005514	Pub Dt:	01/17/2002
Title:	LOW THREADING DISLOCATION DENSITY RELAXED MISMATCHED EPILAYERS WITHOUT HIGH TEMPERATURE GROWTH

Patent #:	6750130	Issue Dt:	06/15/2004	Application #:	09764177	Filing Dt:	01/17/2001
Title:	HETEROINTEGRATION OF MATERIALS USING DEPOSITION AND BONDING

Patent #:	6602613	Issue Dt:	08/05/2003	Application #:	09764182	Filing Dt:	01/17/2001
Title:	HETEROINTEGRATION OF MATERIALS USING DEPOSITION AND BONDING

Patent #:	6589335	Issue Dt:	07/08/2003	Application #:	09779915	Filing Dt:	02/08/2001
Publication #:	US20020129762	Pub Dt:	09/19/2002
Title:	RELAXED INXGA1-XAS LAYERS INTEGRATED WITH SI

Patent #:	6594293	Issue Dt:	07/15/2003	Application #:	09779917	Filing Dt:	02/08/2001
Title:	RELAXED INXGA1-XAS LAYERS INTEGRATED WITH SI

Patent #:	6593191	Issue Dt:	07/15/2003	Application #:	09859137	Filing Dt:	05/16/2001
Publication #:	US20020052084	Pub Dt:	05/02/2002
Title:	BURIED CHANNEL STRAINED SILICON FET USING A SUPPLY LAYER CREATED THROUGH ION IMPLANTATION

Patent #:	6555839	Issue Dt:	04/29/2003	Application #:	09859138	Filing Dt:	05/16/2001
Publication #:	US20020017644	Pub Dt:	02/14/2002
Title:	BURIED CHANNEL STRAINED SILICON FET USING A SUPPLY LAYER CREATED THROUGH ION IMPLANTATION

Patent #:	6969875	Issue Dt:	11/29/2005	Application #:	09859139	Filing Dt:	05/16/2001
Publication #:	US20020030203	Pub Dt:	03/14/2002
Title:	BURIED CHANNEL STRAINED SILICON FET USING A SUPPLY LAYER CREATED THROUGH ION IMPLANTATION

Patent #:	6649480	Issue Dt:	11/18/2003	Application #:	09884172	Filing Dt:	06/19/2001
Publication #:	US20020123197	Pub Dt:	09/05/2002
Title:	METHOD OF FABRICATING CMOS INVERTER AND INTEGRATED CIRCUITS UTILIZING STRAINED SILICON SURFACE CHANNEL MOSFETS

Patent #:	6703688	Issue Dt:	03/09/2004	Application #:	09906200	Filing Dt:	07/16/2001
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6723661	Issue Dt:	04/20/2004	Application #:	09906201	Filing Dt:	07/16/2001
Publication #:	US20030077867	Pub Dt:	04/24/2003
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6646322	Issue Dt:	11/11/2003	Application #:	09906438	Filing Dt:	07/16/2001
Publication #:	US20030089901	Pub Dt:	05/15/2003
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6900103	Issue Dt:	05/31/2005	Application #:	09906533	Filing Dt:	07/16/2001
Publication #:	US20020123183	Pub Dt:	09/05/2002
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6830976	Issue Dt:	12/14/2004	Application #:	09906534	Filing Dt:	07/16/2001
Publication #:	US20020123167	Pub Dt:	09/05/2002
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6677192	Issue Dt:	01/13/2004	Application #:	09906545	Filing Dt:	07/16/2001
Title:	Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits

Patent #:	6593641	Issue Dt:	07/15/2003	Application #:	09906550	Filing Dt:	07/16/2001
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6724008	Issue Dt:	04/20/2004	Application #:	09906551	Filing Dt:	07/16/2001
Publication #:	US20020125497	Pub Dt:	09/12/2002
Title:	RELAXED SILICON GERMANIUM PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6677655	Issue Dt:	01/13/2004	Application #:	09920075	Filing Dt:	08/01/2001
Publication #:	US20020040983	Pub Dt:	04/11/2002
Title:	SILICON WAFER WITH EMBEDDED OPTOELECTRONIC MATERIAL FOR MONOLITHIC OEIC

Patent #:	6680495	Issue Dt:	01/20/2004	Application #:	09920519	Filing Dt:	08/01/2001
Publication #:	US20020068396	Pub Dt:	06/06/2002
Title:	SILICON WAFER WITH EMBEDDED OPTOELECTRONIC MATERIAL FOR MONOLITHIC OEIC

Patent #:	6645829	Issue Dt:	11/11/2003	Application #:	09920520	Filing Dt:	08/01/2001
Publication #:	US20020052061	Pub Dt:	05/02/2002
Title:	SILICON WAFER WITH EMBEDDED OPTOELECTRONIC MATERIAL FOR MONOLITHIC OEIC

Patent #:	6583015	Issue Dt:	06/24/2003	Application #:	09923207	Filing Dt:	08/06/2001
Publication #:	US20020068393	Pub Dt:	06/06/2002
Title:	GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES

Patent #:	7138649	Issue Dt:	11/21/2006	Application #:	10164665	Filing Dt:	06/07/2002
Publication #:	US20030227013	Pub Dt:	12/11/2003
Title:	DUAL-CHANNEL CMOS TRANSISTORS WITH DIFFERENTIALLY STRAINED CHANNELS

Patent #:	7615829	Issue Dt:	11/10/2009	Application #:	10164988	Filing Dt:	06/07/2002
Publication #:	US20030227029	Pub Dt:	12/11/2003
Title:	ELEVATED SOURCE AND DRAIN ELEMENTS FOR STRAINED-CHANNEL HETEROJUNTION FIELD-EFFECT TRANSISTORS

Patent #:	6849508	Issue Dt:	02/01/2005	Application #:	10165014	Filing Dt:	06/07/2002
Publication #:	US20030013287	Pub Dt:	01/16/2003
Title:	METHOD OF FORMING MULTIPLE GATE INSULATORS ON A STRAINED SEMICONDUCTOR HETEROSTRUCTURE

Patent #:	6900094	Issue Dt:	05/31/2005	Application #:	10172542	Filing Dt:	06/14/2002
Publication #:	US20030013323	Pub Dt:	01/16/2003
Title:	METHOD OF SELECTIVE REMOVAL OF SIGE ALLOYS

Patent #:	6982474	Issue Dt:	01/03/2006	Application #:	10179079	Filing Dt:	06/25/2002
Publication #:	US20030234439	Pub Dt:	12/25/2003
Title:	REACTED CONDUCTIVE GATE ELECTRODES

Patent #:	6680496	Issue Dt:	01/20/2004	Application #:	10191006	Filing Dt:	07/08/2002
Publication #:	US20040004230	Pub Dt:	01/08/2004
Title:	BACK-BIASING TO POPULATE STRAINED LAYER QUANTUM WELLS

Patent #:	6974735	Issue Dt:	12/13/2005	Application #:	10216085	Filing Dt:	08/09/2002
Publication #:	US20030057439	Pub Dt:	03/27/2003
Title:	DUAL LAYER CMOS DEVICES

Patent #:	6838728	Issue Dt:	01/04/2005	Application #:	10216091	Filing Dt:	08/09/2002
Publication #:	US20030052406	Pub Dt:	03/20/2003
Title:	BURIED-CHANNEL DEVICES AND SUBSTRATES FOR FABRICATION OF SEMICONDUCTOR-BASED DEVICES

Patent #:	6891209	Issue Dt:	05/10/2005	Application #:	10218007	Filing Dt:	08/13/2002
Publication #:	US20030030091	Pub Dt:	02/13/2003
Title:	DYNAMIC RANDOM ACCESS MEMORY TRENCH CAPACITORS

Patent #:	6831292	Issue Dt:	12/14/2004	Application #:	10251424	Filing Dt:	09/20/2002
Publication #:	US20030057416	Pub Dt:	03/27/2003
Title:	SEMICONDUCTOR STRUCTURES EMPLOYING STRAINED MATERIAL LAYERS WITH DEFINED IMPURITY GRADIENTS AND METHODS FOR FABRICATING SAME

Patent #:	6933518	Issue Dt:	08/23/2005	Application #:	10253361	Filing Dt:	09/24/2002
Publication #:	US20030102498	Pub Dt:	06/05/2003
Title:	RF CIRCUITS INCLUDING TRANSISTORS HAVING STRAINED MATERIAL LAYERS

Patent #:	6864115	Issue Dt:	03/08/2005	Application #:	10268025	Filing Dt:	10/09/2002
Publication #:	US20030113948	Pub Dt:	06/19/2003
Title:	LOW THREADING DISLOCATION DENSITY RELAXED MISMATCHED EPILAYERS WITHOUT HIGH TEMPERATURE GROWTH

Patent #:	7594967	Issue Dt:	09/29/2009	Application #:	10268425	Filing Dt:	10/10/2002
Publication #:	US20040040493	Pub Dt:	03/04/2004
Title:	REDUCTION OF DISLOCATION PILE-UP FORMATION DURING RELAXED LATTICE-MISMATCHED EPITAXY

Patent #:	7060632	Issue Dt:	06/13/2006	Application #:	10389003	Filing Dt:	03/14/2003
Publication #:	US20030215990	Pub Dt:	11/20/2003
Title:	METHODS FOR FABRICATING STRAINED LAYERS ON SEMICONDUCTOR SUBSTRATES

Patent #:	6703144	Issue Dt:	03/09/2004	Application #:	10391086	Filing Dt:	03/18/2003
Publication #:	US20030186073	Pub Dt:	10/02/2003
Title:	HETEROINTEGRATION OF MATERIALS USING DEPOSITION AND BONDING

Patent #:	7041170	Issue Dt:	05/09/2006	Application #:	10392338	Filing Dt:	03/19/2003
Publication #:	US20030230233	Pub Dt:	12/18/2003
Title:	METHOD OF PRODUCING HIGH QUALITY RELAXED SILICON GERMANIUM LAYERS

Patent #:	6846715	Issue Dt:	01/25/2005	Application #:	10421154	Filing Dt:	04/23/2003
Publication #:	US20030207571	Pub Dt:	11/06/2003
Title:	GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES

Patent #:	6995430	Issue Dt:	02/07/2006	Application #:	10456103	Filing Dt:	06/06/2003
Publication #:	US20040005740	Pub Dt:	01/08/2004
Title:	STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES

Patent #:	7074623	Issue Dt:	07/11/2006	Application #:	10456708	Filing Dt:	06/06/2003
Publication #:	US20040031979	Pub Dt:	02/19/2004
Title:	METHODS OF FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR FINFET DEVICE STRUCTURES

Patent #:	7138310	Issue Dt:	11/21/2006	Application #:	10456926	Filing Dt:	06/06/2003
Publication #:	US20040026765	Pub Dt:	02/12/2004
Title:	SEMICONDUCTOR DEVICES HAVING STRAINED DUAL CHANNEL LAYERS

Patent #:	6946371	Issue Dt:	09/20/2005	Application #:	10458544	Filing Dt:	06/10/2003
Publication #:	US20040045499	Pub Dt:	03/11/2004
Title:	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements

Patent #:	6881632	Issue Dt:	04/19/2005	Application #:	10611739	Filing Dt:	07/01/2003
Publication #:	US20040097025	Pub Dt:	05/20/2004
Title:	METHOD OF FABRICATING CMOS INVERTER AND INTEGRATED CIRCUITS UTILIZING STRAINED SURFACE CHANNEL MOSFETS

Patent #:	7375385	Issue Dt:	05/20/2008	Application #:	10646353	Filing Dt:	08/22/2003
Publication #:	US20040075105	Pub Dt:	04/22/2004
Title:	SEMICONDUCTOR HETEROSTRUCTURES HAVING REDUCED DISLOCATION PILE-UPS

Patent #:	7049627	Issue Dt:	05/23/2006	Application #:	10647074	Filing Dt:	08/22/2003
Publication #:	US20040087117	Pub Dt:	05/06/2004
Title:	SEMICONDUCTOR HETEROSTRUCTURES AND RELATED METHODS

Patent #:	6991972	Issue Dt:	01/31/2006	Application #:	10691007	Filing Dt:	10/22/2003
Publication #:	US20040137685	Pub Dt:	07/15/2004
Title:	GATE MATERIAL FOR SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7071014	Issue Dt:	07/04/2006	Application #:	10696994	Filing Dt:	10/30/2003
Publication #:	US20040092051	Pub Dt:	05/13/2004
Title:	METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING

Patent #:	7332417	Issue Dt:	02/19/2008	Application #:	10765372	Filing Dt:	01/27/2004
Publication #:	US20040214407	Pub Dt:	10/28/2004
Title:	SEMICONDUCTOR STRUCTURES WITH STRUCTURAL HOMOGENEITY

Patent #:	7501351	Issue Dt:	03/10/2009	Application #:	10774890	Filing Dt:	02/09/2004
Publication #:	US20040161947	Pub Dt:	08/19/2004
Title:	RELAXED SIGE PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	6960781	Issue Dt:	11/01/2005	Application #:	10794010	Filing Dt:	03/05/2004
Publication #:	US20040173812	Pub Dt:	09/09/2004
Title:	SHALLOW TRENCH ISOLATION PROCESS

Patent #:	7408214	Issue Dt:	08/05/2008	Application #:	10947909	Filing Dt:	09/23/2004
Publication #:	US20050035389	Pub Dt:	02/17/2005
Title:	DYNAMIC RANDOM ACCESS MEMORY TRENCH CAPACITORS

Patent #:	7410861	Issue Dt:	08/12/2008	Application #:	10966959	Filing Dt:	10/15/2004
Publication #:	US20050067647	Pub Dt:	03/31/2005
Title:	METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY TRENCH CAPACITORS

Patent #:	7256142	Issue Dt:	08/14/2007	Application #:	10967998	Filing Dt:	10/19/2004
Publication #:	US20050077511	Pub Dt:	04/14/2005
Title:	RELAXED SIGE PLATFORM FOR HIGH SPEED CMOS ELECTRONICS AND HIGH SPEED ANALOG CIRCUITS

Patent #:	7393733	Issue Dt:	07/01/2008	Application #:	11001166	Filing Dt:	12/01/2004
Publication #:	US20060113605	Pub Dt:	06/01/2006
Title:	METHODS OF FORMING HYBRID FIN FIELD-EFFECT TRANSISTOR STRUCTURES

Patent #:	7217668	Issue Dt:	05/15/2007	Application #:	11013838	Filing Dt:	12/16/2004
Publication #:	US20050202640	Pub Dt:	09/15/2005
Title:	GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES

Patent #:	7172935	Issue Dt:	02/06/2007	Application #:	11015266	Filing Dt:	12/17/2004
Publication #:	US20050098774	Pub Dt:	05/12/2005
Title:	METHOD OF FORMING MULTIPLE GATE INSULATORS ON A STRAINED SEMICONDUCTOR HETEROSTRUCTURE

Patent #:	7217603	Issue Dt:	05/15/2007	Application #:	11073976	Filing Dt:	03/07/2005
Publication #:	US20050156210	Pub Dt:	07/21/2005
Title:	METHODS OF FORMING REACTED CONDUCTIVE GATE ELECTRODES

Patent #:	7122449	Issue Dt:	10/17/2006	Application #:	11103681	Filing Dt:	04/12/2005
Publication #:	US20050176204	Pub Dt:	08/11/2005
Title:	METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES HAVING EPITAXIALLY GROWN SOURCE AND DRAIN ELEMENTS

Patent #:	7259388	Issue Dt:	08/21/2007	Application #:	11120675	Filing Dt:	05/03/2005
Publication #:	US20050189563	Pub Dt:	09/01/2005
Title:	STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES

Patent #:	7420201	Issue Dt:	09/02/2008	Application #:	11125507	Filing Dt:	05/10/2005
Publication #:	US20050218453	Pub Dt:	10/06/2005
Title:	STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH ELEVATED SOURCE/DRAIN REGIONS

Patent #:	7414259	Issue Dt:	08/19/2008	Application #:	11126550	Filing Dt:	05/11/2005
Publication #:	US20050205934	Pub Dt:	09/22/2005
Title:	STRAINED GERMANIUM-ON-INSULATOR DEVICE STRUCTURES

Patent #:	7297612	Issue Dt:	11/20/2007	Application #:	11127508	Filing Dt:	05/12/2005
Publication #:	US20050212061	Pub Dt:	09/29/2005
Title:	METHODS FOR FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES BY USE OF CLEAVE PLANES

Patent #:	7588994	Issue Dt:	09/15/2009	Application #:	11128628	Filing Dt:	05/13/2005
Publication #:	US20050199954	Pub Dt:	09/15/2005
Title:	METHODS FOR FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES BY MECHANICALLY INDUCING STRAIN

Patent #:	7465619	Issue Dt:	12/16/2008	Application #:	11130575	Filing Dt:	05/17/2005
Publication #:	US20050221550	Pub Dt:	10/06/2005
Title:	METHODS OF FABRICATING DUAL LAYER SEMICONDUCTOR DEVICES

Patent #:	7504704	Issue Dt:	03/17/2009	Application #:	11130584	Filing Dt:	05/17/2005
Publication #:	US20050205859	Pub Dt:	09/22/2005
Title:	SHALLOW TRENCH ISOLATION PROCESS

Patent #:	7208332	Issue Dt:	04/24/2007	Application #:	11132856	Filing Dt:	05/19/2005
Publication #:	US20050215069	Pub Dt:	09/29/2005
Title:	METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING

Patent #:	7432139	Issue Dt:	10/07/2008	Application #:	11170250	Filing Dt:	06/29/2005
Publication #:	US20070004224	Pub Dt:	01/04/2007
Title:	METHODS FOR FORMING DIELECTRICS AND METAL ELECTRODES

Patent #:	7109516	Issue Dt:	09/19/2006	Application #:	11211933	Filing Dt:	08/25/2005
Publication #:	US20050280103	Pub Dt:	12/22/2005
Title:	STRAINED-SEMICONDUCTOR-ON-INSULATOR FINFET DEVICE STRUCTURES

Patent #:	7638842	Issue Dt:	12/29/2009	Application #:	11220482	Filing Dt:	09/07/2005
Publication #:	US20070054465	Pub Dt:	03/08/2007
Title:	LATTICE-MISMATCHED SEMICONDUCTOR STRUCTURES ON INSULATORS

Patent #:	7307273	Issue Dt:	12/11/2007	Application #:	11227472	Filing Dt:	09/15/2005
Publication #:	US20060011984	Pub Dt:	01/19/2006
Title:	CONTROL OF STRAIN IN DEVICE LAYERS BY SELECTIVE RELAXATION

Patent #:	7335545	Issue Dt:	02/26/2008	Application #:	11227529	Filing Dt:	09/15/2005
Publication #:	US20060014366	Pub Dt:	01/19/2006
Title:	CONTROL OF STRAIN IN DEVICE LAYERS BY PREVENTION OF RELAXATION

Patent #:	7368308	Issue Dt:	05/06/2008	Application #:	11227770	Filing Dt:	09/15/2005
Publication #:	US20060009012	Pub Dt:	01/12/2006
Title:	METHODS OF FABRICATING SEMICONDUCTOR HETEROSTRUCTURES

Patent #:	7074655	Issue Dt:	07/11/2006	Application #:	11237175	Filing Dt:	09/28/2005
Publication #:	US20060024869	Pub Dt:	02/02/2006
Title:	GATE MATERIAL FOR SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7259108	Issue Dt:	08/21/2007	Application #:	11362892	Filing Dt:	02/27/2006
Publication #:	US20060148225	Pub Dt:	07/06/2006
Title:	METHODS FOR FABRICATING STRAINED LAYERS ON SEMICONDUCTOR SUBSTRATES

Patent #:	7202121	Issue Dt:	04/10/2007	Application #:	11371687	Filing Dt:	03/09/2006
Publication #:	US20070042538	Pub Dt:	02/22/2007
Title:	METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING

Patent #:	7326599	Issue Dt:	02/05/2008	Application #:	11436281	Filing Dt:	05/18/2006
Publication #:	US20060258075	Pub Dt:	11/16/2006
Title:	GATE MATERIAL FOR SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7439164	Issue Dt:	10/21/2008	Application #:	11489787	Filing Dt:	07/20/2006
Publication #:	US20060258125	Pub Dt:	11/16/2006
Title:	METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES HAVING EPITAXIALLY GROWN SOURCE AND DRAIN ELEMENTS

Patent #:	7626246	Issue Dt:	12/01/2009	Application #:	11493365	Filing Dt:	07/26/2006
Publication #:	US20070181977	Pub Dt:	08/09/2007
Title:	SOLUTIONS FOR INTEGRATED CIRCUIT INTEGRATION OF ALTERNATIVE ACTIVE AREA MATERIALS

Patent #:	7566606	Issue Dt:	07/28/2009	Application #:	11544245	Filing Dt:	10/06/2006
Publication #:	US20070032009	Pub Dt:	02/08/2007
Title:	METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING STRAINED DUAL CHANNEL LAYERS

Patent #:	7416909	Issue Dt:	08/26/2008	Application #:	11702825	Filing Dt:	02/06/2007
Publication #:	US20070161196	Pub Dt:	07/12/2007
Title:	METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING

Patent #:	7541208	Issue Dt:	06/02/2009	Application #:	11704464	Filing Dt:	02/09/2007
Publication #:	US20080020551	Pub Dt:	01/24/2008
Title:	METHODS FOR PRESERVING STRAINED SEMICONDUCTOR SUBSTRATE LAYERS DURING CMOS PROCESSING

Patent #:	7494881	Issue Dt:	02/24/2009	Application #:	11945130	Filing Dt:	11/26/2007
Publication #:	US20080070397	Pub Dt:	03/20/2008
Title:	METHODS FOR SELECTIVE PLACEMENT OF DISLOCATION ARRAYS

Assignor

AMBERWAVE SYSTEMS CORPORATION

Exec Dt:

11/22/2009

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

NO. 8, LI-HSIN RD. 6

SCIENCE-BASED INDUSTRIAL PARK

HSIN-CHU, TAIWAN 300-77

Correspondence name and address
	SLATER & MATSIL, L.L.P.
	17950 PRESTON ROAD, SUITE 1000
	DALLAS, TX 75252

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