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Total properties:
63
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07/23/2002
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08946810
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Filing Dt:
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10/08/1997
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Title:
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UNIT FOR PROCESSING NUMERICAL AND LOGICAL OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA -FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
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06/27/2000
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08946812
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Filing Dt:
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10/08/1997
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Title:
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METHOD OF THE SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
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02/01/2000
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10/08/1997
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Title:
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03/14/2000
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08946999
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Filing Dt:
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10/08/1997
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Title:
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06/11/2002
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08/28/1998
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Title:
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02/06/2007
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Filing Dt:
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01/31/2000
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Title:
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RUN-TIME RECONFIGURATION METHOD FOR PROGRAMMABLE UNITS
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Patent #:
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02/24/2004
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09598926
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Filing Dt:
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06/21/2000
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Title:
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METHOD OF REPAIRING INTEGRATED CIRCUITS
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Patent #:
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11/12/2002
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09623052
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Filing Dt:
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01/09/2001
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Title:
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05/27/2003
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01/09/2001
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Title:
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09/10/2002
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09822265
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04/02/2001
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Publication #:
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Pub Dt:
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08/16/2001
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Title:
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09/04/2007
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09967497
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09/28/2001
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03/06/2003
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Title:
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04/24/2007
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09967847
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09/28/2001
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03/20/2003
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Title:
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METHOD FOR TRANSLATING PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
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07/24/2012
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10009649
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05/29/2002
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Title:
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03/07/2006
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10116986
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04/05/2002
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07/17/2003
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Title:
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INTERNAL BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES, FOR MANAGING LARGE VOLUMES OF DATA WITH A HIGH INTERCONNECTION COMPLEXITY
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02/03/2004
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10191926
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07/09/2002
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04/17/2003
| | | | |
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Title:
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METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO-OR
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02/21/2006
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06/19/2003
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02/05/2004
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04/13/2004
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11/26/2002
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05/22/2003
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Title:
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11/22/2005
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10373595
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02/24/2003
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
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Patent #:
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04/25/2006
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10379403
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03/04/2003
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04/29/2004
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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10/28/2008
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09/21/2004
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Pub Dt:
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03/24/2005
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Title:
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Patent #:
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NONE
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10469910
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02/17/2005
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12/27/2007
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08/25/2009
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10/29/2004
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04/21/2005
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02/02/2010
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06/18/2004
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12/02/2004
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08/09/2011
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09/20/2004
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04/21/2005
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08/18/2009
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08/05/2004
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12/09/2004
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Title:
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01/20/2009
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08/25/2004
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01/27/2005
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10/07/2008
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11/02/2004
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03/10/2005
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04/23/2013
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11/29/2004
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11/02/2006
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10/02/2012
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08/26/2005
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04/27/2006
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10501903
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03/01/2005
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06/16/2005
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02/28/2012
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11/22/2005
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08/02/2005
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03/01/2007
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08/28/2006
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04/25/2006
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04/12/2007
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11/30/2010
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11/10/2006
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05/17/2007
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09/16/2004
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01/24/2006
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01/23/2004
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11/17/2005
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Title:
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07/21/2009
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03/01/2004
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08/26/2004
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07/10/2007
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10/07/2004
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10/30/2012
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10/26/2010
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10/07/2005
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02/09/2006
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04/10/2012
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06/19/2007
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01/10/2008
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02/26/2008
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06/20/2007
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11/01/2007
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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02/11/2008
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01/29/2009
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11/23/2010
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11890094
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08/03/2007
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01/01/2009
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01/19/2010
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01/10/2008
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09/11/2008
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10/13/2009
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04/07/2008
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08/14/2008
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08/21/2012
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12087916
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12/02/2008
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08/06/2009
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07/16/2013
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04/24/2008
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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06/26/2012
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10/07/2008
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02/05/2009
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01/17/2012
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10/23/2008
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04/16/2009
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METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
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03/27/2012
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10/24/2008
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06/04/2009
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Title:
|
DATA PROCESSING DEVICE AND METHOD
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Patent #:
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Issue Dt:
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11/29/2011
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Application #:
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12354590
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Filing Dt:
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01/15/2009
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Publication #:
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Pub Dt:
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06/11/2009
| | | | |
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Title:
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METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12367055
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Filing Dt:
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02/06/2009
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Publication #:
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Pub Dt:
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06/04/2009
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12368709
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Filing Dt:
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02/10/2009
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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A CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE CELLS THAT INCLUDE MULTI-BIT-WIDE INPUTS AND OUTPUTS
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12371040
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Filing Dt:
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02/13/2009
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Publication #:
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Pub Dt:
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06/11/2009
| | | | |
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Title:
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LOGIC CELL ARRAY AND BUS SYSTEM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12389116
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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METHOD AND DEVICE FOR TREATING AND PROCESSING DATA
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12389155
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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06/18/2009
| | | | |
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12389174
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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07/16/2009
| | | | |
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Title:
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ELECTRON BEAM APPLYING APPARATUS AND DRAWING APPARATUS
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Patent #:
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Issue Dt:
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Application #:
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UNAVAILABLE
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Filing Dt:
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Title:
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