|
Total properties:
60
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|
|
Patent #:
|
|
Issue Dt:
|
12/05/1995
|
Application #:
|
08239608
|
Filing Dt:
|
05/09/1994
|
|
Title:
|
SINGLE CHIP CONTROLLER-MEMORY DEVICE AND A MEMORY ARCHITECTURE AND METHODS SUITABLE FOR IMPLEMENTING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/1995
|
Application #:
|
08288442
|
Filing Dt:
|
08/10/1994
|
|
Title:
|
DIGITAL VOLTAGE SHIFTERS AND SYSTEMS USING THE SAME
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/19/1995
|
Application #:
|
08288580
|
Filing Dt:
|
08/10/1994
|
|
Title:
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ELECTRONIC MEMORY AND METHODS FOR MAKING AND USING THE SAME
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|
|
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|
Patent #:
|
|
Issue Dt:
|
04/09/1996
|
Application #:
|
08291093
|
Filing Dt:
|
08/16/1994
|
|
Title:
|
DUAL BANK MEMORY AND SYSTEMS USING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/1995
|
Application #:
|
08291155
|
Filing Dt:
|
08/16/1994
|
|
Title:
|
CIRCUITS AND METHODS FOR REFRESHING A DUAL BANK MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/1995
|
Application #:
|
08304508
|
Filing Dt:
|
09/12/1994
|
|
Title:
|
MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/1996
|
Application #:
|
08315934
|
Filing Dt:
|
09/30/1994
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR IMPROVING PAGE ACCESSES AND BLOCK TRANSFERS IN A MEMORY SYSTEM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/1997
|
Application #:
|
08381189
|
Filing Dt:
|
01/31/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR IMPROVING ROW SELECT SPEED IN A ROW SELECT MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1997
|
Application #:
|
08387218
|
Filing Dt:
|
02/13/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR TESTING ASIC AND RAM MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08410868
|
Filing Dt:
|
03/27/1995
|
|
Title:
|
A MULTI-BIT DATA STORAGE LOCATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08410869
|
Filing Dt:
|
03/27/1995
|
|
Title:
|
FABRICATING A MULTI-BIT STORAGE CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08420138
|
Filing Dt:
|
04/11/1995
|
|
Title:
|
BUS DRIVER/RECEIVER CIRCUITRY AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/1996
|
Application #:
|
08423825
|
Filing Dt:
|
04/19/1995
|
|
Title:
|
CONTINUOUS PAGE RANDOM ACCESS MEMORY AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
08424653
|
Filing Dt:
|
04/19/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR MODIFYING DATA STORED IN A MEMORY USING LOGIC OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08434656
|
Filing Dt:
|
05/04/1995
|
|
Title:
|
HIGH PERFORMANCE BUS DRIVING/RECEIVING CIRCUITS, SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1996
|
Application #:
|
08497267
|
Filing Dt:
|
06/30/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR TESTING INTEGRATED CIRCUIT DEVICES INCLUDING LOGIC AND MEMORY CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08502479
|
Filing Dt:
|
07/14/1995
|
|
Title:
|
PIPELAND ADDRESS MEMORIES, AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/1996
|
Application #:
|
08521867
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
LOW PIN COUNT-WIDE MEMORY DEVICES AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/1997
|
Application #:
|
08521891
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR CONTROLLING SUBSTRATE BIAS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08531755
|
Filing Dt:
|
09/21/1995
|
|
Title:
|
MEMORY ARCHITECTURE AND DEVICES, SYSTEMS AND METHODS UTILIZING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2000
|
Application #:
|
08534279
|
Filing Dt:
|
09/27/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR MEMORY MAPPING AND DISPLAY CONTROL SYSTEMS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08538903
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
MEMORY DEVICES WITH SELECTABLE ACCESS TYPE AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08543210
|
Filing Dt:
|
10/13/1995
|
|
Title:
|
CIRCUITS SYSTEMS AND METHODS FOR REDUCING POWER LOSS DURING TRANSFER OF DATA ACROSS A CONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08548752
|
Filing Dt:
|
10/26/1995
|
|
Title:
|
MULTIPLE-BANK MEMORY ARCHITECTURE AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08551526
|
Filing Dt:
|
11/01/1995
|
|
Title:
|
SINGLE CHIP CONTROLLER-MEMORY DEVICE AND A MEMORY ARCHITECTURE AND METHODS SUITABLE FOR IMPLEMENTING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08552197
|
Filing Dt:
|
11/02/1995
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR INTERFACING PROCESSING CIRCUITRY WITH A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/1996
|
Application #:
|
08554297
|
Filing Dt:
|
11/06/1995
|
|
Title:
|
A DUAL BANK MEMORY SYSTEM WITH OUTPUT MULTIPLEXING AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08559379
|
Filing Dt:
|
11/16/1995
|
|
Title:
|
MEMORY ARCHITECTURE USING CONTENT ADDRESSABLE MEMORY, AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08565388
|
Filing Dt:
|
11/30/1995
|
|
Title:
|
MULTI-BANK MEMORY SYSTEM AND METHOD HAVING ADDRESSES SWITCHED BETWEEN THE ROW AND COLUMN DECODERS IN DIFFERENT BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/1997
|
Application #:
|
08584565
|
Filing Dt:
|
01/11/1996
|
|
Title:
|
FAST CYCLE TIME-LOW LATENCY DYNAMIC RANDOM ACCESS MEMORIES AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08591864
|
Filing Dt:
|
01/25/1996
|
|
Title:
|
CIRCUITS SYSTEMS AND METHODS FOR REDUCING POWER LOSS DURING TRANSFER OF DATA ACROSS AN I/O BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/1997
|
Application #:
|
08595236
|
Filing Dt:
|
02/01/1996
|
|
Title:
|
SINGLE CHIP CONTROLLER-MEMORY DEVICE WITH INTERBANK CELL REPLACEMENT CAPABILITY AND A MEMORY ARCHITECTURE AND METHODS SUITABLE FOR IMPLEMENTING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08612113
|
Filing Dt:
|
03/07/1996
|
|
Title:
|
LOW PIN COUNT-WIDE MEMORY DEVICES USING NON-MULTIPLEXED ADDRESSING AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/1997
|
Application #:
|
08613316
|
Filing Dt:
|
03/11/1996
|
|
Title:
|
SYSTEMS AND METHODS FOR IMPLEMENTING INTER-DEVICE CELL REPLACEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/1997
|
Application #:
|
08620115
|
Filing Dt:
|
03/21/1996
|
|
Title:
|
CIRCUITS SYSTEMS AND METHODS FOR REDUCING POWER LOSS DURING TRANSFER OF DATA ACROSS A CONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08633574
|
Filing Dt:
|
04/17/1996
|
|
Title:
|
A MEMORY DIVICE WITH AN EXTERNALLY SELECTABLE-WIDTH I/O PORT AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08637073
|
Filing Dt:
|
04/24/1996
|
|
Title:
|
MEMORY SYSTEM WITH MULTIPLEXED INPUT-OUTPUT PORT AND MEMORY MAPPING CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08638953
|
Filing Dt:
|
04/24/1996
|
|
Title:
|
MEMORY SYSTEM WITH MULTIPLEXED INPUT-OUTPUT PORT AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08641708
|
Filing Dt:
|
05/02/1996
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR THE HIGH SPEED TRANSFER OF DATA ACROSS A CONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08641887
|
Filing Dt:
|
05/02/1996
|
|
Title:
|
MEMORY BANKS WITH PIPELINING OF ADDRESS WORDS DURING PRECHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08645021
|
Filing Dt:
|
05/15/1996
|
|
Title:
|
DISPLAY CONTROLLER WITH INTEGRATED HALF FRAME BUFFER AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08659664
|
Filing Dt:
|
06/06/1996
|
|
Title:
|
MEMORIES WITH PROGRAMMABLE ADDRESS DECODING AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08664471
|
Filing Dt:
|
06/14/1996
|
|
Title:
|
PIPELINED ADDRESS MEMORIES, AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/1997
|
Application #:
|
08666683
|
Filing Dt:
|
06/14/1996
|
|
Title:
|
PIPELINED ADDRESS MEMORIES, AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08666814
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
"MULTIBANK - MULTIPORT MEMORIES AND SYSTEMS AND METHODS USING THE SAME"
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08666815
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
DUAL PORT MEMORIES AND SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08677125
|
Filing Dt:
|
07/09/1996
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHOD FOR ADDRESS MAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08681661
|
Filing Dt:
|
07/29/1996
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR TRANSFERRING DATA ACROSS A CONDUCTIVE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
08726568
|
Filing Dt:
|
10/04/1996
|
|
Title:
|
CIRCUITS, SYSTEMS, AND METHODS FOR ACCOUNTING FOR DEFECTIVE CELLS IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08759764
|
Filing Dt:
|
12/03/1996
|
|
Title:
|
DIGITAL STEP GENERATORS AND CIRCUITS, SYSTEMS AND METHODS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
08843569
|
Filing Dt:
|
04/18/1997
|
|
Title:
|
SYSTEM AND METHODS FOR PASSIVELY TRANSFERRING DATA ACROSS A SELECTED SINGLE BUS LINE INDEPENDENT OF A CONTROL CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
08862325
|
Filing Dt:
|
05/23/1997
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR GRAPHICS AND VIDEO WINDOW/DISPLAY DATA BLOCK TRANSFER VIA DEDICATED MEMORY CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
08864506
|
Filing Dt:
|
05/28/1997
|
|
Title:
|
METHOD AND APPARATUS FOR TRANSFERRING DATA IN A DUAL PORT MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08902674
|
Filing Dt:
|
07/30/1997
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR MODIFYING DATA STORED IN A MEMORY USING LOGIC OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08903317
|
Filing Dt:
|
07/30/1997
|
|
Title:
|
SENSING CIRCUITRY WITH BOOLEAN LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/1999
|
Application #:
|
08903390
|
Filing Dt:
|
07/30/1997
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR MODIFYING DATA STORED IN A MEMORY USING LOGIC OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09045757
|
Filing Dt:
|
03/19/1998
|
|
Title:
|
CIRCUITRY AND METHODS FOR DYNAMICALLY SENSING OF DATA IN A STATIC RANDOM ACCESS MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09066618
|
Filing Dt:
|
04/24/1998
|
|
Title:
|
CIRCUITS, SYSTEMS AND METHODS FOR MEMORY MAPPING AND DISPLAY CONTROL SYSTEMS USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
09088535
|
Filing Dt:
|
06/01/1998
|
|
Title:
|
DYNAMIC RANDOM ACCESS MEMORY WITH A NORMAL PRECHARGE MODE AND A PRIORTY PRECHARGE MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09088649
|
Filing Dt:
|
06/01/1998
|
|
Title:
|
MEMORY WITH PIPELINED ACCESSED AND PRIORITY PRECHARGE
|
|
