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Total properties:
39
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|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1993
|
Application #:
|
07644902
|
Filing Dt:
|
01/23/1991
|
|
Title:
|
OUTPUT CONTROL CIRCUIT HAVING CONTINUOUSLY VARIABLE DRIVE CURRENT
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|
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|
Patent #:
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|
Issue Dt:
|
07/28/1992
|
Application #:
|
07644903
|
Filing Dt:
|
01/23/1991
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|
Title:
|
CURRENT SUPPLY CIRCUIT FOR DRIVING HIGH CAPACITANCE LOAD IN AN INTEGRATED CIRCUIT
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|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/1992
|
Application #:
|
07644904
|
Filing Dt:
|
01/23/1991
|
|
Title:
|
REFERENCE GENERATOR FOR AN INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08267278
|
Filing Dt:
|
06/28/1994
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|
Title:
|
PROCESS FOR FABRICATING TRANSISTORS USING COMPOSITE NITRIDE STRUCTURE
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|
|
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Patent #:
|
|
Issue Dt:
|
10/15/1996
|
Application #:
|
08284384
|
Filing Dt:
|
08/02/1994
|
|
Title:
|
CIRCUIT WITH A SINGLE ADDRESS REGISTER THAT AUGMENTS A MEMORY CONTROLLER BY ENABLING CACHE READS AND PAGE-MODE WRITES
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|
|
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Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08319289
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Filing Dt:
|
10/06/1994
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|
Title:
|
ENHANCED DRAM WITH ALL READS FROM ON-CHIP CACHE AND ALL WRITERS TO MEMORY ARRAY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08460665
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
ENHANCED DRAM WITH SINGLE ROW SRAM CACHE FOR ALL DEVICE READ OPERATIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08620450
|
Filing Dt:
|
03/22/1996
|
|
Title:
|
EDRAM WITH INTEGRATED GENERATION AND CONTROL OF WRITE ENABLE AND COLUMN LATCH SIGNALS AND METHOD FOR MAKING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/1998
|
Application #:
|
08731790
|
Filing Dt:
|
10/18/1996
|
|
Title:
|
CACHED SYNCHRONOUS DRAM ARCHITECTURE ALLOWING CONCURRENT DRAM OPERATIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08840118
|
Filing Dt:
|
04/01/1997
|
|
Title:
|
FIRST-IN, FIRST-OUT INTEGRATED CIRCUIT MEMORY DEVICE UTILIZING A DYNAMIC RANDOM ACCESS MEMORY ARRAY FOR DATA STORAGE IMPLEMENTED IN CONJUCTION WITH AN ASSOCIATED STATIC RANDOM ACCESS MEMORY CACHE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08850802
|
Filing Dt:
|
05/02/1997
|
|
Title:
|
ENHANCED SIGNAL PROCESSING RANDOM ACCESS MEMORY DEVICE UTILIZING A DRAM MEMORY ARRAY INTEGRATED WITH AN ASSOCIATED SRAM CACHE AND INTERNAL REFRESH CONTROL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08888371
|
Filing Dt:
|
07/03/1997
|
|
Title:
|
ENHANCED DRAM WITH EMBEDDED REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09069468
|
Filing Dt:
|
04/29/1998
|
|
Title:
|
TECHNIQUE FOR REDUCING ELEMENT DISABLE FUSE PITCH REQUIREMENTS IN AN INTEGRATED CIRCUIT DEVICE INCORPORATING REPLACEABLE CIRCUIT ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09108089
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
EMBEDDED ENHANCED DRAM, AND ASSOCIATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09111822
|
Filing Dt:
|
07/08/1998
|
|
Title:
|
MULTI-ARRAY MEMORY DEVICE, AND ASSOCIATED METHOD, HAVING SHARED DECODER CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
09146726
|
Filing Dt:
|
09/03/1998
|
|
Title:
|
DYNAMIC RANDOM ACCESS MEMORY WORD LINE BOOST TECHNIQUE EMPLOYING A BOOST-ON-WRITES POLICY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09178298
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
MULTI-BANK ESDRAM WITH CROSS -COUPLED SRAM CACHE REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09182994
|
Filing Dt:
|
10/30/1998
|
|
Title:
|
ENHANCED DRAM WITH EMBEDDED REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09236804
|
Filing Dt:
|
01/29/1999
|
|
Title:
|
DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY DEVICE INCORPORATING A STATIC RAM CACHE PER MEMORY BANK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
09266472
|
Filing Dt:
|
03/11/1999
|
|
Title:
|
FIRST-IN, FIRST-OUT INTEGRATED CIRCUIT MEMORY DEVICE INCORPORATING A RETRANSMIT FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09360373
|
Filing Dt:
|
10/15/1999
|
|
Title:
|
CACHED SYNCHRONOUS DRAM ARCHITECTURE HAVING A MODE REGISTER PROGRAMMABLE CACHE POLICY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09515007
|
Filing Dt:
|
02/29/2000
|
|
Title:
|
Enhanced bus turnaround integrated circuit dynamic random access memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09533923
|
Filing Dt:
|
03/23/2000
|
|
Title:
|
Multi-array memory device, and associated method, having shared decoder circuitry
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09536072
|
Filing Dt:
|
03/24/2000
|
|
Title:
|
First-In, first-out integrated circuit memory device incorporating a retransmit function
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09571135
|
Filing Dt:
|
05/15/2000
|
|
Title:
|
PACKET-BASED INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY DEVICE INCORPORATING AN ON-CHIP ROW REGISTER CACHE TO REDUCE DATA ACCESS LATENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09593111
|
Filing Dt:
|
06/13/2000
|
|
Title:
|
FAST RESPONSE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09626623
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
Enhanced bus turnaround integrated circuit dynamic random access memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09689219
|
Filing Dt:
|
10/11/2000
|
|
Title:
|
METHOD FOR REDUCING THE WIDTH OF A GLOBAL DATA BUS IN A MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09703765
|
Filing Dt:
|
11/01/2000
|
|
Title:
|
STRUCTURE AND METHOD FOR HIDING DRAM CYCLE TIME BEHIND A BURST ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
09828283
|
Filing Dt:
|
04/05/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
|
Title:
|
METHOD FOR HIDING A REFRESH IN A PSEUDO-STATIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
09962287
|
Filing Dt:
|
09/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
|
Title:
|
ENHANCED DRAM WITH EMBEDDED REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
10080399
|
Filing Dt:
|
02/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/03/2002
| | | | |
|
Title:
|
PACKET-BASED INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY DEVICE INCORPORATING AN ON-CHIP ROW REGISTER CACHE TO REDUCE DATA ACCESS LATENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10178072
|
Filing Dt:
|
06/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/25/2003
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR INCREASING THE MEMORY ACCESS SPEED OF AN ENHANCED SYNCHRONOUS SDRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10346330
|
Filing Dt:
|
01/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2003
| | | | |
|
Title:
|
PACKET-BASED INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY DEVICE INCORPORATING AN ON-CHIP ROW REGISTER CACHE TO REDUCE DATA ACCESS LATENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10782386
|
Filing Dt:
|
02/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR INCREASING THE MEMORY ACCESS SPEED OF AN ENHANCED SYNCHRONOUS SDRAM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
10965602
|
Filing Dt:
|
10/13/2004
|
|
Title:
|
METHOD AND CIRCUIT FOR INCREASING THE MEMORY ACCESS SPEED OF AN ENHANCED SYNCHRONOUS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11238182
|
Filing Dt:
|
09/27/2005
|
|
Title:
|
METHOD FOR HIDING A REFRESH IN A PSEUDO-STATIC MEMORY WITH PLURAL DRAM SUB-ARRAYS AND AN ON-BOARD ADDRESS DECODER
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12116097
|
Filing Dt:
|
05/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
|
Title:
|
Enhanced DRAM with Embedded Registers
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
03/30/2010
|
Application #:
|
12273437
|
Filing Dt:
|
11/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
|
Title:
|
METHOD FOR HIDING A REFRESH IN A PSEUDO-STATIC MEMORY
|
|
