|
Total properties:
26
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/1996
|
Application #:
|
08252284
|
Filing Dt:
|
05/31/1994
|
|
Title:
|
REDUNDANCY SCHEME FOR MEMORY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/1995
|
Application #:
|
08297723
|
Filing Dt:
|
08/26/1994
|
|
Title:
|
FAST VOLTAGE EQUILIBRATION OF COMPLEMENTARY DATA LINES FOLLOWING WRITE CYCLE IN MEMORY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/1996
|
Application #:
|
08438148
|
Filing Dt:
|
05/09/1995
|
|
Title:
|
FAST VOLTAGE EQUILIBRATION OF DIFFERENTIAL DATA LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08630283
|
Filing Dt:
|
04/10/1996
|
|
Title:
|
POWER BUSSING LAYOUT FOR MEMORY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08630310
|
Filing Dt:
|
04/10/1996
|
|
Title:
|
WORD LINE DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08656165
|
Filing Dt:
|
05/31/1996
|
|
Title:
|
SHARED BOOTSTRAP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08890584
|
Filing Dt:
|
07/09/1997
|
|
Title:
|
SELF ADJUSTING DELAY CIRCUIT AND METHOD FOR COMPENSATING SENSE AMPLIFIER CLOCK TIMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09199884
|
Filing Dt:
|
11/24/1998
|
|
Title:
|
DISABLING A DEFECTIVE ELEMENT IN AN INTEGRATED CIRCUIT DEVICE HAVING REDUNDANT ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09285232
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
BIT LINE CROSS-OVER LAYOUT ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09287948
|
Filing Dt:
|
04/07/1999
|
|
Title:
|
DISABLING A DECODER FOR A DEFECTIVE ELEMENT IN AN INTEGRATED CIRCUIT DEVICE HAVING REDUNDANT ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09329975
|
Filing Dt:
|
06/10/1999
|
|
Title:
|
HIERARCHICAL DYNAMIC MEMORY ARRAY ARCHITECTURE USING READ AMPLIFIERS SEPARATE FROM BIT LINE SENSE AMPLIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09372320
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
DYNAMIC MEMORY ARRAY HAVING WRITE DATA APPLIED TO SELECTED BIT LINE SENSE AMPLIFIERS BEFORE SENSING TO WRITE ASSOCIATED SELECTED MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
09439061
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
HIGH SPEED VIDEO FRAME BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09451042
|
Filing Dt:
|
11/30/1999
|
|
Title:
|
EQUILIBRATION CIRCUIT AND METHOD USING A PULSED EQUILIBRATE SIGNAL AND A LEVEL EQUILIBRATE SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09474351
|
Filing Dt:
|
12/29/1999
|
|
Title:
|
PROGRAMMABLE AND ELECTRICALLY CONFIGURABLE LATCH TIMING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09499265
|
Filing Dt:
|
02/07/2000
|
|
Title:
|
Word line straps using two differentlayers of metal
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09502983
|
Filing Dt:
|
02/11/2000
|
|
Title:
|
Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09503048
|
Filing Dt:
|
02/12/2000
|
|
Title:
|
Merging write cycles by comparing at least a portion of the respective write cycle addresses
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09503049
|
Filing Dt:
|
02/12/2000
|
|
Title:
|
Intializing memory cells within a dynamic memory array prior to performing internal memory operations
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09503050
|
Filing Dt:
|
02/12/2000
|
|
Title:
|
Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09503108
|
Filing Dt:
|
02/11/2000
|
|
Title:
|
GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09503109
|
Filing Dt:
|
02/11/2000
|
|
Title:
|
Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09516399
|
Filing Dt:
|
03/01/2000
|
|
Title:
|
APPARATUS FOR TRANSLATING A VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
09999563
|
Filing Dt:
|
11/15/2001
|
|
Title:
|
INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11085770
|
Filing Dt:
|
03/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12635543
|
Filing Dt:
|
12/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
CONCURRENT MEMORY BANK ACCESS AND REFRESH RETIREMENT
|
|
