Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 025580/0030 | |
| Pages: | 11 |
| | Recorded: | 01/04/2011 | | |
| Attorney Dkt #: | **BS-2,3,5,10,13,14,18,19 |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09642140
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Filing Dt:
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08/18/2000
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Title:
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METHOD FOR MAKING INTEGRATED CIRCUIT INCLUDING INTERCONNECTS WITH ENHANCED ELECTROMIGRATION RESISTANCE USING DOPED SEED LAYER AND INTEGRATED CIRCUITS PRODUCED THEREBY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12554137
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Filing Dt:
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09/04/2009
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Publication #:
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Pub Dt:
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12/31/2009
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Title:
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Methods of Manufacturing Copper Interconnect Systems
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Assignee
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| 2711 CENTERVILLE ROAD |
| SUITE 400 |
| WILMINGTON, DELAWARE 19808 |
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Correspondence name and address
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WOODCOCK WASHBURN LLC
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2929 ARCH STREET
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CIRA CENTRE, 12TH FLOOR
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PHILADELPHIA, PA 19104
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