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Total properties:
12
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09433245
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Filing Dt:
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11/03/1999
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Title:
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FLASH MEMORY ARCHITECTURE AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09503982
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Filing Dt:
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02/14/2000
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Title:
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Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09542802
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Filing Dt:
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04/04/2000
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Title:
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Powering dies on a semiconductor wafer through wafer scribe line areas
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09668431
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Filing Dt:
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09/22/2000
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Title:
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AN INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09757088
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Filing Dt:
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01/08/2001
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Title:
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A STRUCTURE AND METHOD OF OPERATING AN ARRAY OF NON-VOLATILE MEMORY CELL WITH SOUCE-SIDE PROGRAMMING
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09930011
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Filing Dt:
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08/14/2001
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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TESTING DIES ON A SEMICONDUCTOR WAFER IN A SEQUENTIAL AND OVERLAPPING MANNER
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09938266
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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NON-VOLATILE MEMORY ARCHITECTURE AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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10099291
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10100508
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM USING A MEMORY CELL WITH SOURCE-SIDE PROGRAMMING
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10340558
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Filing Dt:
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01/09/2003
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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11614241
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Filing Dt:
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12/21/2006
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Publication #:
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Pub Dt:
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05/10/2007
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Title:
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STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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11614252
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Filing Dt:
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12/21/2006
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Publication #:
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Pub Dt:
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05/03/2007
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Title:
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STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER
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