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Total properties:
16
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Patent #:
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Issue Dt:
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11/25/1997
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Application #:
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08754602
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Filing Dt:
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11/20/1996
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Title:
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METHOD FOR FORMING BLANKET PLANARIZATION OF THE MULTILEVEL INTERCONNECTION
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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08774753
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Filing Dt:
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12/30/1996
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Title:
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MANUFACTURING PROCESS OF A SPLIT GATE FLASH MEMORY UNIT
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08805391
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Filing Dt:
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02/24/1997
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Title:
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INTRACHIP POWER DISTRIBUTION PACKAGE AND METHOD FOR SEMICONDUCTORS HAVING A SUPPLY NODE ELECTRICALLY INTERCONNECTED WITH ONE OR MORE INTERMEDIATE NODES
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08968981
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Filing Dt:
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11/12/1997
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Title:
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NEW MULTIPLE CHIP MODULE CONFIGURATION TO SIMPLIFY TESTING PROCESS AND REUSE OF KNOWN-GOOD CHIP-SIZE PACKAGE (CSP)
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09048832
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Filing Dt:
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03/20/1998
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Title:
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COVERED SLIT ISOLATION BETWEEN INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09159079
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Filing Dt:
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09/22/1998
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Title:
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CONTACT PRESSURE JIG FOR SIGNAL ANALYSIS
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09190660
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Filing Dt:
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11/12/1998
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Title:
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MULTI-CHIP MEMORY APPARATUS AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09229139
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Filing Dt:
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01/12/1999
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Publication #:
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Pub Dt:
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12/06/2001
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Title:
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SOLDER BALLS AND COLUMNS WITH STRATIFIED UNDERFILLS ON SUBSTRATE FOR FLIP CHIP JOINING
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09287218
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Filing Dt:
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04/05/1999
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Title:
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DIRECT-CHIP-ATTACH (DCA) MULTIPLE CHIP MODULE (MCM) WITH REPAIR-CHIP READY SITE T0 SIMPLIFY ASSEMBLING AND TESTING PROCESS
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09313562
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Filing Dt:
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05/15/1999
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Title:
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FACE-TO-FACE (FTF) STACKED ASSEMBLY OF SUBSTRATE-ON-BARE-CHIP (SOBC) MODULES
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09314493
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Filing Dt:
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05/18/1999
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Title:
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SUBSTRATE ON CHIP (SOC) MULTIPLE-CHIP MODULE (MCM) WITH CHIP-SIZE-PACKAGE (CSP) READY CONFIGURATION
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09444988
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Filing Dt:
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11/23/1999
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Title:
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SELF-ALIGNED CONTACT FOR TRENCH DMOS TRANSISTORS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09687022
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Filing Dt:
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10/13/2000
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Title:
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Covered slit isolation between integrated circuit devices
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09727913
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Filing Dt:
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11/28/2000
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Title:
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PROCESS FLOW AND CONFIGURATION OF MULTIPLE CHIP MODULE(MCM) MANUFACTURED WITH PRE-TESTED KNOWN GOOD SUBSTRATE(KGS)
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09905416
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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METHOD AND APPARATUS FOR WAFER ANALYSIS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10004680
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Filing Dt:
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12/05/2001
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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APPARATUS AND METHOD FOR PREVENTING A WAFER MAPPING SYSTEM OF AN SMIF SYSTEM FROM BEING POLLUTED BY CORROSIVE GASES REMAINING ON WAFERS
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