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Total properties:
20
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Patent #:
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Issue Dt:
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02/27/1996
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Application #:
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08270274
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Filing Dt:
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07/05/1994
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Title:
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NON-VOLATILE RAM TRANSFERRING DATA BETWEEN FERRO-ELECTRIC CAPACITORS AND A MEMORY CELL
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Patent #:
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Issue Dt:
|
08/13/1996
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Application #:
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08393790
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Filing Dt:
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02/24/1995
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Title:
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INTEGRATED CIRCUIT MEMORY HAVING A SELF-TIMED WRITE PULSE INDEPENDENT OF CLOCK FREQUENCY AND DUTY CYCLE
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Patent #:
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Issue Dt:
|
02/18/1997
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Application #:
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08506989
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Filing Dt:
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07/28/1995
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Title:
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NON-VOLATILE MEMORY CELL HAVING A SINGLE POLYSILICON GATE
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Patent #:
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Issue Dt:
|
05/12/1998
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Application #:
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08557401
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Filing Dt:
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11/13/1995
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Title:
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MULTI-PURPOSE PERIPHERAL BUS DRIVER APPARATUS AND METHOD
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|
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Patent #:
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Issue Dt:
|
05/04/1999
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Application #:
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08780120
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Filing Dt:
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12/26/1996
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Title:
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PIPELINED FAST-ACCESS FLOATING GATE MEMORY ARCHITECTURE AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08834960
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Filing Dt:
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04/07/1997
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Title:
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FUSLELESS MEMORY REPAIR SYSTEM AND METHOD OF OPERATION
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|
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Patent #:
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|
Issue Dt:
|
03/21/2000
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Application #:
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08859898
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Filing Dt:
|
05/21/1997
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Title:
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CIRCUIT AND METHOD FOR VERIFYING DATA OF A WIRELESS COMMUNICATIONS DEVICE
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|
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Patent #:
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|
Issue Dt:
|
07/04/2000
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Application #:
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08936371
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Filing Dt:
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09/24/1997
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Title:
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METHOD AND APPARATUS FOR DISTINGUISHING REGISTER READS FROM MEMORY READS IN A FLASH MEMORY
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|
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Patent #:
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|
Issue Dt:
|
11/02/1999
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Application #:
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09009290
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Filing Dt:
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01/20/1998
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Title:
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CIRCUIT AND METHOD OF LATCHING A BIT LINE IN A NON-VOLATILE MEMORY
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|
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Patent #:
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Issue Dt:
|
03/23/1999
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Application #:
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09010042
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Filing Dt:
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01/20/1998
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Title:
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CIRCUIT AND METHOD OF MEASURING THE NEGATIVE THRESHOLD VOLTAGE OF A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
|
01/04/2000
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Application #:
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09241150
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Filing Dt:
|
02/01/1999
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Title:
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A DIGITAL SIGNAL PROCESSOR HAVING AN ON-CHIP PIPLINED EEPROM DATA MEMORY AND A ON-CHIP PIPELINED EEPROM PROGRAM MEMORY
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Patent #:
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|
Issue Dt:
|
04/10/2001
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Application #:
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09302505
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Filing Dt:
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04/30/1999
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Title:
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ON-CHIP ERROR DETECTION AND CORRECTION SYSTEM FOR AN EMBEDDED NON-VOLATILE MEMORY ARRAY AND METHOD OF OPERATION
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|
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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09441865
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Filing Dt:
|
11/17/1999
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Title:
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IN-CIRCUIT MEMORY ARRAY BIT CELL THRESHOLD VOLTAGE DISTRIBUTION MEASUREMENT
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|
|
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Patent #:
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Issue Dt:
|
08/20/2002
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Application #:
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09639195
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Filing Dt:
|
08/15/2000
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Title:
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NON-VOLATILE MEMORY, METHOD OF MANUFACTURE, AND METHOD OF PROGRAMMING
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|
|
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Patent #:
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|
Issue Dt:
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10/29/2002
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Application #:
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09997330
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Filing Dt:
|
11/29/2001
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|
Title:
|
CASCODE SENSE AMP AND COLUMN SELECT CIRCUIT AND METHOD OF OPERATION
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|
|
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Patent #:
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|
Issue Dt:
|
07/06/2004
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Application #:
|
10260970
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Filing Dt:
|
09/30/2002
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|
Publication #:
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|
Pub Dt:
|
04/01/2004
| | | | |
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Title:
|
ERASE OF A NON-VOLATILE MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
12/28/2004
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Application #:
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10319664
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Filing Dt:
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12/13/2002
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Publication #:
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|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
COMPACTION SCHEME IN NVM
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/01/2005
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Application #:
|
10412490
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Filing Dt:
|
04/11/2003
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Publication #:
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|
Pub Dt:
|
10/14/2004
| | | | |
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Title:
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MEMORY DEVICE WITH SENSE AMPLIFIER AND SELF-TIMED LATCH
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|
|
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Patent #:
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|
Issue Dt:
|
05/24/2005
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Application #:
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10622353
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Filing Dt:
|
07/18/2003
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Publication #:
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Pub Dt:
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01/20/2005
| | | | |
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Title:
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PROGRAMMING OF A MEMORY WITH DISCRETE CHARGE STORAGE ELEMENTS
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/27/2007
|
Application #:
|
10930892
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Filing Dt:
|
08/31/2004
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|
Publication #:
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|
Pub Dt:
|
03/02/2006
| | | | |
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Title:
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PROGRAMMING, ERASING, AND READING STRUCTURE FOR AN NVM CELL
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