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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:031290/0038   Pages: 6
Recorded: 09/23/2013
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 23
1
Patent #:
5815041
Issue Dt:
09/29/1998
Application #:
08631420
Filing Dt:
04/12/1996
Title:
HIGH-SPEED AND HIGH-PRECISION PHASE LOCKED LOOP HAVING PHASE DETECTOR WITH DYNAMIC LOGIC STRUCTURE
2
Patent #:
6100879
Issue Dt:
08/08/2000
Application #:
08909022
Filing Dt:
08/11/1997
Title:
SYSTEM AND METHOD FOR CONTROLLING AN ACTIVE MATRIX DISPLAY
3
Patent #:
6100868
Issue Dt:
08/08/2000
Application #:
08937262
Filing Dt:
09/15/1997
Title:
HIGH DENSITY COLUMN DRIVERS FOR AN ACTIVE MATRIX DISPLAY
4
Patent #:
6157263
Issue Dt:
12/05/2000
Application #:
09098266
Filing Dt:
06/16/1998
Title:
HIGH-SPEED AND HIGH-PRECISION PHASE LOCKED LOOP HAVING PHASE DETECTOR WITH DYNAMIC LOGIC STRUCTURE
5
Patent #:
6229859
Issue Dt:
05/08/2001
Application #:
09146818
Filing Dt:
09/04/1998
Title:
SYSTEM AND METHOD FOR HIGH-SPEED, SYNCHRONIZED DATA COMMUNICATION
6
Patent #:
6271816
Issue Dt:
08/07/2001
Application #:
09148583
Filing Dt:
09/04/1998
Title:
POWER SAVING CIRCUIT AND METHOD FOR DRIVING AN ACTIVE MATRIX DISPLAY
7
Patent #:
6144242
Issue Dt:
11/07/2000
Application #:
09148815
Filing Dt:
09/04/1998
Title:
CONTROLLABLE DELAYS IN MULTIPLE SYNCHRONIZED SIGNALS FOR REDUCED ELECTROMAGNETIC INTERFERENCE AT PEAK FREQUENCIES
8
Patent #:
6560290
Issue Dt:
05/06/2003
Application #:
09234619
Filing Dt:
01/20/1999
Publication #:
US20020064247
Pub Dt:
05/30/2002
Title:
CMOS DRIVER AND ON-CHIP TERMINATION FOR GIGABAUD SPEED DATA COMMUNICATION
9
Patent #:
6600771
Issue Dt:
07/29/2003
Application #:
09234777
Filing Dt:
01/20/1999
Title:
SPREAD SPECTRUM PHASE MODULATION FOR SUPPRESSION OF ELECTROMAGNETIC INTERFERENCE IN PARALLEL DATA CHANNELS
10
Patent #:
6463092
Issue Dt:
10/08/2002
Application #:
09393235
Filing Dt:
09/09/1999
Title:
SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE
11
Patent #:
6462624
Issue Dt:
10/08/2002
Application #:
09693516
Filing Dt:
10/20/2000
Title:
HIGH-SPEED AND HIGH-PRECISION PHASE LOCKED LOOP
12
Patent #:
6587525
Issue Dt:
07/01/2003
Application #:
09814256
Filing Dt:
03/21/2001
Publication #:
US20010009571
Pub Dt:
07/26/2001
Title:
SYSTEM AND METHOD FOR HIGH-SPEED, SYNCHRONIZED DATA COMMUNICATION
13
Patent #:
NONE
Issue Dt:
Application #:
09943029
Filing Dt:
08/29/2001
Publication #:
US20020085656
Pub Dt:
07/04/2002
Title:
Data recovery using data eye tracking
14
Patent #:
6693985
Issue Dt:
02/17/2004
Application #:
10043886
Filing Dt:
10/26/2001
Publication #:
US20020131539
Pub Dt:
09/19/2002
Title:
CLOCK AND DATA RECOVERY METHOD AND APPARATUS
15
Patent #:
6930560
Issue Dt:
08/16/2005
Application #:
10183974
Filing Dt:
06/25/2002
Publication #:
US20030090327
Pub Dt:
05/15/2003
Title:
HIGH-SPEED AND HIGH-PRECISION PHASE LOCKED LOOP
16
Patent #:
NONE
Issue Dt:
Application #:
10305254
Filing Dt:
11/25/2002
Publication #:
US20040210790
Pub Dt:
10/21/2004
Title:
0.6-2.5 GBaud CMOS tracked 3X oversampling transceiver with dead zone phase detection for robust clock/data recovery
17
Patent #:
6859107
Issue Dt:
02/22/2005
Application #:
10356695
Filing Dt:
01/30/2003
Title:
FREQUENCY COMPARATOR WITH HYSTERESIS BETWEEN LOCKED AND UNLOCKED CONDITIONS
18
Patent #:
7203260
Issue Dt:
04/10/2007
Application #:
10612840
Filing Dt:
07/03/2003
Publication #:
US20040005021
Pub Dt:
01/08/2004
Title:
TRACKED 3X OVERSAMPLING RECEIVER
19
Patent #:
6888417
Issue Dt:
05/03/2005
Application #:
10613442
Filing Dt:
07/03/2003
Publication #:
US20040051597
Pub Dt:
03/18/2004
Title:
VOLTAGE CONTROLLED OSCILLATOR
20
Patent #:
6876240
Issue Dt:
04/05/2005
Application #:
10722842
Filing Dt:
11/25/2003
Publication #:
US20040104778
Pub Dt:
06/03/2004
Title:
WIDE RANGE MULTI-PHASE DELAY-LOCKED LOOP
21
Patent #:
7627044
Issue Dt:
12/01/2009
Application #:
11264303
Filing Dt:
10/31/2005
Publication #:
US20070098112
Pub Dt:
05/03/2007
Title:
CLOCK-EDGE MODULATED SERIAL LINK WITH DC-BALANCE CONTROL
22
Patent #:
7315598
Issue Dt:
01/01/2008
Application #:
11498355
Filing Dt:
08/02/2006
Publication #:
US20070002990
Pub Dt:
01/04/2007
Title:
DATA RECOVERY USING DATA EYE TRACKING
23
Patent #:
7519138
Issue Dt:
04/14/2009
Application #:
11962066
Filing Dt:
12/20/2007
Publication #:
US20080152057
Pub Dt:
06/26/2008
Title:
METHOD AND APPARATUS FOR DATA RECOVERY IN A DIGITAL DATA STREAM USING DATA EYE TRACKING
Assignor
1
ACACIA RESEARCH GROUP LLC
Exec Dt:
09/13/2013
Assignee
1
SUPER INTERCONNECT TECHNOLOGIES LLC
2400 DALLAS PARKWAY, SUITE 200
PLANO, TEXAS 75093
Correspondence name and address
JENNIFER GRAFF
2400 DALLAS PARKWAY, SUITE 200
PLANO, TX 75093

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