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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08076876
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Filing Dt:
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06/11/1993
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Title:
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MULTIPLEX ADDRESS/DATA BUS WITH MULTIPLEX SYSTEM CONTROLLER AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/12/1995
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Application #:
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08158968
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Filing Dt:
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11/30/1993
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Title:
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BUS INTERFACE WITH GRAPHICS AND SYSTEM PATHS FOR AN INTEGRATED MEMORY SYSTEM
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08216192
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Filing Dt:
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01/14/1993
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Title:
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TWO-WIRE BUS SYSTEM COMPRISING A CLOCK WIRE AND A DATA WIRE FOR INTERCONNECTING A NUMBER OF STATIONS AND ALLOWING BOTH LONG-FORMAT AND SHORT-FORMAT SLAVE ADDRESSES
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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08253465
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Filing Dt:
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06/03/1994
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Title:
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TWO-LINE MIXED ANALOG/DIGITAL BUS SYSTEM AND A MASTER STATION AND A SLAVE STATION FOR USE IN SUCH SYSTEM
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08308059
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Filing Dt:
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09/16/1994
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Title:
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A SYSTEM FOR WRITE PROTECTING A BIT THAT IS HARDWARE MODIFIED DURING A READ-MODIFY-WRITE CYCLE
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Patent #:
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Issue Dt:
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02/03/1998
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Application #:
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08308328
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Filing Dt:
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09/19/1994
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Title:
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MULTI-MODE INFRARED INPUT/OUTPUT INTERFACE
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Patent #:
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Issue Dt:
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09/17/1996
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Application #:
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08316280
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Filing Dt:
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09/30/1994
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Title:
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FILTER FOR COMPUTER BUS SIGNALS
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08327123
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Filing Dt:
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10/21/1994
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Title:
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BI-DIRECTIONAL SIGNAL TRANSMISSION SYSTEM AND ADAPTER FOR SUCH A SYSTEM
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Patent #:
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Issue Dt:
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08/06/1996
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Application #:
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08494756
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Filing Dt:
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06/26/1995
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Title:
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HIGH VOLTAGE TOLERANT CMOS INPUT/OUTPUT CIRCUIT
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Patent #:
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Issue Dt:
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09/02/1997
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Application #:
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08504936
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Filing Dt:
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07/20/1995
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Title:
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INPUT/OUTPUT(I/O) HOLDOFF MECHANISM FOR USE IN A SYSTEM WHERE I/O DEVICE INPUTS ARE FED THROUGH A LATENCY INTRODUCING BUS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08510076
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Filing Dt:
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08/01/1995
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Title:
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METHOD AND APPARATUS FOR ENHANCING ACCESS TO A SHARED MEMORY
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Patent #:
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Issue Dt:
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03/04/1997
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Application #:
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08526956
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Filing Dt:
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09/12/1995
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Title:
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HIGH SPEED PHASE ALIGNER WITH JITTER REMOVAL
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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08552666
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Filing Dt:
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11/03/1995
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Title:
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GTL INPUT RECEIVER WITH HYSTERESIS
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08565774
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Filing Dt:
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12/01/1995
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Title:
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CIRCUIT COMPRISING A DATA COMMUNICATION BUS
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08602535
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Filing Dt:
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02/20/1996
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Title:
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SYSTEM FOR ESTIMATING SIGNALS RECEIVED IN THE FORM OF MIXED SIGNALS
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08611784
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Filing Dt:
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03/06/1996
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Title:
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PCI BUS MASTER WITH CASCADED PCI ARBITRATION
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08619924
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Filing Dt:
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03/20/1996
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Title:
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METHOD FOR OPTIMIZING PERFORMANCE VERSUS POWER CONSUMPTION USING EXTERNAL/INTERNAL CLOCK FREQUENCY RATIOS
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08621594
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Filing Dt:
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03/26/1996
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Title:
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VERSATILE CONNECTION OF A FIRST KEYBOARD/MOUSE INTERFACE AND A SECOND KEYBOARD/MOUSE INTERFACE TO A HOST COMPUTER
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08643350
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Filing Dt:
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05/06/1996
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Title:
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SYSTEM AND METHOD FOR AUTOMATICALLY ENABLING AND DISABLING A PREFETCHING CAPABILITIY
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08652780
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Filing Dt:
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05/23/1996
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Title:
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TIMING METHOD AND APPARATUS FOR INTERLEAVING PIO AND DMA DATA TRANSFERS
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08664107
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Filing Dt:
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06/13/1996
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Title:
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METHOD AND APPARATUS FOR ARBITRATING ACCESS TO MAIN MEMORY OF A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08703563
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Filing Dt:
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08/27/1996
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Title:
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DEADLOCK RESOLUTION METHODS AND APPARATUS FOR INTERFACING CONCURRENT AND ASYNCHRONOUS BUSES
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08706059
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Filing Dt:
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08/30/1996
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Title:
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METHOD AND APPARATUS FOR CUSTOM OPERATIONS
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Patent #:
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Issue Dt:
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01/26/1999
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Application #:
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08715457
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Filing Dt:
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09/18/1996
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Title:
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BUFFER AND METHOD FOR TRANSFERRING DATA THEREIN
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08717529
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Filing Dt:
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09/17/1996
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Title:
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WAVETABLE ADDRESS CACHE TO REDUCE ACCESSES OVER A PCI BUS
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08719844
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Filing Dt:
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09/30/1996
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Title:
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WIRELESS SYSTEM FOR DIAGNOSING EXAMINATION AND PROGRAMMING OF VEHICULAR CONTROL SYSTEMS AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08740501
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Filing Dt:
|
10/29/1996
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Title:
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MULTIPLE BUS AGENT INTEGRATED CIRCUIT DEVICE FOR CONNECTING TO AN EXTERNAL BUS
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08751281
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Filing Dt:
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11/18/1996
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Title:
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PIN SELECTION SYSTEM FOR MICROCONTROLLER HAVING MULTIPLEXER SELECTS BETWEEN ADDRESS/DATA SIGNALS AND SPECIAL SIGNALS PRODUCED BY SPECIAL FUNCTION DEVICE
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08758654
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Filing Dt:
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12/02/1996
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Title:
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CIRCUIT COMPRISING A BUS CONDUCTOR AND A BUS INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08760701
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Filing Dt:
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12/05/1996
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Title:
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METHOD AND SYSTEM FOR AN EXTENSIBLE ON SILICON BUS SUPPORTING MULTIPLE FUNCTIONAL BLOCKS
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08823003
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Filing Dt:
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03/21/1997
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Title:
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PARALLEL DATA PROCESSING DEVICE HAVING A CONCATENATED DATA PATH BETWEEN ELEMENTARY PROCESSORS
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08836852
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Filing Dt:
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04/30/1997
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Title:
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METHOD AND APPARATUS FOR CUSTOM OPERATIONS OF A PROCESSOR
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08853288
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Filing Dt:
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05/09/1997
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Title:
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SYSTEM AND METHOD FOR SHARING PHYSICAL MEMORY AMONG DISTINCT COMPUTER ENVIRONMENTS
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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08859168
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Filing Dt:
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05/20/1997
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Title:
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MEMORY SPACE COMPRESSION TECHNIQUE FOR A SEQUENTIALLY ACCESSIBLE MEMORY
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08873099
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Filing Dt:
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06/10/1997
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Title:
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MULTI-MASTER PCI BUS SYSTEM WITHIN A SINGLE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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08897216
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Filing Dt:
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07/14/1997
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Title:
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SMART RETRY MECHANISM TO PROGRAM THE RETRY LATENCY OF A PCI INITIATOR AGENT
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08934449
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Filing Dt:
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09/19/1997
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Title:
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FLOATING-POINT PROCESSOR WITH OPERAND-FORMAT PRECISION GREATER THAN EXECUTION PRECISION
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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08935565
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Filing Dt:
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09/24/1997
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Title:
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METHOD OF IMPLEMENTING MULTIPLE FORMAT ADDRESSING IN AN EMBEDDED MICROCONTROLLER, COMPILER BEING ARRANGED FOR IMPLEMENTING THE METHOD, AND A MICROCONTROLLER BEING ARRANGED FOR USING THE METHOD AND COMPILER
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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08947650
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Filing Dt:
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10/09/1997
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Title:
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METHOD AND SYSTEM FOR PSEUDO DELAYED TRANSACTIONS THROUGH A BRIDGE TO GUARANTEE ACCESS TO A SHARED RESOURCE
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08951396
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Filing Dt:
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10/16/1997
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Title:
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METHOD FOR MEASURING THE EFFECTIVENESS OF OPTICAL PROXIMITY CORRECTIONS
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08958530
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Filing Dt:
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10/27/1997
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Title:
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SCAN TESTABLE CIRCUIT ARRANGEMENT
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08968679
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Filing Dt:
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11/12/1997
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Title:
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GRAPHICS CONTROLLER FOR FORMING A COMPOSITE IMAGE
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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08989833
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Filing Dt:
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12/12/1997
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Title:
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INPUT SLOPE TIMING ANALYSIS AND NON-LINEAR DELAY TABLE OPTIMIZATION
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09011868
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Filing Dt:
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05/18/1998
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Title:
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DATA TRANSMISSION SYSTEM HAVING WATCHDOG AND VOLTAGE REGULATORS FOR MULTIPLE MODES OF OPERATION
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09015328
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Filing Dt:
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01/29/1998
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Title:
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FIVE VOLT TOLERANT I/O BUFFER
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09025020
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Filing Dt:
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02/17/1998
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Title:
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SELECTIVE DATA READ-AHEAD IN BUS-TO-BUS BRIDGE ARCHITECTURE
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09045469
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Filing Dt:
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03/20/1998
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Title:
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METHOD OF AND SYSTEM FOR ALLOWING A COMPUTER SYSTEM TO ACCESS CACHEABLE MEMORY IN A NON-CACHEABLE MANNER
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09074226
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Filing Dt:
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05/07/1998
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Title:
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INTERFACE CIRCUIT WITH SLEW RATE CONTROL
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09079989
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Filing Dt:
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05/14/1998
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Title:
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CENTRALLY CONTROLLED INTERFACE SCHEME FOR PROMOTING DESIGN REUSABLE CIRCUIT BLOCKS
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09080836
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Filing Dt:
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05/18/1998
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Title:
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METHOD AND SYSTEM FOR EMULATING MICROCONTROLLERS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09098765
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Filing Dt:
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06/17/1998
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Title:
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ELECTRONIC APPARATUS HAVING A HIGH-SPEED COMMUNICATION BUS SYSTEM SUCH AS AN I2C BUS SYSTEM
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09105553
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Filing Dt:
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06/26/1998
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Title:
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PHYSICAL LAYER SECURITY MANAGER FOR MEMORY-MAPPED SERIAL COMMUNICATIONS INTERFACE
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09107030
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Filing Dt:
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06/29/1998
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Title:
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DUAL POINTER CIRCULAR QUEUE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09110872
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Filing Dt:
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07/07/1998
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Title:
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METHOD AND APPARATUS FOR READING MULTIPLE MATCHED ADDRESSES
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09119081
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Filing Dt:
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07/20/1998
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Title:
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HOT DOCKING SYSTEM FOR DETECTING AND MANAGING HOT DOCKING OF BUS CARDS
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09159424
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Filing Dt:
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09/24/1998
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Title:
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POINT TO POINT OR RING CONNECTABLE BUS BRIDGE AND AN INTERFACE WITH METHOD FOR ENHANCING LINK PERFORMANCE IN A POINT TO POINT CONNECTABLE BUS BRIDGE SYSTEM USING THE FIBRE CHANNEL
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Issue Dt:
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08/14/2001
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Application #:
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09163061
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Filing Dt:
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09/29/1998
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Title:
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MICROPROCESSOR-BASED SERIAL BUS INTERFACE ARRANGEMENT AND METHOD
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Patent #:
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04/09/2002
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Application #:
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09185411
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Filing Dt:
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11/03/1998
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Title:
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INTERGRATED CIRCUITRY, INTERFACE CIRCUIT OF AN INTEGRATED CIRCUIT DEVICE AND CIRCUITRY
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Patent #:
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09/11/2001
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Application #:
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09187325
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Filing Dt:
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11/06/1998
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Title:
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OPTIMIZING THE PERFORMANCE OF ASYNCHRONOUS BUS BRIDGES WITH DYNAMIC TRANSACTIONS
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Issue Dt:
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07/29/2003
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Application #:
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09198925
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Filing Dt:
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11/24/1998
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Title:
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MEMORY INTERFACE UNIT WITH PROGRAMMABLE STROBES TO SELECT DIFFERENT MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09200641
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Filing Dt:
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11/25/1998
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Title:
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A PULSE DETECTOR WITH DOUBLE RESOLUTION
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Issue Dt:
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11/13/2001
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09201450
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Filing Dt:
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11/30/1998
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Title:
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CONCURRENT SERIAL INTERCONNECT FOR INTEGRATING FUNCTIONAL BLOCKS IN AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09203634
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Filing Dt:
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12/01/1998
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Title:
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ARBITRATION SCHEME FOR A SERIAL INTERFACE
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09210103
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Filing Dt:
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12/11/1998
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Title:
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SMART TARGET MECHANISM FOR ELIMINATING DUAL ADDRESS CYCLES IN A PERIPHERAL COMPONENT INTERCONNECT ENVIRONMENT
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09215942
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Filing Dt:
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12/18/1998
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Title:
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METHOD AND ARRANGEMENT FOR RAPID SILICON PROTOTYPING
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09216291
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Filing Dt:
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12/18/1998
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Title:
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METHOD AND ARRANGEMENT FOR PASSING DATA BETWEEN A REFERENCE CHIP AND AN EXTERNAL BUS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09222397
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Filing Dt:
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12/29/1998
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Title:
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HIGH-SPEED SERIAL DATA COMMUNICATION SYSTEM
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09222401
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Filing Dt:
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12/29/1998
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Title:
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DATA AND/OR ENERGY TRANSMISSION DEVICE WITH A DISCONNECTING UNIT
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09239461
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Filing Dt:
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01/28/1999
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Title:
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METHOD FOR ELIMINATING DUAL ADDRESS CYCLES IN A PERIPHERAL COMPONENT INTERCONNECT ENVIRONMENT
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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09261005
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Filing Dt:
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03/02/1999
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Title:
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BUS BRIDGE DEVICE FOR ADVANCED MICROCCONTROLLER BUS ARCHITECTURE (AMBA) ADVANCED SYSTEM BUS (ASB) PROTOCOL
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Patent #:
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Issue Dt:
|
08/28/2001
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Application #:
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09262099
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Filing Dt:
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03/04/1999
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Title:
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POWER SUPPLY IN THE STANDBY MODE
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Patent #:
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Issue Dt:
|
10/09/2001
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Application #:
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09277860
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Filing Dt:
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03/26/1999
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Title:
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DIRECT MEMORY ACCESS SYSTEM AND METHOD TO BRIDGE PCI BUS PROTOCOLS AND HITACHI SH4 PROTOCOLS
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Patent #:
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Issue Dt:
|
08/15/2000
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Application #:
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09282291
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Filing Dt:
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03/31/1999
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Title:
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METHOD OF PROTECTING AN INTEGRATED CIRCUIT, METHOD OF OPERATING INTEGRATED CIRCUITRY, AND METHOD OF OPERATING CASCODE CIRCUITRY
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Patent #:
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Issue Dt:
|
10/30/2001
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Application #:
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09291402
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Filing Dt:
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04/13/1999
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Title:
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METHOD AND SYSTEM FOR OPTIMIZED DATA TRANSFERS IN A MIXED 64-BIT/32-BIT PCI ENVIRONMENT
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Patent #:
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Issue Dt:
|
06/25/2002
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Application #:
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09293077
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Filing Dt:
|
04/16/1999
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Title:
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SYSTEM AND METHOD TO OPTIMIZE READ PERFORMANCE WHILE ACCEPTING WRITE DATA IN A PCI BUS ARCHITECTURE
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Patent #:
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Issue Dt:
|
07/16/2002
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Application #:
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09304595
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Filing Dt:
|
05/04/1999
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Title:
|
ELECTRONIC APPARATUS
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Patent #:
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Issue Dt:
|
11/28/2000
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Application #:
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09304596
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Filing Dt:
|
05/04/1999
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Title:
|
CAN BUS DRIVER WITH SYMMETRICAL DIFFERENTIAL OUTPUT SIGNALS
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Patent #:
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Issue Dt:
|
01/28/2003
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Application #:
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09307164
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Filing Dt:
|
05/07/1999
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Title:
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FIFO SYSTEM WITH VARIABLE-WIDTH INTERFACE TO HOST PROCESSOR
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09311911
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Filing Dt:
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05/14/1999
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Title:
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PCI BRIDGE CONFIGURATION HAVING PHYSICALLY SEPARATE PARTS
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09312206
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Filing Dt:
|
05/14/1999
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Title:
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PCI BRIDGE HAVING LATENCY INDUCING SERIAL BUS
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Patent #:
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Issue Dt:
|
08/13/2002
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Application #:
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09316983
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Filing Dt:
|
05/24/1999
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Title:
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CLOCK SYSTEM FOR MULTIPLE COMPONENT SYSTEM INCLUDING MODULE CLOCKS FOR SAFETY MARGIN OF DATA TRANSFERS AMONG PROCESSING MODULES
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Patent #:
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|
Issue Dt:
|
07/09/2002
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Application #:
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09329033
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Filing Dt:
|
06/09/1999
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Title:
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ARRANGEMENT AND METHOD FOR THE TRANSMISSION OF ADDRESS, INSTRUCTION AND/OR DATA TELEGRAMS
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Patent #:
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Issue Dt:
|
02/18/2003
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Application #:
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09389871
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Filing Dt:
|
09/02/1999
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Title:
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METHOD AND SYSTEM FOR CONTROLLING INTERNAL BUSSES TO PREVENT BUS CONTENTION DURING INTERNAL SCAN TESTING BY USING A CENTRALIZED CONTROL RESOURCE
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Patent #:
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Issue Dt:
|
03/26/2002
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Application #:
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09394395
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Filing Dt:
|
09/13/1999
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Title:
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INTERFACE AND PROCESS FOR HANDLING OUT-OF-ORDER DATA TRANSACTIONS AND SYNCHRONIZING EVENTS IN A SPLIT-BUS SYSTEM
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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09402154
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Filing Dt:
|
09/29/1999
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Title:
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CIRCUIT WITH INTERCONNECT TEST UNIT AND A METHOD OF TESTING INTERCONNECTS BETWEEN A FIRST AND A SECOND ELECTRONIC CIRCUIT
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Patent #:
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Issue Dt:
|
08/22/2000
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Application #:
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09408791
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Filing Dt:
|
09/30/1999
|
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Title:
|
ZERO POWER SRAM PRECHARGE
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Patent #:
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Issue Dt:
|
04/03/2001
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Application #:
|
09412260
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Filing Dt:
|
10/05/1999
|
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Title:
|
ARRANGEMENT FOR CONTROLLING PREDETERMINED FUNCTION VIA A DATA BUS
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Patent #:
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Issue Dt:
|
02/11/2003
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Application #:
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09423570
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Filing Dt:
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11/09/1999
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Title:
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DATA TRANSMISSION SYSTEM
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Patent #:
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Issue Dt:
|
06/10/2003
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Application #:
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09435133
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Filing Dt:
|
11/04/1999
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Title:
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PREDICTIVE MECHANISM FOR ASB SLAVE RESPONSES
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Patent #:
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Issue Dt:
|
11/11/2003
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Application #:
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09451275
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Filing Dt:
|
11/30/1999
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Title:
|
SYSTEM AND METHOD FOR OUTPUTTING A SAMPLE USING A TIME STAMP PREDICTED AT A RECEIVING STATION COUPLED TO AN OUTPUT STATION VIA A VARIABLE LATENCY BUS
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Patent #:
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Issue Dt:
|
09/30/2003
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Application #:
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09469885
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Filing Dt:
|
12/22/1999
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Title:
|
SYSTEM AND METHOD FOR ACCESSING INTERNAL REGISTERS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
04/27/2004
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Application #:
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09474901
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Filing Dt:
|
12/30/1999
|
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Title:
|
METHOD FOR CONSERVING POWER IN A CAN MICROCONTROLLER USING A CAN/CAL MODULE
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|
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Patent #:
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Issue Dt:
|
10/07/2003
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Application #:
|
09474903
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Filing Dt:
|
12/30/1999
|
|
Title:
|
SEMAPHORE CODING METHOD TO ENSURE DATA INTEGRITY IN A CAN MICROCONTROLLER AND A CAN MICROCONTROLLER THAT IMPLEMENTS THIS METHOD
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|
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Patent #:
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|
Issue Dt:
|
04/13/2004
|
Application #:
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09474904
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Filing Dt:
|
12/30/1999
|
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Title:
|
METHOD FOR AUTOMATICALLY TRANSMITTING AN ACKNOWLEDGE FRAME IN CANOPEN AND OTHER CAN APPLICATION LAYER PROTOCOLS AND A CAN MICROCONTROLLER THAT IMPLEMENTS THIS METHOD
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Patent #:
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|
Issue Dt:
|
08/13/2002
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Application #:
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09474905
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Filing Dt:
|
12/30/1999
|
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Title:
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METHOD FOR WRITING BACK MESSAGE ID INFORMATION TO A MATCH ID REGISTER AND A CAN MICROCONTROLLER THAT IMPLEMENTS THIS METHOD
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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09495044
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Filing Dt:
|
01/31/2000
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Title:
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EXPANSION MODULE WITH EXTERNAL BUS FOR PERSONAL DIGITAL ASSISTANT AND DESIGN METHOD THEREFOR
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Patent #:
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Issue Dt:
|
01/09/2001
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Application #:
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09500663
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Filing Dt:
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02/09/2000
|
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Title:
|
Circuit arrangement for delivering a supply current
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Patent #:
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Issue Dt:
|
10/15/2002
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Application #:
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09513009
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Filing Dt:
|
02/25/2000
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Title:
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METHOD AND ARRANGEMENT FOR PASSING DATA BETWEEN A REFERENCE CHIP AND AN EXTERNAL BUS
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
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09531103
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Filing Dt:
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03/17/2000
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Title:
|
Scan testable circuit arrangement
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Patent #:
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|
Issue Dt:
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01/27/2004
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Application #:
|
09550446
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Filing Dt:
|
04/17/2000
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Title:
|
MULTI-PROCESSOR JAVA SUBSYSTEM
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