Total properties:
419
Page
1
of
5
Pages:
1 2 3 4 5
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/1995
|
Application #:
|
08068139
|
Filing Dt:
|
05/26/1993
|
|
Title:
|
METALLIZATION OVER TUNGSTEN PLUGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/1995
|
Application #:
|
08084971
|
Filing Dt:
|
06/28/1993
|
|
Title:
|
METHOD OF MAKING NOR-TYPE ROM WITH LDD CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/1998
|
Application #:
|
08188569
|
Filing Dt:
|
01/28/1994
|
|
Title:
|
METHOD AND APPARATUS FOR FILTERING DIGITAL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/1997
|
Application #:
|
08189271
|
Filing Dt:
|
01/28/1994
|
|
Title:
|
METHOD AND APPARATUS FOR FILTERING HIGH RESOLUTION DIGITAL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/1996
|
Application #:
|
08196572
|
Filing Dt:
|
02/15/1994
|
|
Title:
|
NONVOLATILE EPROM, EEPROM OF FLASH-EEPROM MEMORY WITH TUNNEL OXIDE PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/1996
|
Application #:
|
08212907
|
Filing Dt:
|
03/15/1994
|
|
Title:
|
METHOD OF READING, ERASING AND PROGRAMMING A NONVOLATILE FLASH-EEPROM MEMORY ARRAY USING SOURCE LINE SWITCHING TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/1996
|
Application #:
|
08214049
|
Filing Dt:
|
03/15/1994
|
|
Title:
|
NONVOLATILE FLASH-EEPROM MEMORY ARRAY WITH SOURCE CONTROL TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/1995
|
Application #:
|
08219204
|
Filing Dt:
|
03/29/1994
|
|
Title:
|
SEMICONDUCTOR MEMORY WITH MEMORY MATRIX COMPRISING REDUNDANCY CELL COLUMNS ASSOCIATED WITH SINGLE MATRIX SECTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1996
|
Application #:
|
08282408
|
Filing Dt:
|
07/28/1994
|
|
Title:
|
PROCESS FOR REALIZING P-CHANNEL MOS TRANSISTORS HAVING A LOW THRESHOLD VOLTAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS FOR ANALOG APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/1996
|
Application #:
|
08311941
|
Filing Dt:
|
09/26/1994
|
|
Title:
|
VOLTAGE GENERATOR CIRCUIT PROVIDING POTENTIALS OF OPPOSITE POLARITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/1996
|
Application #:
|
08344232
|
Filing Dt:
|
11/23/1994
|
|
Title:
|
METHOD AND DEVICE FOR SUPPLYING NEGATIVE PROGRAMMING VOLTAGES TO NON-VOLATILE MEMORY CELLS IN A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/1998
|
Application #:
|
08345530
|
Filing Dt:
|
11/28/1994
|
|
Title:
|
METHOD AND APPARATUS FOR TESTING A NETWORK WITH A PROGRAMMABLE LOGIC MATRIX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1996
|
Application #:
|
08347653
|
Filing Dt:
|
11/30/1994
|
|
Title:
|
MONOLITHICALLY INTEGRATED STORAGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
08347788
|
Filing Dt:
|
11/30/1994
|
|
Title:
|
STABLE REFERENCE VOLTAGE GENERATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/1996
|
Application #:
|
08348461
|
Filing Dt:
|
12/02/1994
|
|
Title:
|
BIAS CIRCUIT FOR A MEMORY LINE DECODER DRIVER OF NONVOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/1996
|
Application #:
|
08349783
|
Filing Dt:
|
12/06/1994
|
|
Title:
|
REDUNDANCY CIRCUITRY FOR A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/1996
|
Application #:
|
08350961
|
Filing Dt:
|
12/07/1994
|
|
Title:
|
INTEGRATED CIRCUITRY FOR CHECKING THE UTILIZATION RATE OF REDUNDANCY MEMORY ELEMENTS IN A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/1996
|
Application #:
|
08365154
|
Filing Dt:
|
12/28/1994
|
|
Title:
|
INTEGRATED PROGRAMMING CIRCUITRY FOR AN ELECTRICALLY PROGRAMMABLE SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/1997
|
Application #:
|
08365510
|
Filing Dt:
|
12/28/1994
|
|
Title:
|
END-OF-COUNT DETECTING DEVICE FOR NONVOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08366211
|
Filing Dt:
|
12/29/1994
|
|
Title:
|
DEVICE FOR DETECTING A REDUCTION IN A SUPPLY VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08366212
|
Filing Dt:
|
12/29/1994
|
|
Title:
|
CIRCUIT DEVICE AND CORRESPONDING METHOD FOR RESETTING NON-VOLATILE AND ELECTRICALLY PROGRAMMABLE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/1996
|
Application #:
|
08366259
|
Filing Dt:
|
12/29/1994
|
|
Title:
|
VOLTAGE REGULATOR FOR PROGRAMMING NON-VOLATILE AND ELECTRICALLY PROGRAMMABLE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/1996
|
Application #:
|
08367538
|
Filing Dt:
|
01/03/1995
|
|
Title:
|
VOLTAGE REGULATOR FOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08368211
|
Filing Dt:
|
01/03/1995
|
|
Title:
|
VOLTAGE REGULATOR FOR NON-VOLATILE SEMICONDUCTOR ELECTRICALLY PROGRAMMABLE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/1996
|
Application #:
|
08368976
|
Filing Dt:
|
01/05/1995
|
|
Title:
|
REMOVABLE BOWLING BALL THUMB INSERT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/1997
|
Application #:
|
08380309
|
Filing Dt:
|
01/30/1995
|
|
Title:
|
CIRCUIT FOR COVERING INITIAL CONDITIONS WHEN STARTING-UP AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08381530
|
Filing Dt:
|
01/31/1995
|
|
Title:
|
METHOD FOR PROGRAMMING AND TESTING A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1997
|
Application #:
|
08389599
|
Filing Dt:
|
02/16/1995
|
|
Title:
|
METHOD FOR PROGRAMMING REDUNDANCY REGISTERS IN A COLUMN REDUNDANCY INTEGRATED CIRCUITRY FOR A SEMICONDUCTOR MEMORY DEVICE, AND COLUMN REDUNDANCY INTEGRATED CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/1996
|
Application #:
|
08391147
|
Filing Dt:
|
02/21/1995
|
|
Title:
|
METHOD AND CIRCUIT FOR SUPPRESSING DATA LOADING NOISE IN NONVOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08391159
|
Filing Dt:
|
02/21/1995
|
|
Title:
|
INTERNAL TIMING METHOD AND CIRCUIT FOR PROGRAMMABLE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/1996
|
Application #:
|
08391160
|
Filing Dt:
|
02/21/1995
|
|
Title:
|
METHOD AND CIRCUIT FOR TIMING THE LOADING OF NONVOLATILE-MEMORY OUTPUT DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08391999
|
Filing Dt:
|
02/16/1995
|
|
Title:
|
METHOD FOR PROGRAMMING REDUNDANCY REGISTERS IN A ROW REDUNDANCY INTEGRATED CIRCUITRY FOR A SEMICONDUCTOR MEMORY DEVICE, AND ROW REDUNDANCY INTEGRATED CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1997
|
Application #:
|
08395361
|
Filing Dt:
|
02/21/1995
|
|
Title:
|
REGULATION CIRCUIT AND METHOD FOR THE ERASING PHASE OF NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/1997
|
Application #:
|
08408589
|
Filing Dt:
|
03/22/1995
|
|
Title:
|
READING CIRCUIT FORAN INTEGRATED SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/1996
|
Application #:
|
08411904
|
Filing Dt:
|
03/28/1995
|
|
Title:
|
REFERENCE SIGNAL GENERATING METHOD AND CIRCUIT FOR DIFFERENTIAL EVALUATION OF THE CONTENT OF NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08412162
|
Filing Dt:
|
03/28/1995
|
|
Title:
|
FLASH-EEPROM MEMORY ARRAY AND METHOD FOR BIASING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08412326
|
Filing Dt:
|
03/31/1995
|
|
Title:
|
THRESHOLD VOLTAGE MEASURING DEVICE FOR MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/1996
|
Application #:
|
08412550
|
Filing Dt:
|
03/29/1995
|
|
Title:
|
REDUNDANCY CIRCUITRY LAYOUT FOR A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/1996
|
Application #:
|
08422813
|
Filing Dt:
|
04/17/1995
|
|
Title:
|
MEMORY ARRAY CELL READING CIRCUIT WITH EXTRA CURRENT BRANCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/1998
|
Application #:
|
08432838
|
Filing Dt:
|
05/02/1995
|
|
Title:
|
SENSE AMPLIFIER WITH HYSTERESIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08454650
|
Filing Dt:
|
05/31/1995
|
|
Title:
|
FAILURE TOLERANT MEMORY DEVICE, IN PARTICULAR OF THE FLASH EEPROM TYPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08476547
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
READING CIRCUIT FOR MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08479081
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHOD FOR TESTING AN ELECTRICALLY ERASABLE AND PROGRAMMABLE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08503303
|
Filing Dt:
|
07/18/1995
|
|
Title:
|
NONVOLATILE MEMORY CELL AND A METHOD FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08521304
|
Filing Dt:
|
08/30/1995
|
|
Title:
|
CIRCUIT FOR IDENTIFYING A MEMORY CELL HAVING ERRONEOUS DATA STORED THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08521666
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
POWER-ON RESET CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/1997
|
Application #:
|
08533631
|
Filing Dt:
|
09/25/1995
|
|
Title:
|
BYTE ERASABLE EEPROM FULLY COMPATIBLE WITH A SINGLE POWER SUPPLY FLASH-EPROM PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08538161
|
Filing Dt:
|
10/02/1995
|
|
Title:
|
MEMORY DEVICE HAVING ERROR DETECTION AND CORRECTION FUNCTION, AND METHODS FOR READING, WRITING AND ERASING THE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/1997
|
Application #:
|
08538302
|
Filing Dt:
|
10/02/1995
|
|
Title:
|
INTEGRATED CIRCUIT WITH IMPROVED IMMUNITY TO LARGE METALLIZATION DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/1998
|
Application #:
|
08560090
|
Filing Dt:
|
11/17/1995
|
|
Title:
|
DECODER WITH REDUCED ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1997
|
Application #:
|
08560324
|
Filing Dt:
|
11/17/1995
|
|
Title:
|
SYNCHRONIZATION DEVICE FOR OUTPUT STAGES, PARTICULARLY FOR ELECTRONIC MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08567328
|
Filing Dt:
|
12/05/1995
|
|
Title:
|
CHARGE PUMP VOLTAGE MULTIPLIER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
08577125
|
Filing Dt:
|
12/22/1995
|
|
Title:
|
PROCESS FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE HAVING BETTER INTERFACE ADHESION BETWEEN DIELECTRIC LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
08592122
|
Filing Dt:
|
01/26/1996
|
|
Title:
|
PROGRAMMABLE MULTIBIT REGISTER FOR COINCIDENCE AND JUMP OPERATIONS AND COINCIDENCE FUSE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/1997
|
Application #:
|
08593650
|
Filing Dt:
|
01/29/1996
|
|
Title:
|
SERIAL DICHOTOMIC METHOD FOR SENSING MULTIPLE-LEVEL NON-VOLATILE MEMORY CELLS, AND SENSING CIRCUIT IMPLEMENTING SUCH METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/1998
|
Application #:
|
08602237
|
Filing Dt:
|
02/16/1996
|
|
Title:
|
INTEGRATED CIRCUITRY FOR CHECKING THE UTILIZATION RATE OF REDUNDANCY MEMORY ELEMENTS IN A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
08607779
|
Filing Dt:
|
02/27/1996
|
|
Title:
|
HIGH-VOLTAGE N-CHANNEL MOS TRANSISTOR AND ASSOCIATED MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
08628587
|
Filing Dt:
|
04/04/1996
|
|
Title:
|
PROGRAMMABLE MEMORY WITH SINGLE BIT ENCODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08631574
|
Filing Dt:
|
04/12/1996
|
|
Title:
|
VOLTAGE GENERATOR-BOOSTER FOR SUPPLYING A PULSATING VOLTAGE HAVING APPROXIMATELY CONSTANT VOLTAGE LEVELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/1998
|
Application #:
|
08639192
|
Filing Dt:
|
04/26/1996
|
|
Title:
|
SENSE AMPLIFIER HAVING CAPACITIVELY COUPLED INPUT FOR OFFSET COMPENSATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/1998
|
Application #:
|
08642325
|
Filing Dt:
|
05/03/1996
|
|
Title:
|
EEPROM MEMORY WITH CONTACTLESS MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08644892
|
Filing Dt:
|
05/10/1996
|
|
Title:
|
METHOD OF MANUFACTURING A MOS INTEGRATED CIRCUIT HAVING COMPONENTS WITH DIFFERENT DIELECTRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/1997
|
Application #:
|
08649468
|
Filing Dt:
|
05/17/1996
|
|
Title:
|
OUTPUT STAGE FOR INTEGRATED CIRCUITS, PARTICULARLY FOR ELECTRONIC MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08649857
|
Filing Dt:
|
05/03/1996
|
|
Title:
|
NONVOLATILE MEMORY DEVICE HAVING SECTORS OF SELECTABLE SIZE AND NUMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08665862
|
Filing Dt:
|
06/19/1996
|
|
Title:
|
NEGATIVE WORD LINE VOLTAGE REGULATION CIRCUIT FOR ELECTRICALLY ERASABLE SEMICONDUCTOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08667097
|
Filing Dt:
|
06/20/1996
|
|
Title:
|
PROCESS FOR FORMING AN INTEGRATED CIRCUIT COMPRISING NON-VOLATILE MEMORY CELLS AND SIDE TRANSISTORS AND CORRESPONDING IC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08670179
|
Filing Dt:
|
06/20/1996
|
|
Title:
|
PROCESS FOR FORMING AN INTEGRATED CIRCUIT COMPRISING NON-VOLATILE MEMORY CELLS AND SIDE TRANSISTORS OF AT LEAST TWO DIFFERENT TYPES, AND CORRESPONDING IC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08671848
|
Filing Dt:
|
06/28/1996
|
|
Title:
|
MEMORY DEVICE WITH IMPROVED YIELD AND RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08679656
|
Filing Dt:
|
07/12/1996
|
|
Title:
|
METHOD FOR SETTING THE THRESHOLD VOLTAGE OF A REFERENCE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08684192
|
Filing Dt:
|
07/19/1996
|
|
Title:
|
CHARGE PUMP CIRCUIT WITH MULTIPLE BOOST STAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08684406
|
Filing Dt:
|
07/19/1996
|
|
Title:
|
UNBALANCED LATCH AND FUSE CIRCUIT INCLUDING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08684431
|
Filing Dt:
|
07/19/1996
|
|
Title:
|
MODULATED SLOPE SIGNAL GENERATION CIRCUIT, PARTICULARLY FOR LATCH DATA SENSING ARRANGEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
08687145
|
Filing Dt:
|
07/24/1996
|
|
Title:
|
FLASH EEPROM WITH ON-CHIP ERASE SOURCE VOLTAGE GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08688956
|
Filing Dt:
|
07/31/1996
|
|
Title:
|
THRESHOLD DETECTING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/1998
|
Application #:
|
08690059
|
Filing Dt:
|
07/31/1996
|
|
Title:
|
PARALLEL-DICHOTOMIC SERIAL SENSING METHOD FOR SENSING MULTIPLE-LEVEL NON-VOLATILE MEMORY CELLS, AND SENSING CIRCUIT FOR ACTUATING SUCH METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/1998
|
Application #:
|
08690530
|
Filing Dt:
|
07/31/1996
|
|
Title:
|
CIRCUIT FOR READING NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08691796
|
Filing Dt:
|
08/02/1996
|
|
Title:
|
CURRENT DETECTING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
08692936
|
Filing Dt:
|
07/31/1996
|
|
Title:
|
FLASH EEPROM WITH INTEGRATED DEVICE FOR LIMITING THE ERASE SOURCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08720491
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
VOLTAGE REGULATOR FOR SEMICONDUCTOR NON-VOLATILE ELECTRICALLY PROGRAMMABLE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08722378
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
PARALLEL PROGRAMMING METHOD OF MEMORY WORDS AND CORRESPONDING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/1998
|
Application #:
|
08724495
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
HIERARCHIC MEMORY DEVICE HAVING AUXILIARY LINES CONNECTED TO WORD LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
08739997
|
Filing Dt:
|
10/30/1996
|
|
Title:
|
HIGH CAPACITY CAPACITOR AND CORRESPONDING MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08742978
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
ANALOG VOLTAGE-SIGNAL SELECTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/1998
|
Application #:
|
08751299
|
Filing Dt:
|
10/31/1996
|
|
Title:
|
NEGATIVE CHARGE PUMP CIRCUIT FOR ELECTRICALLY ERASABLE SEMICONDUCTOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08774860
|
Filing Dt:
|
12/24/1996
|
|
Title:
|
ERASING METHOD FOR A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08775111
|
Filing Dt:
|
12/30/1996
|
|
Title:
|
DEVICE FOR GENERATING AND REGULATING A GATE VOLTAGE IN A NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08777296
|
Filing Dt:
|
12/27/1996
|
|
Title:
|
MONOLITHICALLY INTEGRATED PROGRAMMABLE DEVICE HAVING ELEMENTARY MODULES CONNECTED ELECTRICALLY BY MEANS OF MEMORY CELLS OF THE FLASH TYPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08784967
|
Filing Dt:
|
01/16/1997
|
|
Title:
|
FABRICATION OF NATURAL TRANSISTORS IN A NONVOLATILE MEMORY PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08787494
|
Filing Dt:
|
01/21/1997
|
|
Title:
|
BOOST REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08787907
|
Filing Dt:
|
01/23/1997
|
|
Title:
|
ERASE VOLTAGE CONTROL CIRCUIT FOR AN ELECTRICALLY ERASABLE NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08788530
|
Filing Dt:
|
01/24/1997
|
|
Title:
|
METHOD FOR ERASING AN ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08790832
|
Filing Dt:
|
01/30/1997
|
|
Title:
|
ZERO CONSUMPTION POWER-ON-RESET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08791348
|
Filing Dt:
|
01/30/1997
|
|
Title:
|
MULTI-LEVEL MEMORY CIRCUITS AND CORRESPONDING READING AND WRITING METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08791700
|
Filing Dt:
|
01/30/1997
|
|
Title:
|
HIGH VOLTAGES DETECTOR CIRCUIT AND INTEGRATED CIRCUIT USING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08791746
|
Filing Dt:
|
01/30/1997
|
|
Title:
|
DECODING HIERARCHICAL ARCHITECTURE FOR HIGH INTEGRATION MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08792893
|
Filing Dt:
|
01/31/1997
|
|
Title:
|
PROCESS OF FABRICATING TUNNEL-OXIDE NONVOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08802619
|
Filing Dt:
|
02/19/1997
|
|
Title:
|
METHOD FOR IMPROVING THE INTERMEDIATE DIELECTRIC PROFILE, PARTICULARLY FOR NON-VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08807113
|
Filing Dt:
|
12/13/1996
|
|
Title:
|
PROCESS FOR FABRICATING A MICROTIP CATHODE ASSEMBLY FOR A FIELD EMISSION DISPLAY PANEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08807574
|
Filing Dt:
|
02/27/1997
|
|
Title:
|
ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY CELLS DEVICE FOR A REDUCED NUMBER OF PROGRAMMING CYCLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08811386
|
Filing Dt:
|
03/04/1997
|
|
Title:
|
CIRCUIT FOR THE GENERATION AND RESET OF TIMING SIGNAL USED FOR READING A MEMORY DEVICE
|
|
