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Patent #:
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Issue Dt:
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06/19/1990
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Application #:
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07285808
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Filing Dt:
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12/16/1988
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Title:
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CYLINDER DEFECT MANAGEMENT SYSTEM FOR DATA STORAGE SYSTEM
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Patent #:
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Issue Dt:
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12/24/1996
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Application #:
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08410712
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Filing Dt:
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03/27/1995
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Title:
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APPARATUS FOR REORDERING DATA FRAMES WITHIN AN INTERFERENCE DEVICE
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|
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Patent #:
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Issue Dt:
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08/19/1997
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Application #:
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08429916
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Filing Dt:
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04/27/1995
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Title:
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COMPUTER CONTROL DEVICE FOR MANAGING A TIMER ARRAY
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|
|
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Patent #:
|
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Issue Dt:
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01/12/1999
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Application #:
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08484592
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Filing Dt:
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06/07/1995
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Title:
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A MEMORY BUFFER SYSTEM USING A SINGLE POINTER TO REFERENCE MULTIPLE ASSOCIATED DATA
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|
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Patent #:
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Issue Dt:
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05/27/1997
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Application #:
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08488035
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Filing Dt:
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06/07/1995
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Title:
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BURST BROADCASTING ON A PERIPHERAL COMPONENT INTERCONNECT BUS
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|
|
|
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Patent #:
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|
Issue Dt:
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07/25/2000
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Application #:
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08762186
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Filing Dt:
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12/04/1996
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Title:
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COMPUTER NETWORK INTERFACE FOR DIRECT MAPPING OF DATA TRANSFERRED BETWEEN APPLICATIONS ON DIFFERENT HOST COMPUTERS FROM VIRTUAL ADDRESSES TO PHYSICAL MEMORY ADDRESSES
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|
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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08801471
|
Filing Dt:
|
02/18/1997
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Title:
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FIBRE CHANNEL SWITCHING FABRIC
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|
|
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08813271
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Filing Dt:
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03/10/1997
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Title:
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ELASTIC BUS INTERFACE DATA BUFFER
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|
|
Patent #:
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|
Issue Dt:
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04/28/1998
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Application #:
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08843315
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Filing Dt:
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04/15/1997
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|
Title:
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LINKED CACHES MEMORY FOR STORING UNITS OF INFORMATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
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05/21/2002
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Application #:
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08884794
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Filing Dt:
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06/30/1997
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|
Title:
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METHOD AND APPARATUS FOR NETWORK INTERFACE CARD LOAD BALANCING AND PORT AGGREGATION
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08907385
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Filing Dt:
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08/07/1997
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Title:
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METHODS AND APPARATUS FOR FIBRE CHANNEL INTERCONNECTION OF PRIVATE LOOP DEVICES
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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08937065
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Filing Dt:
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09/24/1997
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Title:
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COMMUNICATION PROCESSOR HAVING BUFFER LIST MODIFIER CONTROL BITS
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08937066
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Filing Dt:
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09/24/1997
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|
Title:
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FULL-DUPLEX COMMUNICATION PROCESSOR WHICH CAN BE USED FOR FIBRE CHANNEL FRAMES.
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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04/04/2000
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Application #:
|
08957856
|
Filing Dt:
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10/27/1997
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|
Title:
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BUFFERING DATA THAT FLOWS BETWEEN BUSES OPERATING AT DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
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Application #:
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09048930
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Filing Dt:
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03/26/1998
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|
Title:
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METHOD OF VALIDATION AND HOST BUFFER ALLOCATION FOR UNMAPPED FIBRE CHANNEL FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
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Application #:
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09065115
|
Filing Dt:
|
04/23/1998
|
|
Title:
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SYSTEM AND METHOD FOR SCHEDULING MESSAGE TRANSMISSION AND PROCESSING IN A DIGITAL DATA NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09065118
|
Filing Dt:
|
04/23/1998
|
|
Title:
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SYSTEM AND METHOD FOR REGULATING MESSAGE FLOW IN A DIGITAL DATA NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09067533
|
Filing Dt:
|
04/27/1998
|
|
Title:
|
SYSTEM FOR TRANSFERING INFORMATION BETWEEN DEVICES OVER VIRTUAL CIRCUIT ESTABLISHED THEREBETWEEN USING COMPUTER NETWORK A COMPUTER NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09071275
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROL OF SOFT HANDOFF USAGE IN RADIOCOMMUNICATION SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09071276
|
Filing Dt:
|
05/01/1998
|
|
Title:
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METHOD OF MAPPING FIBRE CHANNEL FRAMES BASED ON CONTROL AND TYPE HEADER FIELDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09071288
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
AUTOMATIC LOOP SEGMENT FAILURE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09071431
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
PROGRAMMABLE ERROR CONTROL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09071508
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
SCALABLE HUB
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09071632
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
HUB PORT WITHOUT JITTER TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09071678
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
AUTOMATIC ISOLATION IN LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09071930
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
ELIMINATION OF INVALID DATA IN LOOP NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09071932
|
Filing Dt:
|
05/01/1998
|
|
Title:
|
HUB PORT WITH CONSTANT PHASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09161158
|
Filing Dt:
|
09/25/1998
|
|
Title:
|
METHOD AND SYSTEM FOR PROGRAMMING FIRMWARE OVER A COMPUTER NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09177550
|
Filing Dt:
|
10/22/1998
|
|
Title:
|
NODE INSERTION AND REMOVAL IN A LOOP NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09204669
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
AUTOMATIC DETECTION OF 8B/10B DATA RATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09229464
|
Filing Dt:
|
01/12/1999
|
|
Title:
|
AN EFFICIENT TRANSMISSION BUFFER MANAGEMENT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09234231
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
SANITIZING FIBRE CHANNEL FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
09330398
|
Filing Dt:
|
06/11/1999
|
|
Title:
|
FIBRE CHANNEL SWITCHING FABRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
09330755
|
Filing Dt:
|
06/11/1999
|
|
Title:
|
FIBRE CHANNEL SWITCHING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2004
|
Application #:
|
09347709
|
Filing Dt:
|
07/03/1999
|
|
Title:
|
DISTRIBUTED SWITCH AND CONNECTION CONTROL ARRAGEMENT AND METHOD FOR DIGITAL COMMUNICATIONS NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09370096
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
VARIABLE ACCESS FAIRNESS IN A FIBRE CHANNEL ARBITRATED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09398520
|
Filing Dt:
|
09/15/1999
|
|
Title:
|
AUTOMATIC LOOP SEGMENT FAILURE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09398523
|
Filing Dt:
|
09/15/1999
|
|
Title:
|
AUTOMATIC ISOLATION IN LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09436620
|
Filing Dt:
|
11/09/1999
|
|
Title:
|
HIGH PERFORMANCE DIGITAL LOOP DIAGNOSTIC TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09611173
|
Filing Dt:
|
07/06/2000
|
|
Title:
|
INTERCONNECT SYSTEM FOR FIBRE CHANNEL ARBITRATED LOOP INCLUDING PRIVATE LOOP DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09640564
|
Filing Dt:
|
08/16/2000
|
|
Title:
|
DETECTING AND COUNTING NODE PORT LOOP INITIALIZATION ORIGINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09687259
|
Filing Dt:
|
10/12/2000
|
|
Title:
|
DETECTING AND COUNTING OPEN ORDERED SETS ORIGINATING FROM AN ATTACHED NODE PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
09687526
|
Filing Dt:
|
10/12/2000
|
|
Title:
|
METHOD FOR DETERMINING VALID BYTES FOR MULTIPLE-BYTE BURST MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09730149
|
Filing Dt:
|
12/04/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
OLD-PORT NODE DETECTION AND HUB PORT BYPASS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09774428
|
Filing Dt:
|
01/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/07/2001
| | | | |
|
Title:
|
SANITIZING FIBRE CHANNEL FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
09779195
|
Filing Dt:
|
02/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2002
| | | | |
|
Title:
|
HARDWARE INITIALIZATION WITH OR WITHOUT PROCESSOR INTERVENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
09849102
|
Filing Dt:
|
05/04/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
AUTOMATIC ISOLATION IN LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
09934977
|
Filing Dt:
|
08/21/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2002
| | | | |
|
Title:
|
PROTOCOL STACK FOR LINKING STORAGE AREA NETWORKS OVER AN EXISTING LAN, MAN, OR WAN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
09944716
|
Filing Dt:
|
08/31/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR VERIFYING THE HARDWARE IMPLEMENTATION OF TCP/IP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
10000848
|
Filing Dt:
|
11/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
DATA FORMATTER FOR SHIFTING DATA TO CORRECT DATA LANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10057626
|
Filing Dt:
|
01/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
SYSTEM FOR COMMUNICATION WITH A STORAGE AREA NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10113147
|
Filing Dt:
|
03/28/2002
|
|
Title:
|
SEPARABLE CYCLIC REDUNDANCY CHECK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10120733
|
Filing Dt:
|
04/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
RECEIVING DATA FROM INTERLEAVED MULTIPLE CONCURRENT TRANSACTIONS IN A FIFO MEMORY HAVING PROGRAMMABLE BUFFER ZONES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10125101
|
Filing Dt:
|
04/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
TRACKING DEFERRED DATA TRANSFERS ON A SYSTEM-INTERCONNECT BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10161922
|
Filing Dt:
|
06/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
PHASE-LOCKED LOOP (PLL) CIRCUIT FOR SELECTIVELY CORRECTING CLOCK SKEW IN DIFFERENT MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10179816
|
Filing Dt:
|
06/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
DIRECT MEMORY ACCESS (DMA) TRANSFER BUFFER PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10198867
|
Filing Dt:
|
07/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR FIBRE CHANNEL INTERCONNECTION OF PRIVATE LOOP DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10232819
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR TRANSMITTING DATA AT HIGH SPEED USING TCP/IP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10232821
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR RECEIVING DATA AT HIGH SPEED USING TCP/IP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10233302
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR HIGH SPEED DATA TRANSMISSION USING TCP/IP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10233303
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR IMPLEMENTING HOST-BASED SECURITY IN A COMPUTER NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10233304
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR PARTIALLY REORDERING DATA PACKETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10245436
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
RE-PROGRAMMABLE FINITE STATE MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10245437
|
Filing Dt:
|
09/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING NOISE IMMUNITY IN A DDR SDRAM SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10264580
|
Filing Dt:
|
10/04/2002
|
|
Title:
|
LINE RATE BUFFER USING SINGLE PORTED MEMORIES FOR VARIABLE LENGTH PACKETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
10268178
|
Filing Dt:
|
10/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR MAINTAINING ORDERED LINKED LISTS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10277922
|
Filing Dt:
|
10/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
Remote management system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10278189
|
Filing Dt:
|
10/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
SYSTEM WITH MULTIPLE PATH FAIL OVER, FAIL BACK AND LOAD BALANCING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
10280503
|
Filing Dt:
|
10/24/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
NETWORK CONFIGURATION SYNCHRONIZATION FOR HARDWARE ACCELERATED NETWORK PROTOCOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10288616
|
Filing Dt:
|
11/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
MESSAGE LOGGING
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10289128
|
Filing Dt:
|
11/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
Methods and apparatus for fibre channel interconnection of private loop devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
10289241
|
Filing Dt:
|
11/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/08/2003
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR FIBRE CHANNEL INTERCONNECTION OF PRIVATE LOOP DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10316604
|
Filing Dt:
|
12/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2003
| | | | |
|
Title:
|
SUPERCHARGE MESSAGE EXCHANGER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10324310
|
Filing Dt:
|
12/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
DIRECT MEMORY ACCESS CONTROLLER SYSTEM WITH MESSAGE-BASED PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10338629
|
Filing Dt:
|
01/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
FLOW-THROUGH REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10340078
|
Filing Dt:
|
01/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
SHARED MEMORY MANAGEMENT UTILIZING A FREE LIST OF BUFFER INDICES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10365963
|
Filing Dt:
|
02/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
Zero configuration auto-discovery for network storage
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10376354
|
Filing Dt:
|
02/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR MANAGING AVAILABLE MEMORY RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10376659
|
Filing Dt:
|
02/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
SANITIZING FIBRE CHANNEL FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10377496
|
Filing Dt:
|
02/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
ABSTRACTED NODE DISCOVERY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10379776
|
Filing Dt:
|
03/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2003
| | | | |
|
Title:
|
PHASE-LOCKED LOOP (PLL) CIRCUIT FOR SELECTIVELY CORRECTING CLOCK SKEW IN DIFFERENT MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10382728
|
Filing Dt:
|
03/04/2003
|
|
Title:
|
METHOD OF QUEUING FIBRE CHANNEL RECEIVE FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
10386642
|
Filing Dt:
|
03/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2003
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR REGULATING MESSAGE FLOW IN A DIGITAL DATA NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10396985
|
Filing Dt:
|
03/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
DIRECT DATA PLACEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10401459
|
Filing Dt:
|
03/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
LOCAL EMULATION OF DATA RAM UTILIZING WRITE-THROUGH CACHE HARDWARE WITHIN A CPU MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10402182
|
Filing Dt:
|
03/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
HARDWARE ASSISTED FIRMWARE TASK SCHEDULING AND MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10407031
|
Filing Dt:
|
04/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
VIRTUAL PERIPHERAL COMPONENT INTERCONNECT MULTIPLE-FUNCTION DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
10421495
|
Filing Dt:
|
04/22/2003
|
|
Title:
|
AVOIDING PORT COLLISIONS IN HARDWARE-ACCELERATED NETWORK PROTOCOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10422581
|
Filing Dt:
|
04/23/2003
|
|
Title:
|
REVERSE MESSAGE WRITES AND READS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10431647
|
Filing Dt:
|
05/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
LOOP NETWORK HUB USING LOOP INITIALIZATION INSERTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10434626
|
Filing Dt:
|
05/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
HOT SWAP COMPACT PCI POWER SUPPLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10440681
|
Filing Dt:
|
05/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
DYNAMICALLY SELF-ADJUSTING POLLING MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10440855
|
Filing Dt:
|
05/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
MEMORY DATA INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10452330
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR LOCAL AND DISTRIBUTED DATA MEMORY ACCESS ("DMA") CONTROL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10569322
|
Filing Dt:
|
02/17/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2008
| | | | |
|
Title:
|
Apparatus for Performing and Coordinating Data Storage Functions
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10572231
|
Filing Dt:
|
11/02/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
|
Title:
|
Data transfer management method, software and system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10609289
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
SPARSE AND NON-SPARSE DATA MANAGEMENT METHOD AND SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10609291
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
READ/WRITE COMMAND BUFFER POOL RESOURCE MANAGEMENT USING READ-PATH PREDICTION OF FUTURE RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
10612753
|
Filing Dt:
|
07/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR SWITCHING FIBRE CHANNEL ARBITRATED LOOP DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
10616862
|
Filing Dt:
|
07/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR DEVICE ACCESS FAIRNESS IN FIBRE CHANNEL ARBITRATED LOOP SYSTEMS
|
|
