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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08544435
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Filing Dt:
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11/17/1995
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Title:
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DYNAMICALLY RECONFIGURABLE DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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08946810
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Filing Dt:
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10/08/1997
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Title:
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UNIT FOR PROCESSING NUMERICAL AND LOGICAL OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA -FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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08946812
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Filing Dt:
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10/08/1997
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Title:
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METHOD OF THE SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08946998
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Filing Dt:
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10/08/1997
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Title:
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RUN-TIME RECONFIGURATION METHOD FOR PROGRAMMABLE UNITS
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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08946999
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Filing Dt:
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10/08/1997
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Title:
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METHOD FOR THE AUTOMATIC ADDRESS GENERATION OF MODULES WITHIN CLUSTERS COMPRISED OF A PLURALITY OF THESE MODULES
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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08947002
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Filing Dt:
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10/08/1997
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA-FLOW PROCESSORS (DFPS) AND UNITS WITH TWO-OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS AND THE LIKE)
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08947254
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Filing Dt:
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10/08/1997
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09145139
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Filing Dt:
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08/28/1998
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Title:
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INTERNAL BUS SYSTEM FOR DFPS AND UNITS WITH TWO-OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES, FOR MANAGING LARGE VOLUMES OF DATA WITH A HIGH INTERCONNECTION COMPLEXITY
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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09290342
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Filing Dt:
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04/12/1999
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Title:
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DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09329132
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Filing Dt:
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06/09/1999
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Title:
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RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09335974
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Filing Dt:
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06/18/1999
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09369653
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Filing Dt:
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08/06/1999
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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09494567
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Filing Dt:
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01/31/2000
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Title:
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RUN-TIME RECONFIGURATION METHOD FOR PROGRAMMABLE UNITS
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09537932
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Filing Dt:
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03/29/2000
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09598926
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Filing Dt:
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06/21/2000
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Title:
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METHOD OF REPAIRING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09613217
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Filing Dt:
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07/10/2000
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO-OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS,DPGAS, AND THE LIKE)
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09623052
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Filing Dt:
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01/09/2001
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Title:
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METHOD FOR HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO-OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGS, ETC.)--
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09623113
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Filing Dt:
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01/09/2001
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Title:
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METHOD FOR DEADLOCK-FREE CONFIGURATION OF DATAFLOW PROCESSORS AND MODULES WITH A TWO-OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09915213
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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09967497
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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09967847
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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METHOD FOR TRANSLATING PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
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Patent #:
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Issue Dt:
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07/24/2012
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Application #:
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10009649
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Filing Dt:
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05/29/2002
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Title:
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METHOD FOR INTERLEAVING A PROGRAM OVER A PLURALITY OF CELLS
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10116986
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Filing Dt:
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04/05/2002
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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INTERNAL BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES, FOR MANAGING LARGE VOLUMES OF DATA WITH A HIGH INTERCONNECTION COMPLEXITY
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10156397
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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RECONFIGURABLE MULTIDIMENSIONAL ARRAY PROCESSOR ALLOWING RUNTIME RECONFIGURATION OF SELECTED INDIVIDUAL ARRAY CELLS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10191926
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Filing Dt:
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07/09/2002
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO-OR
MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10265846
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10/07/2002
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10297959
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06/19/2003
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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PIPELINE CONFIGURATION UNIT PROTOCOLS AND COMMUNICATION
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Patent #:
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04/13/2004
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Application #:
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10304252
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11/26/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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L/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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11/22/2005
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Application #:
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10373595
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02/24/2003
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10379403
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03/04/2003
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Publication #:
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Pub Dt:
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04/29/2004
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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09/29/2009
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10398546
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01/20/2004
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07/01/2004
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Title:
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LOGIC CELL ARRAY AND BUS SYSTEM
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10/28/2008
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10469909
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09/21/2004
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03/24/2005
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Title:
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METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
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NONE
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10469910
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02/17/2005
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12/27/2007
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Method and Device for Treating and Processing Data
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08/25/2009
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10471061
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10/29/2004
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04/21/2005
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Title:
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METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA
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02/02/2010
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10480003
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06/18/2004
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12/02/2004
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Title:
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METHOD FOR PROCESSING DATA
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08/09/2011
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10486771
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09/20/2004
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04/21/2005
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Title:
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METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
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08/18/2009
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10487681
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08/05/2004
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Pub Dt:
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12/09/2004
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Title:
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PARALLEL TASK OPERATION IN PROCESSOR AND RECONFIGURABLE COPROCESSOR CONFIGURED BASED ON INFORMATION IN LINK LIST INCLUDING TERMINATION INFORMATION FOR SYNCHRONIZATION
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01/20/2009
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10487687
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08/25/2004
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01/27/2005
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Title:
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METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
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10/07/2008
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10490079
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11/02/2004
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03/10/2005
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Title:
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ROUTER
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Patent #:
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04/23/2013
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10490081
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11/29/2004
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11/02/2006
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Title:
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DEVICE INCLUDING A FIELD HAVING FUNCTION CELLS AND INFORMATION PROVIDING CELLS CONTROLLED BY THE FUNCTION CELLS
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10/02/2012
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10501845
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08/26/2005
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Pub Dt:
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04/27/2006
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Title:
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RECONFIGURABLE GENERAL PURPOSE PROCESSOR HAVING TIME RESTRICTED CONFIGURATIONS
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Patent #:
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NONE
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10501903
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03/01/2005
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06/16/2005
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Method of compilation
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02/28/2012
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10504684
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07/14/2006
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06/28/2007
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BUS SYSTEMS AND RECONFIGURATION METHODS
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NONE
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10508559
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06/20/2005
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04/06/2006
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Method and device for data processing
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02/02/2010
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10523763
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11/22/2005
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11/02/2006
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METHOD AND DEVICE FOR PROCESSING DATA
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04/10/2012
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10523764
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08/02/2005
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03/01/2007
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DATA PROCESSING METHOD AND DEVICE
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07/01/2008
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10526595
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01/09/2006
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08/31/2006
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RECONFIGURABLE SEQUENCER STRUCTURE
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NONE
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10551891
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08/28/2006
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01/11/2007
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Method and device for data processing
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NONE
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10561135
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04/25/2006
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04/12/2007
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Data processing device and method
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11/30/2010
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10570173
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11/10/2006
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05/17/2007
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DATA PROCESSING DEVICE AND METHOD
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09/01/2009
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10757900
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01/14/2004
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09/16/2004
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Title:
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METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT
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01/24/2006
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10764159
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01/23/2004
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Publication #:
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Pub Dt:
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11/17/2005
| | | | |
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Title:
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METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
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Patent #:
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07/21/2009
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10791501
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03/01/2004
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL
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Patent #:
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Issue Dt:
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07/10/2007
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10792168
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03/02/2004
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO-OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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10/30/2012
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11122500
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05/04/2005
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10/06/2005
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PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION
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10/26/2010
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11246617
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10/07/2005
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Publication #:
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Pub Dt:
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02/09/2006
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Title:
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PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE
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Patent #:
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Issue Dt:
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04/10/2012
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Application #:
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11820780
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Filing Dt:
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06/19/2007
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Publication #:
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Pub Dt:
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01/10/2008
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Title:
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PROCESSOR CHIP FOR RECONFIGURABLE DATA PROCESSING, FOR PROCESSING NUMERIC AND LOGIC OPERATIONS AND INCLUDING FUNCTION AND INTERCONNECTION CONTROL UNITS.
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11820943
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Filing Dt:
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06/20/2007
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Publication #:
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Pub Dt:
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11/01/2007
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11883670
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Filing Dt:
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02/11/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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Low Latency Massive Parallel Data Processing Device
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Patent #:
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Issue Dt:
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11/23/2010
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Application #:
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11890094
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Filing Dt:
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08/03/2007
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Publication #:
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Pub Dt:
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01/01/2009
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Title:
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METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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12008543
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Filing Dt:
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01/10/2008
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Publication #:
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Pub Dt:
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09/11/2008
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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12082073
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Filing Dt:
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04/07/2008
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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RECONFIGURABLE SEQUENCER STRUCTURE
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12087916
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Filing Dt:
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12/02/2008
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Publication #:
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Pub Dt:
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08/06/2009
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Title:
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HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWARE
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Patent #:
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Issue Dt:
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07/16/2013
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Application #:
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12109280
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Filing Dt:
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04/24/2008
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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Issue Dt:
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06/26/2012
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Application #:
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12247076
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Filing Dt:
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10/07/2008
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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ROUTER
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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12257075
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Filing Dt:
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10/23/2008
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12258100
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Filing Dt:
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10/24/2008
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Publication #:
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Pub Dt:
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06/04/2009
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Title:
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DATA PROCESSING DEVICE AND METHOD
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Patent #:
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Issue Dt:
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11/29/2011
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Application #:
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12354590
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Filing Dt:
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01/15/2009
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12368709
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Filing Dt:
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02/10/2009
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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A CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE CELLS THAT INCLUDE MULTI-BIT-WIDE INPUTS AND OUTPUTS
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12371040
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Filing Dt:
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02/13/2009
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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LOGIC CELL ARRAY AND BUS SYSTEM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12389116
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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METHOD AND DEVICE FOR TREATING AND PROCESSING DATA
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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12389274
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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07/02/2009
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Title:
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DATA PROCESSING DEVICE AND METHOD
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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12495465
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Filing Dt:
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06/30/2009
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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Data Processor Having Disabled Cores
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12496012
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Filing Dt:
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07/01/2009
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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12541299
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Filing Dt:
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08/14/2009
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Publication #:
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Pub Dt:
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02/18/2010
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Title:
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RECONFIGURABLE SEQUENCER STRUCTURE
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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12570943
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Filing Dt:
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09/30/2009
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Publication #:
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Pub Dt:
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06/17/2010
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Title:
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DATA PROCESSING METHOD AND DEVICE
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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12570984
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Filing Dt:
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09/30/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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12571173
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Filing Dt:
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09/30/2009
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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RECONFIGURABLE ELEMENTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12571195
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Filing Dt:
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09/30/2009
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Publication #:
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Pub Dt:
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05/13/2010
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Title:
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METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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12621860
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Filing Dt:
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11/19/2009
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Publication #:
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Pub Dt:
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03/18/2010
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Title:
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METHOD AND DEVICE FOR PROCESSING DATA
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12630139
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Filing Dt:
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12/03/2009
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Publication #:
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Pub Dt:
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04/01/2010
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12640201
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Filing Dt:
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12/17/2009
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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METHOD FOR PROCESSING DATA
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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12720898
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Filing Dt:
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03/10/2010
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Publication #:
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Pub Dt:
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09/09/2010
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Title:
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CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12729090
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Filing Dt:
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03/22/2010
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Publication #:
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Pub Dt:
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07/08/2010
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Title:
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Processor device having a sequential data processing unit and an arrangement of data processing elements
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12729932
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Filing Dt:
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03/23/2010
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Publication #:
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Pub Dt:
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06/30/2011
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Title:
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METHOD AND DEVICE FOR THREAD SCHEDULING WITHIN A PROCESSOR HAVING MULTIPLE HETEROGENEOUS CORES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12743356
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
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11/04/2010
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Title:
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RECONFIGURABLE FLOATING-POINT AND BIT-LEVEL DATA PROCESSING UNIT
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Patent #:
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NONE
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Application #:
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12745335
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Filing Dt:
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03/24/2011
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Publication #:
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Pub Dt:
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07/14/2011
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Title:
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METHOD FOR FACILITATING COMPILATION OF HIGH-LEVEL CODE FOR VARYING ARCHITECTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12746570
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Filing Dt:
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01/24/2011
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Publication #:
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Pub Dt:
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05/19/2011
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Title:
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USING FUNCTION CALLS AS COMPILER DIRECTIVES
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12836364
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07/14/2010
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Publication #:
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Pub Dt:
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01/13/2011
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Title:
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MULTI-CORE PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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12840477
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Filing Dt:
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07/21/2010
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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A PROCESSOR CHIP INCLUDING A PLURALITY OF CACHE ELEMENTS CONNECTED TO A PLURALITY OF PROCESSOR CORES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12840559
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Filing Dt:
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07/21/2010
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Publication #:
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Pub Dt:
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01/20/2011
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Title:
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CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12840742
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Filing Dt:
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07/21/2010
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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12909061
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Filing Dt:
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10/21/2010
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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12909150
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Filing Dt:
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10/21/2010
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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Issue Dt:
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09/02/2014
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Application #:
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12909203
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Filing Dt:
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10/21/2010
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Title:
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METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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12944068
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11/11/2010
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Publication #:
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Pub Dt:
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03/10/2011
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Title:
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PROCESSOR ARRANGEMENT ON A CHIP INCLUDING DATA PROCESSING, MEMORY, AND INTERFACE ELEMENTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12947167
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Filing Dt:
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11/16/2010
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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METHOD AND DEVICE FOR COUPLING A DATA PROCESSING UNIT AND A DATA PROCESSING ARRAY
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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13023796
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Filing Dt:
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02/09/2011
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Publication #:
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Pub Dt:
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06/16/2011
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Title:
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RECONFIGURABLE ELEMENTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13026475
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Filing Dt:
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02/14/2011
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Publication #:
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Pub Dt:
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05/02/2013
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Title:
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LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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13040769
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Filing Dt:
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03/04/2011
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Publication #:
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Pub Dt:
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06/23/2011
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Title:
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RECONFIGURABLE SEQUENCER STRUCTURE
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