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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:032457/0560   Pages: 5
Recorded: 03/17/2014
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 47
1
Patent #:
Issue Dt:
11/18/2014
Application #:
13405703
Filing Dt:
02/27/2012
Title:
DUTY CYCLE CORRECTION CIRCUIT OF DELAY LOCKED LOOP AND DELAY LOCKED LOOP HAVING THE DUTY CYCLE CORRECTION CIRCUIT
2
Patent #:
Issue Dt:
12/30/2014
Application #:
13747802
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
POWER SAVING IN WIRELESS NETWORK ENTITIES
3
Patent #:
Issue Dt:
02/02/2016
Application #:
13774415
Filing Dt:
02/22/2013
Title:
METHOD AND SYSTEM FOR MULTIPHASE CURRENT SENSING
4
Patent #:
Issue Dt:
06/03/2014
Application #:
13774477
Filing Dt:
02/22/2013
Title:
OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER
5
Patent #:
Issue Dt:
09/03/2019
Application #:
13803085
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
06/05/2014
Title:
NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME
6
Patent #:
Issue Dt:
12/01/2015
Application #:
13829392
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
09/18/2014
Title:
STRUCTURE AND METHOD FOR MANUFACTURE OF MEMORY DEVICE WITH THIN SILICON BODY
7
Patent #:
Issue Dt:
05/05/2015
Application #:
13829436
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
09/18/2014
Title:
Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof
8
Patent #:
Issue Dt:
04/14/2015
Application #:
13830054
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
07/10/2014
Title:
NONVOLATILE MEMORY WITH SPLIT SUBSTRATE SELECT GATES AND HEIRARCHICAL BITLINE CONFIGURATION
9
Patent #:
Issue Dt:
07/11/2017
Application #:
13830135
Filing Dt:
03/14/2013
Publication #:
Pub Dt:
04/24/2014
Title:
INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
10
Patent #:
Issue Dt:
05/12/2015
Application #:
13832785
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
05/15/2014
Title:
METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS
11
Patent #:
Issue Dt:
10/18/2016
Application #:
13835968
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
03/20/2014
Title:
FLASH MEMORY CONTROLLER HAVING DUAL MODE PIN-OUT
12
Patent #:
Issue Dt:
02/17/2015
Application #:
13836028
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
04/17/2014
Title:
SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE
13
Patent #:
NONE
Issue Dt:
Application #:
13836113
Filing Dt:
03/15/2013
Publication #:
Pub Dt:
05/01/2014
Title:
FLASH MEMORY CONTROLLER HAVING MULTI MODE PIN-OUT
14
Patent #:
NONE
Issue Dt:
Application #:
13951058
Filing Dt:
07/25/2013
Publication #:
Pub Dt:
08/07/2014
Title:
DISPERSION TOLERANT OPTICAL SYSTEM AND METHOD
15
Patent #:
NONE
Issue Dt:
Application #:
13969058
Filing Dt:
08/16/2013
Publication #:
Pub Dt:
02/19/2015
Title:
Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors
16
Patent #:
Issue Dt:
09/12/2017
Application #:
14025203
Filing Dt:
09/12/2013
Title:
INTEGRATED CIRCUIT CHIP HAVING ANTI-MOISTURE-ABSORPTION FILM AT EDGE THEREOF AND METHOD OF FORMING ANTI-MOISTURE-ABSORPTION FILM
17
Patent #:
Issue Dt:
12/01/2015
Application #:
14044449
Filing Dt:
10/02/2013
Publication #:
Pub Dt:
04/02/2015
Title:
VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION
18
Patent #:
Issue Dt:
12/15/2015
Application #:
14046281
Filing Dt:
10/04/2013
Publication #:
Pub Dt:
10/16/2014
Title:
U-SHAPED COMMON-BODY TYPE CELL STRING
19
Patent #:
Issue Dt:
12/02/2014
Application #:
14057102
Filing Dt:
10/18/2013
Publication #:
Pub Dt:
04/24/2014
Title:
RING-OF-CLUSTERS NETWORK TOPOLOGIES
20
Patent #:
NONE
Issue Dt:
Application #:
14057724
Filing Dt:
10/18/2013
Publication #:
Pub Dt:
04/03/2014
Title:
OUTLET ADD-ON MODULE
21
Patent #:
Issue Dt:
06/09/2015
Application #:
14066748
Filing Dt:
10/30/2013
Publication #:
Pub Dt:
05/15/2014
Title:
PLL LOCKING CONTROL IN DAISY CHAINED MEMORY SYSTEM
22
Patent #:
NONE
Issue Dt:
Application #:
14080302
Filing Dt:
11/14/2013
Publication #:
Pub Dt:
03/13/2014
Title:
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
23
Patent #:
Issue Dt:
02/24/2015
Application #:
14082454
Filing Dt:
11/18/2013
Publication #:
Pub Dt:
03/13/2014
Title:
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
24
Patent #:
NONE
Issue Dt:
Application #:
14083668
Filing Dt:
11/19/2013
Publication #:
Pub Dt:
06/19/2014
Title:
MODULAR OUTLET
25
Patent #:
Issue Dt:
01/17/2017
Application #:
14089242
Filing Dt:
11/25/2013
Publication #:
Pub Dt:
03/27/2014
Title:
Semiconductor Memory Asynchronous Pipeline
26
Patent #:
NONE
Issue Dt:
Application #:
14092788
Filing Dt:
11/27/2013
Publication #:
Pub Dt:
03/27/2014
Title:
Wide Frequency Range Delay Locked Loop
27
Patent #:
Issue Dt:
09/12/2017
Application #:
14096867
Filing Dt:
12/04/2013
Publication #:
Pub Dt:
08/28/2014
Title:
POSITION DETERMINATION OF MOBILE STATIONS IN A WIRELESS NETWORK
28
Patent #:
Issue Dt:
05/11/2021
Application #:
14097506
Filing Dt:
12/05/2013
Publication #:
Pub Dt:
04/03/2014
Title:
SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS
29
Patent #:
Issue Dt:
07/14/2015
Application #:
14097614
Filing Dt:
12/05/2013
Publication #:
Pub Dt:
04/03/2014
Title:
METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH
30
Patent #:
Issue Dt:
08/25/2015
Application #:
14101507
Filing Dt:
12/10/2013
Publication #:
Pub Dt:
04/10/2014
Title:
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
31
Patent #:
NONE
Issue Dt:
Application #:
14102063
Filing Dt:
12/10/2013
Publication #:
Pub Dt:
06/11/2015
Title:
System and Method of Operation for High Capacity Solid-State Drive
32
Patent #:
Issue Dt:
01/26/2016
Application #:
14107735
Filing Dt:
12/16/2013
Publication #:
Pub Dt:
04/17/2014
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
33
Patent #:
NONE
Issue Dt:
Application #:
14134996
Filing Dt:
12/19/2013
Publication #:
Pub Dt:
04/17/2014
Title:
Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory
34
Patent #:
Issue Dt:
09/30/2014
Application #:
14135167
Filing Dt:
12/19/2013
Publication #:
Pub Dt:
04/17/2014
Title:
NETWORK ARCHITECTURE FOR DATA COMMUNICATION
35
Patent #:
Issue Dt:
05/01/2018
Application #:
14141686
Filing Dt:
12/27/2013
Title:
SYNCHRONOUS MEMORY READ DATA CAPTURE
36
Patent #:
Issue Dt:
01/12/2016
Application #:
14148336
Filing Dt:
01/06/2014
Publication #:
Pub Dt:
05/01/2014
Title:
METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES
37
Patent #:
Issue Dt:
04/28/2015
Application #:
14148436
Filing Dt:
01/06/2014
Publication #:
Pub Dt:
05/01/2014
Title:
Method, Apparatus, Signals and Media, for Selecting Operating Conditions of a Genset
38
Patent #:
Issue Dt:
04/26/2016
Application #:
14148895
Filing Dt:
01/07/2014
Publication #:
Pub Dt:
05/01/2014
Title:
METHOD AND SYSTEM FOR PACKET PROCESSING
39
Patent #:
Issue Dt:
02/09/2016
Application #:
14156047
Filing Dt:
01/15/2014
Publication #:
Pub Dt:
05/15/2014
Title:
MEMORY WITH OUTPUT CONTROL
40
Patent #:
Issue Dt:
10/28/2014
Application #:
14157824
Filing Dt:
01/17/2014
Publication #:
Pub Dt:
05/15/2014
Title:
FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE
41
Patent #:
Issue Dt:
08/25/2015
Application #:
14158116
Filing Dt:
01/17/2014
Publication #:
Pub Dt:
05/15/2014
Title:
NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE
42
Patent #:
Issue Dt:
10/07/2014
Application #:
14158215
Filing Dt:
01/17/2014
Publication #:
Pub Dt:
05/15/2014
Title:
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
43
Patent #:
NONE
Issue Dt:
Application #:
14159823
Filing Dt:
01/21/2014
Publication #:
Pub Dt:
05/15/2014
Title:
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
44
Patent #:
NONE
Issue Dt:
Application #:
14163499
Filing Dt:
01/24/2014
Publication #:
Pub Dt:
05/22/2014
Title:
MULTI-CHIP PACKAGE WITH PILLAR CONNECTION
45
Patent #:
NONE
Issue Dt:
Application #:
14172946
Filing Dt:
02/05/2014
Publication #:
Pub Dt:
07/10/2014
Title:
SCALABLE MEMORY SYSTEM
46
Patent #:
NONE
Issue Dt:
Application #:
14175142
Filing Dt:
02/07/2014
Publication #:
Pub Dt:
06/05/2014
Title:
METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY
47
Patent #:
NONE
Issue Dt:
Application #:
14180582
Filing Dt:
02/14/2014
Publication #:
Pub Dt:
10/02/2014
Title:
ASYNCHRONOUS BRIDGE CHIP
Assignor
1
Exec Dt:
01/01/2014
Assignee
1
11 HINES RD, SUITE 203
OTTAWA, ONTARIO, CANADA K2K2X1
Correspondence name and address
CPA GLOBAL LIMITED
LIBERATION HOUSE
CASTLE STREET
ST HELIER, JE1 1BL JERSEY

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