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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:034591/0627   Pages: 8
Recorded: 12/10/2014
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 59
1
Patent #:
Issue Dt:
01/05/1999
Application #:
08710230
Filing Dt:
09/13/1996
Title:
DRIVER CIRCUIT WITH PRECHARGE AND ACTIVE HOLD
2
Patent #:
Issue Dt:
04/14/1998
Application #:
08724595
Filing Dt:
09/30/1996
Title:
ESD PROTECTION SYSTEM FOR AN INTEGRATED CIRCUIT WITH MULTIPLE POWER SUPPLY NETWORKS
3
Patent #:
Issue Dt:
03/09/1999
Application #:
08758606
Filing Dt:
11/27/1996
Title:
INPUT COMPARISON CIRCUITRY AND METHOD FOR A PROGRAMMABLE STATE MACHINE
4
Patent #:
Issue Dt:
10/17/2000
Application #:
08910847
Filing Dt:
08/13/1997
Title:
MEMORY CONTROLLER SUPPORTING DRAM CIRCUITS WITH DIFFERENT OPERATING SPEEDS
5
Patent #:
Issue Dt:
07/10/2001
Application #:
09114426
Filing Dt:
07/13/1998
Title:
METHOD AND APPARATUS FOR SUPPORTING HETEROGENEOUS MEMORY IN COMPUTER SYSTEMS
6
Patent #:
Issue Dt:
12/17/2002
Application #:
09266506
Filing Dt:
03/11/1999
Title:
METHOD AND APPARATUS FOR DISABLING A PROCESSOR IN A MULTIPROCESSOR COMPUTER
7
Patent #:
Issue Dt:
04/23/2002
Application #:
09295668
Filing Dt:
04/21/1999
Title:
SCALABLE SYSTEM CONTROL UNIT FOR DISTRIBUTED SHARED MEMORY MULTI-PROCESSOR SYSTEMS
8
Patent #:
Issue Dt:
07/17/2001
Application #:
09296038
Filing Dt:
04/21/1999
Title:
BACKUP REDUNDANT ROUTING SYSTEM CROSSBAR SWITCH ARCHITECTURE FOR MULTI-PROCESSOR SYSTEM INTERCONNECTION NETWORKS
9
Patent #:
Issue Dt:
07/22/2003
Application #:
09296045
Filing Dt:
04/21/1999
Publication #:
Pub Dt:
07/10/2003
Title:
SCALABLE, RE-CONFIGURABLE CROSSBAR SWITCH ARCHITECTURE FOR MULTI-PROCESSOR SYSTEM INTERCONNECTION NETWORKS
10
Patent #:
Issue Dt:
10/03/2000
Application #:
09368401
Filing Dt:
08/04/1999
Title:
MULTIPLE FREQUENCY SWITCHING POWER SUPPLY AND METHODS TO OPERATE A SWITCHING POWER SUPPLY
11
Patent #:
Issue Dt:
12/23/2003
Application #:
09392424
Filing Dt:
09/09/1999
Title:
SYSTEM FOR ENABLING A RECEIVER FOR ONLY A FIX AMOUNT OF TIME AND DISABLING THE RECEIVER THEREAFTER
12
Patent #:
Issue Dt:
07/24/2001
Application #:
09466493
Filing Dt:
12/17/1999
Title:
CONTENTION BASED LOGIC GATE DRIVING A LATCH AND DRIVEN BY PULSED CLOCK
13
Patent #:
Issue Dt:
09/04/2001
Application #:
09505561
Filing Dt:
02/17/2000
Title:
System and method for enabling/disabling sram banks for memory access
14
Patent #:
Issue Dt:
05/20/2003
Application #:
09514981
Filing Dt:
02/29/2000
Title:
READ AROUND SPECULATIVE LOAD
15
Patent #:
Issue Dt:
10/14/2003
Application #:
09540386
Filing Dt:
03/31/2000
Title:
METHOD AND APPARATUS FOR RESTORING COMPUTER RESOURCES
16
Patent #:
Issue Dt:
09/23/2003
Application #:
09540811
Filing Dt:
03/31/2000
Title:
COMPUTER SYSTEM HAVING SECURITY FEATURES FOR AUTHENTICATING DIFFERENT COMPONENTS
17
Patent #:
Issue Dt:
12/10/2002
Application #:
09726738
Filing Dt:
11/30/2000
Publication #:
Pub Dt:
05/30/2002
Title:
METHOD AND APPARATUS FOR SCHEDULING AND USING MEMORY CALIBRATIONS TO REDUCE MEMORY ERRORS IN HIGH SPEED MEMORY DEVICES
18
Patent #:
Issue Dt:
11/19/2002
Application #:
09727861
Filing Dt:
11/30/2000
Publication #:
Pub Dt:
05/30/2002
Title:
ADAPTIVE CALIBRATION TECHNIQUE FOR HIGH SPEED MEMORY DEVICES
19
Patent #:
Issue Dt:
02/11/2003
Application #:
09735436
Filing Dt:
12/12/2000
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD AND SYSTEM FOR DIRECTLY INTERCONNECTING STORAGE DEVICES TO CONTROLLER CARDS WITHIN A HIGHLY AVAILABLE STORAGE SYSTEM
20
Patent #:
Issue Dt:
12/03/2002
Application #:
09811243
Filing Dt:
03/16/2001
Publication #:
Pub Dt:
09/19/2002
Title:
SYSTEM AND METHOD UTILIZING ON-CHIP VOLTAGE MONITORING TO MANAGE POWER CONSUMPTION
21
Patent #:
Issue Dt:
09/13/2005
Application #:
09823596
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
10/03/2002
Title:
RETIRING EARLY-COMPLETION INSTRUCTIONS TO IMPROVE COMPUTER OPERATION THROUGHPUT
22
Patent #:
Issue Dt:
07/05/2005
Application #:
09864527
Filing Dt:
05/23/2001
Publication #:
Pub Dt:
11/28/2002
Title:
METHOD AND SYSTEM FOR CREATING SECURE ADDRESS SPACE USING HARDWARE MEMORY ROUTER
23
Patent #:
Issue Dt:
09/05/2006
Application #:
09896043
Filing Dt:
06/28/2001
Publication #:
Pub Dt:
01/02/2003
Title:
MEMORY TABLE AND MEMORY MANAGER FOR USE IN MANAGING MEMORY
24
Patent #:
Issue Dt:
03/04/2003
Application #:
09919294
Filing Dt:
07/31/2001
Publication #:
Pub Dt:
02/06/2003
Title:
CONDITIONAL CLOCK GATE THAT REDUCES DATA DEPENDENT LOADING ON A CLOCK NETWORK
25
Patent #:
Issue Dt:
11/07/2006
Application #:
09921467
Filing Dt:
08/03/2001
Publication #:
Pub Dt:
02/06/2003
Title:
OPPORTUNISTIC TRANSMISSION OF PORTABLY STORED DIGITAL DATA
26
Patent #:
Issue Dt:
06/26/2007
Application #:
09967268
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
METHOD AND APPARATUS FOR PRESERVING THE INTEGRITY OF A MANAGEMENT SUBSYSTEM ENVIRONMENT
27
Patent #:
Issue Dt:
07/01/2003
Application #:
10020114
Filing Dt:
12/18/2001
Publication #:
Pub Dt:
06/19/2003
Title:
ADAPTING VLSI CLOCKING TO SHORT TERM VOLTAGE TRANSIENTS
28
Patent #:
Issue Dt:
09/18/2007
Application #:
10033102
Filing Dt:
10/25/2001
Publication #:
Pub Dt:
05/29/2003
Title:
A METHOD OF PROTECTING USER PROCESS DATA IN A SECURE PLATFORM INACCESSIBLE TO THE OPERATING SYSTEM AND OTHER TASKS ON TOP OF THE SECURE PLATFORM
29
Patent #:
Issue Dt:
09/13/2005
Application #:
10044364
Filing Dt:
01/11/2002
Publication #:
Pub Dt:
01/02/2003
Title:
MANAGING LATENCIES IN ACCESSING MEMORY OF COMPUTER SYSTEMS
30
Patent #:
Issue Dt:
08/16/2005
Application #:
10053991
Filing Dt:
10/22/2001
Publication #:
Pub Dt:
04/24/2003
Title:
HIGH PERFORMANCE MULTI-CONTROLLER PROCESSING
31
Patent #:
Issue Dt:
08/15/2006
Application #:
10095125
Filing Dt:
03/11/2002
Publication #:
Pub Dt:
09/11/2003
Title:
DATA REDUNDANCY IN A HOT PLUGGABLE, LARGE SYMMETRIC MULTI-PROCESSOR SYSTEM
32
Patent #:
Issue Dt:
04/10/2007
Application #:
10164534
Filing Dt:
06/06/2002
Title:
SYSTEM WORKLOAD CHARACTERIZATION
33
Patent #:
Issue Dt:
07/06/2004
Application #:
10167507
Filing Dt:
06/13/2002
Publication #:
Pub Dt:
12/18/2003
Title:
DRIVER CIRCUIT CONNECTED TO A SWITCHED CAPACITOR AND METHOD OF OPERATING SAME
34
Patent #:
Issue Dt:
09/23/2003
Application #:
10205831
Filing Dt:
07/26/2002
Title:
METHOD AND APPARATUS FOR SAVING POWER IN DYNAMIC CIRCUITS
35
Patent #:
Issue Dt:
09/14/2004
Application #:
10212691
Filing Dt:
08/07/2002
Publication #:
Pub Dt:
02/12/2004
Title:
SYSTEM AND METHOD FOR USING A USING VENDOR-LONG DESCRIPTOR IN ACPI FOR THE CHIPSET REGISTERS
36
Patent #:
Issue Dt:
12/25/2007
Application #:
10246024
Filing Dt:
09/17/2002
Publication #:
Pub Dt:
03/18/2004
Title:
A SYSTEM AND METHOD FOR MANAGING POWER CONSUMPTION FOR A PLURALITY OF PROCESSORS BASED ON A SUPPLY VOLTAGE TO EACH PROCESSOR, TEMPERATURE, TOTAL POWER CONSUMPTION AND INDIVIDUAL PROCESSOR POWER CONSUMPTION
37
Patent #:
Issue Dt:
01/08/2008
Application #:
10355516
Filing Dt:
01/31/2003
Publication #:
Pub Dt:
08/05/2004
Title:
PHASE-LOCKED LOOP CONTROL CIRCUIT
38
Patent #:
Issue Dt:
03/04/2008
Application #:
10376390
Filing Dt:
02/28/2003
Publication #:
Pub Dt:
09/02/2004
Title:
REGISTER-BASED DE-SKEW SYSTEM AND METHOD FOR A SOURCE SYNCHRONOUS RECEIVER
39
Patent #:
Issue Dt:
04/10/2007
Application #:
10448763
Filing Dt:
05/30/2003
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND STRUCTURE FOR EXTERNAL CONTROL OF ESD PROTECTION IN ELECTRONIC CIRCUITS
40
Patent #:
Issue Dt:
12/25/2007
Application #:
10622672
Filing Dt:
07/18/2003
Publication #:
Pub Dt:
11/11/2004
Title:
RESET SCHEME FOR I/O PADS IN A SOURCE SYNCHRONOUS SYSTEM
41
Patent #:
Issue Dt:
03/20/2007
Application #:
10629989
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
SYSTEM AND METHOD FOR SYNCHRONIZING MULTIPLE SYNCHRONIZER CONTROLLERS
42
Patent #:
Issue Dt:
05/15/2007
Application #:
10630159
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
PROGRAMMABLE CLOCK SYNCHRONIZER
43
Patent #:
Issue Dt:
08/29/2006
Application #:
10630182
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
A CONTROLLER ARRANGEMENT FOR SYNCHRONIZER DATA TRANSFER BETWEEN A CORE CLOCK DOMAIN AND BUS CLOCK DOMAIN EACH HAVING ITS OWN INDIVIDUAL SYNCHRONIZING CONTROLLER
44
Patent #:
Issue Dt:
07/03/2007
Application #:
10630297
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
SYSTEM AND METHOD FOR MAINTAINING A STABLE SYNCHRONIZATION STATE IN A PROGRAMMABLE CLOCK SYNCHRONIZER
45
Patent #:
Issue Dt:
03/08/2005
Application #:
10630298
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
PHASE DETECTOR FOR A PROGRAMMABLE CLOCK SYNCHRONIZER
46
Patent #:
Issue Dt:
07/17/2007
Application #:
10630317
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
11/11/2004
Title:
SYSTEM AND METHOD FOR COMPENSATING FOR SKEW BETWEEN A FIRST CLOCK SIGNAL AND A SECOND CLOCK SIGNAL
47
Patent #:
Issue Dt:
11/28/2006
Application #:
10630994
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
PERSISTENT VOLATILE MEMORY FAULT TRACKING
48
Patent #:
Issue Dt:
03/25/2008
Application #:
10632885
Filing Dt:
08/01/2003
Publication #:
Pub Dt:
02/03/2005
Title:
DISTRIBUTED MULTIPLEXING CIRCUIT WITH BUILT-IN REPEATER
49
Patent #:
Issue Dt:
05/29/2007
Application #:
10651360
Filing Dt:
08/29/2003
Publication #:
Pub Dt:
12/23/2004
Title:
METHOD AND DEVICE FOR CIRCUIT CONTROL
50
Patent #:
Issue Dt:
07/03/2007
Application #:
10653760
Filing Dt:
09/03/2003
Publication #:
Pub Dt:
03/03/2005
Title:
SYSTEM AND METHOD TO MITIGATE VOLTAGE FLUCTUATIONS
51
Patent #:
Issue Dt:
01/02/2007
Application #:
10700919
Filing Dt:
11/04/2003
Publication #:
Pub Dt:
05/05/2005
Title:
SYSTEMS AND METHODS FOR GENERATING A CURRENT
52
Patent #:
Issue Dt:
04/10/2007
Application #:
10732687
Filing Dt:
12/10/2003
Publication #:
Pub Dt:
06/16/2005
Title:
OUTPUT BUFFER SLEW RATE CONTROL USING CLOCK SIGNAL
53
Patent #:
Issue Dt:
02/13/2007
Application #:
10744174
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
06/23/2005
Title:
SYSTEM AND METHOD FOR SIGNAL SYNCHRONIZATION BASED ON PLURAL CLOCK SIGNALS
54
Patent #:
Issue Dt:
10/10/2006
Application #:
10898693
Filing Dt:
07/23/2004
Publication #:
Pub Dt:
01/26/2006
Title:
PHASE DETECTION IN A SYNC PULSE GENERATOR
55
Patent #:
Issue Dt:
01/23/2007
Application #:
11038732
Filing Dt:
01/20/2005
Publication #:
Pub Dt:
07/20/2006
Title:
APPARATUS AND METHOD OF TUNING A DIGITALLY CONTROLLED INPUT/OUTPUT DRIVER
56
Patent #:
Issue Dt:
02/05/2008
Application #:
11047196
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD AND APPARATUS FOR PROVIDING THE PROPER VOLTAGE TO A MEMORY
57
Patent #:
Issue Dt:
10/18/2011
Application #:
11058554
Filing Dt:
02/15/2005
Publication #:
Pub Dt:
08/17/2006
Title:
SYSTEM AND METHOD FOR CONTROLLING POWER TO RESOURCES BASED ON HISTORICAL UTILIZATION DATA
58
Patent #:
Issue Dt:
12/12/2006
Application #:
11112121
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
FAULT DETECTION SYSTEM
59
Patent #:
Issue Dt:
03/30/2010
Application #:
11588918
Filing Dt:
10/27/2006
Publication #:
Pub Dt:
05/01/2008
Title:
LIMITING POWER STATE CHANGES TO A PROCESSOR OF A COMPUTER DEVICE
Assignor
1
Exec Dt:
11/03/2014
Assignee
1
390 MARCH ROAD
SUITE 100
OTTAWA, ONTARIO, CANADA K2K 0G7
Correspondence name and address
CONVERSANT INTELLECTUAL PROPERTY MGMT
5601 GRANITE PARKWAY
SUITE 1300
PLANO, TX 75024

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