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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08873384
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Filing Dt:
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06/11/1997
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Title:
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NROM FABRICATION METHOD WITH A PERIPHERY PORTION
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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08976303
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Filing Dt:
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11/21/1997
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Title:
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BIOS MEMORY AND MULTIMEDIA DATA STORAGE COMBINATION
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Patent #:
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Issue Dt:
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10/17/2000
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09166385
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Filing Dt:
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10/05/1998
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Title:
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WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09273430
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Filing Dt:
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03/19/1999
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Title:
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SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
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Patent #:
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Issue Dt:
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11/19/2002
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09304519
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Filing Dt:
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05/04/1999
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Title:
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ELECTRIC DEVICE WITH FLASH MEMORY BUILT-IN
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Patent #:
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Issue Dt:
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10/02/2001
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09365369
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Filing Dt:
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07/30/1999
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Title:
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NROM FABRICATION METHOD
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Patent #:
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Issue Dt:
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03/13/2001
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09409542
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Filing Dt:
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09/30/1999
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Title:
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METHOD AND APPARATUS FOR MEASURING SUBTHRESHOLD CURRENT IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09421762
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Filing Dt:
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10/19/1999
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Title:
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SEPARATE OUTPUT POWER SUPPLY TO REDUCE OUTPUT NOISE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09480868
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Filing Dt:
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01/10/2000
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Title:
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NONLINEAR STEPPED PROGRAMMING VOLTAGE
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Patent #:
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Issue Dt:
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06/05/2001
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09504186
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Filing Dt:
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02/15/2000
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Title:
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Two-stage pipeline sensing for page mode flash memory
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Patent #:
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06/12/2001
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09511652
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Filing Dt:
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02/22/2000
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Title:
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Symmetrical program and erase scheme to improve erase time degradation in NAND devices
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Patent #:
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Issue Dt:
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10/02/2001
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09513402
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Filing Dt:
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02/25/2000
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Title:
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MODE INDICATOR FOR MULTI-LEVEL MEMORY
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Patent #:
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Issue Dt:
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10/16/2001
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09514404
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Filing Dt:
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02/28/2000
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Title:
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Register driven means to control programming voltages
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09563923
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Filing Dt:
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05/04/2000
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Title:
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Patent #:
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Issue Dt:
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06/18/2002
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09654831
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09/01/2000
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Title:
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ARRANGEMENT FOR PROGRAMMING SELECTED DEVICE REGISTERS DURING INITIALIZATION FROM AN EXTERNAL MEMORY
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10/08/2002
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09663765
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09/18/2000
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Title:
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VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
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Patent #:
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03/04/2003
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09665916
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09/20/2000
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Title:
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NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
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Patent #:
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Issue Dt:
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10/02/2001
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09712382
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11/13/2000
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Title:
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Acceleration voltage implementation for a high density flash memory device
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Patent #:
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08/09/2005
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09730586
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12/07/2000
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Pub Dt:
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11/11/2004
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Title:
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PROGRAMMING AND ERASING METHODS FOR AN NON-VOLATILE MEMORY CELL
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08/10/2004
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09768348
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01/25/2001
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03/07/2002
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Title:
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CACHE SYSTEM WITH LIMITED NUMBER OF TAG MEMORY ACCESSES
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Patent #:
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06/04/2002
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02/26/2001
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Title:
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Patent #:
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05/07/2002
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09822995
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Filing Dt:
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03/30/2001
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Title:
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I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
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03/18/2003
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09827756
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04/05/2001
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10/10/2002
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Title:
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ARCHITECTURE AND SCHEME FOR A NON-STROBED READ SEQUENCE
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Patent #:
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Issue Dt:
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06/24/2003
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09827757
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04/05/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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METHOD FOR PROGRAMMING A REFERENCE CELL
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Patent #:
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02/11/2003
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09854351
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05/10/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
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Patent #:
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10/15/2002
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09859193
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05/15/2001
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Pub Dt:
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03/14/2002
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Title:
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SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
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Patent #:
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07/23/2002
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09892189
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06/26/2001
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Title:
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MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
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03/18/2003
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09905421
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07/13/2001
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11/08/2001
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Title:
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MIXED MODE MULTI LEVEL MODE INDICTOR
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10/12/2004
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09966754
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10/01/2001
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05/02/2002
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NROM FABRICATION METHOD
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07/12/2005
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02/01/2002
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03/06/2003
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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12/28/2004
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02/11/2002
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08/30/2005
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05/28/2002
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01/02/2003
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PROGRAMMING AND ERASING METHODS FOR A NON -VOLATILE MEMORY CELL
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12/07/2004
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05/28/2002
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04/17/2003
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PROGRAMMING OF NONVOLATILE MEMORY CELLS
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03/02/2004
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08/05/2002
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08/21/2003
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07/27/2004
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09/30/2002
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06/12/2003
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09/07/2004
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06/05/2003
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11/06/2003
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06/20/2006
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04/29/2004
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08/17/2004
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02/14/2012
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11613620
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Filing Dt:
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12/20/2006
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Pub Dt:
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06/26/2008
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Title:
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NEAR FIELD COMMUNICATION, SECURITY AND NON-VOLATILE MEMORY INTEGRATED SUB-SYSTEM FOR EMBEDDED PORTABLE APPLICATIONS
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05/29/2012
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11613627
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12/20/2006
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06/26/2008
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Title:
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SECURE DATA VERIFICATION VIA BIOMETRIC INPUT
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05/29/2012
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11613691
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12/20/2006
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05/08/2008
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Title:
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MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
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05/29/2012
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11614257
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12/21/2006
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06/26/2008
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Title:
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NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
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01/15/2013
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11614309
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12/21/2006
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05/08/2008
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Title:
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SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
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02/01/2011
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11615492
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12/22/2006
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06/26/2008
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SYSTEMS AND METHODS FOR DISTINGUISHING BETWEEN ACTUAL DATA AND ERASED/BLANK MEMORY WITH REGARD TO ENCRYPTED DATA
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11/16/2010
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11618075
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12/29/2006
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07/03/2008
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Title:
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SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
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08/07/2012
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11625158
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01/19/2007
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07/24/2008
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BYTE MASK COMMAND FOR MEMORIES
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10/20/2009
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11636155
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12/07/2006
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06/28/2007
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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01/05/2010
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11642412
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12/19/2006
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Title:
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SYSTEM AND METHOD FOR MAINTAINING RAM COMMAND TIMING ACROSS PHASE-SHIFTED TIME DOMAINS
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07/21/2009
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11644031
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12/22/2006
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06/26/2008
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
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08/11/2009
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11644161
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12/22/2006
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06/26/2008
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
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10/16/2007
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11653655
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01/16/2007
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05/24/2007
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METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
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09/21/2010
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11687487
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03/16/2007
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09/18/2008
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STATE CHANGE SENSING
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06/22/2010
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11704908
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02/12/2007
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07/19/2007
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MEMORY ARRAY PROGRAMMING CIRCUIT AND A METHOD FOR USING THE CIRCUIT
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05/12/2009
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11767622
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06/25/2007
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12/25/2008
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COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES
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05/19/2009
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11834420
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08/06/2007
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02/12/2009
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READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
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04/07/2009
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11841468
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08/20/2007
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02/26/2009
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CMOS LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL STRUCTURE, OPERATION, AND ARRAY CONFIGURATION
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03/20/2012
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11870102
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10/10/2007
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04/16/2009
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RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS
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04/05/2011
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11874001
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10/17/2007
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04/23/2009
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OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
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10/30/2012
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11877497
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10/23/2007
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04/23/2009
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Title:
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LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE
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08/07/2012
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11928434
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10/30/2007
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04/30/2009
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Title:
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ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
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07/10/2012
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11949521
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12/03/2007
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06/04/2009
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DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
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06/29/2010
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11953689
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12/10/2007
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06/11/2009
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SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
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03/20/2012
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11957226
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12/14/2007
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06/18/2009
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INTELLIGENT MEMORY DATA MANAGEMENT
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09/04/2012
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11960601
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12/19/2007
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06/25/2009
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EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN
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09/04/2012
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11963078
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12/21/2007
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06/25/2009
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SYSTEM AND METHOD FOR OPTIMIZED ERROR CORRECTION IN FLASH MEMORY ARRAYS
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01/31/2012
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11979183
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10/31/2007
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05/01/2008
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NROM FRABRICATION METHOD
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04/26/2011
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11983041
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11/05/2007
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05/07/2009
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REDUCTION OF PACKAGE HEIGHT IN A STACKED DIE CONFIGURATION
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03/08/2011
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11984152
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11/14/2007
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05/15/2008
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METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE
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12/07/2010
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11987003
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11/26/2007
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06/12/2008
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PLL CIRCUIT
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08/30/2011
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12005323
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12/27/2007
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06/12/2008
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NROM FABRICATION METHOD
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12/11/2012
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12026299
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02/05/2008
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08/06/2009
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WEAR LEVELING MECHANISM USING A DRAM BUFFER
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01/08/2013
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12026302
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02/05/2008
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08/06/2009
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PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
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