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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:034817/0256   Pages: 7
Recorded: 01/26/2015
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
5966603
Issue Dt:
10/12/1999
Application #:
08873384
Filing Dt:
06/11/1997
Title:
NROM FABRICATION METHOD WITH A PERIPHERY PORTION
2
Patent #:
6297096
Issue Dt:
10/02/2001
Application #:
09365369
Filing Dt:
07/30/1999
Title:
NROM FABRICATION METHOD
3
Patent #:
6396741
Issue Dt:
05/28/2002
Application #:
09563923
Filing Dt:
05/04/2000
Title:
A METHOD OF PROGRAMMING NONVOLATILE MEMORY CELLS".
4
Patent #:
6928001
Issue Dt:
08/09/2005
Application #:
09730586
Filing Dt:
12/07/2000
Publication #:
US20040222437
Pub Dt:
11/11/2004
Title:
PROGRAMMING AND ERASING METHODS FOR AN NON-VOLATILE MEMORY CELL
5
Patent #:
6490204
Issue Dt:
12/03/2002
Application #:
09827596
Filing Dt:
04/05/2001
Publication #:
US20010048614
Pub Dt:
12/06/2001
Title:
PROGRAMMING AND ERASING METHODS FOR A REFERENCE CELL OF AN NROM ARRAY
6
Patent #:
6535434
Issue Dt:
03/18/2003
Application #:
09827756
Filing Dt:
04/05/2001
Publication #:
US20020145918
Pub Dt:
10/10/2002
Title:
ARCHITECTURE AND SCHEME FOR A NON-STROBED READ SEQUENCE
7
Patent #:
6584017
Issue Dt:
06/24/2003
Application #:
09827757
Filing Dt:
04/05/2001
Publication #:
US20020145911
Pub Dt:
10/10/2002
Title:
METHOD FOR PROGRAMMING A REFERENCE CELL
8
Patent #:
6803279
Issue Dt:
10/12/2004
Application #:
09966754
Filing Dt:
10/01/2001
Publication #:
US20020052081
Pub Dt:
05/02/2002
Title:
NROM FABRICATION METHOD
9
Patent #:
6937521
Issue Dt:
08/30/2005
Application #:
10155216
Filing Dt:
05/28/2002
Publication #:
US20030002345
Pub Dt:
01/02/2003
Title:
PROGRAMMING AND ERASING METHODS FOR A NON -VOLATILE MEMORY CELL
10
Patent #:
6829172
Issue Dt:
12/07/2004
Application #:
10155217
Filing Dt:
05/28/2002
Publication #:
US20030072192
Pub Dt:
04/17/2003
Title:
PROGRAMMING OF NONVOLATILE MEMORY CELLS
11
Patent #:
6700818
Issue Dt:
03/02/2004
Application #:
10211248
Filing Dt:
08/05/2002
Publication #:
US20030156456
Pub Dt:
08/21/2003
Title:
METHOD FOR OPERATING A MEMORY DEVICE
12
Patent #:
7064983
Issue Dt:
06/20/2006
Application #:
10454820
Filing Dt:
06/05/2003
Publication #:
US20040081010
Pub Dt:
04/29/2004
Title:
METHOD FOR PROGRAMMING A REFERENCE CELL
13
Patent #:
6963505
Issue Dt:
11/08/2005
Application #:
10695448
Filing Dt:
10/29/2003
Publication #:
US20040136220
Pub Dt:
07/15/2004
Title:
METHOD CIRCUIT AND SYSTEM FOR DETERMINING A REFERENCE VOLTAGE
14
Patent #:
6992932
Issue Dt:
01/31/2006
Application #:
10695457
Filing Dt:
10/29/2003
Publication #:
US20040136236
Pub Dt:
07/15/2004
Title:
METHOD CIRCUIT AND SYSTEM FOR READ ERROR DETECTION IN A NON-VOLATILE MEMORY ARRAY
15
Patent #:
7079420
Issue Dt:
07/18/2006
Application #:
10747217
Filing Dt:
12/30/2003
Publication #:
US20050058005
Pub Dt:
03/17/2005
Title:
METHOD FOR OPERATING A MEMORY DEVICE
16
Patent #:
7095655
Issue Dt:
08/22/2006
Application #:
10916413
Filing Dt:
08/12/2004
Publication #:
US20060034122
Pub Dt:
02/16/2006
Title:
DYNAMIC MATCHING OF SIGNAL PATH AND REFERENCE PATH FOR SENSING
17
Patent #:
7190620
Issue Dt:
03/13/2007
Application #:
11029380
Filing Dt:
01/06/2005
Publication #:
US20050117395
Pub Dt:
06/02/2005
Title:
METHOD FOR OPERATING A MEMORY DEVICE
18
Patent #:
7352627
Issue Dt:
04/01/2008
Application #:
11324718
Filing Dt:
01/03/2006
Publication #:
US20070153575
Pub Dt:
07/05/2007
Title:
METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
19
Patent #:
7420848
Issue Dt:
09/02/2008
Application #:
11328015
Filing Dt:
01/09/2006
Publication #:
US20060126396
Pub Dt:
06/15/2006
Title:
METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
20
Patent #:
7512009
Issue Dt:
03/31/2009
Application #:
11413962
Filing Dt:
04/27/2006
Publication #:
US20060268621
Pub Dt:
11/30/2006
Title:
METHOD FOR PROGRAMMING A REFERENCE CELL
21
Patent #:
7466594
Issue Dt:
12/16/2008
Application #:
11490539
Filing Dt:
07/19/2006
Publication #:
US20070171717
Pub Dt:
07/26/2007
Title:
DYNAMIC MATCHING OF SIGNAL PATH AND REFERENCE PATH FOR SENSING
22
Patent #:
7701779
Issue Dt:
04/20/2010
Application #:
11518192
Filing Dt:
09/11/2006
Publication #:
US20070253248
Pub Dt:
11/01/2007
Title:
METHOD FOR PROGRAMMING A REFERENCE CELL
23
Patent #:
7743230
Issue Dt:
06/22/2010
Application #:
11704908
Filing Dt:
02/12/2007
Publication #:
US20070168637
Pub Dt:
07/19/2007
Title:
MEMORY ARRAY PROGRAMMING CIRCUIT AND A METHOD FOR USING THE CIRCUIT
24
Patent #:
7715237
Issue Dt:
05/11/2010
Application #:
12071749
Filing Dt:
02/26/2008
Publication #:
US20080180999
Pub Dt:
07/31/2008
Title:
METHOD, SYSTEM AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
25
Patent #:
7742339
Issue Dt:
06/22/2010
Application #:
12087594
Filing Dt:
07/10/2008
Publication #:
US20090003073
Pub Dt:
01/01/2009
Title:
RD ALGORITHM IMPROVEMENT FOR NROM TECHNOLOGY
Assignor
1
SAIFUN SEMICONDUCTORS LTD.
Exec Dt:
07/28/2010
Assignee
1
SPANSION ISRAEL LTD.
17 GIBORAY YISRAEL STREET
SAPIR INDUSTRIAL AREA
NETANYA, ISRAEL 42504
Correspondence name and address
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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