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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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08172575
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Filing Dt:
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12/22/1993
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Title:
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DUAL-PORT CONTENT ADDRESSABLE MEMORY
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Patent #:
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Issue Dt:
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04/15/1997
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Application #:
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08235663
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Filing Dt:
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04/29/1994
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Title:
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METHOD AND APPARATUS FOR PRECHARGING MATCH OUTPUT IN A CASCADED CONTENT ADDRESSABLE MEMORY SYSTEM
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Patent #:
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Issue Dt:
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09/19/1995
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Application #:
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08281436
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Filing Dt:
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07/27/1994
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Title:
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FULLY STATIC CAM CELLS WITH LOW WRITE POWER AND METHODS OF MATCHING AND WRITING TO THE SAME
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08284347
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Filing Dt:
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08/01/1994
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Title:
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AN INTEGRATED CONTENT ADDRESSABLE MEMORY ARRAY WITH PROCESSING LOGIC AND A HOST COMPUTER INTERFACE
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08284372
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Filing Dt:
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08/01/1994
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Title:
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INSTRUCTION SET FOR A CONTENT ADDRESSABLE MEMORY ARRAY WITH READ/WRITE CIRCUITS AND AN INTERFACE REGISTER LOGIC BLOCK
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Patent #:
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Issue Dt:
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01/06/1998
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Application #:
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08729626
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Filing Dt:
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10/10/1996
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Title:
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CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY PARTITION CIRCUIT
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08822988
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Filing Dt:
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03/21/1997
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Title:
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WIDE BAND-WIDTH OPERATIONAL AMPLIFIER
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Patent #:
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|
Issue Dt:
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04/28/1998
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Application #:
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08822989
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Filing Dt:
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03/21/1997
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Title:
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COMPENSATION TECHNIQUE FOR PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08822990
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Filing Dt:
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03/21/1997
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Title:
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A PLL- BASED DIFFERENTIAL TUNER CIRCUIT
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Patent #:
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Issue Dt:
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12/22/1998
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Application #:
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08858997
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Filing Dt:
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05/20/1997
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Title:
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CONTENT ADDRESSABLE MEMORY MULTIPLE MATCH DETECTION CIRCUIT
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|
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Patent #:
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|
Issue Dt:
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10/12/1999
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Application #:
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08865819
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Filing Dt:
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05/30/1997
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Title:
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PRIORITY ENCODER FOR A CONTENT ADDRESSABLE MEMORY SYSTEM
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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08872530
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Filing Dt:
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06/11/1997
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Title:
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SCHEDULING TECHNIQUES FOR DATA CELLS IN A DATA SWITCH
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08883147
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Filing Dt:
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06/27/1997
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Title:
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METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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08885909
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Filing Dt:
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06/30/1997
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Title:
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DIFFERENTIAL DYNAMIC CONTENT ADDRESSABLE MEMORY AND HIGH SPEED NETWORK ADDRESS FILTERING
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|
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Patent #:
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|
Issue Dt:
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04/25/2000
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Application #:
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08924604
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Filing Dt:
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09/05/1997
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Title:
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A WRITEBACK CACHE CELL WITH A DUAL PORTED DIRTY BIT CELL AND METHOD FOR OPERATING SUCH A CACHE CELL
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|
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Patent #:
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|
Issue Dt:
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05/30/2000
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Application #:
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08959056
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Filing Dt:
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10/28/1997
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Title:
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ASYNCHRONOUS TRANSFER MODE SWITCHING ARCHITECTURES HAVING CONNECTION BUFFERS
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Patent #:
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|
Issue Dt:
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03/06/2001
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Application #:
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08967314
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Filing Dt:
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10/30/1997
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Title:
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SYNCHRONOUS CONTENT ADDRESSABLE MEMORY WITH SINGLE CYCLE OPERATION
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|
|
Patent #:
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|
Issue Dt:
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05/30/2000
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Application #:
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08982822
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Filing Dt:
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12/02/1997
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Title:
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CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09001110
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Filing Dt:
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12/30/1997
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Title:
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METHOD AND APPARATUS FOR CASCADING CONTENT ADDRESSABLE MEMORY DEVICES
|
|
|
Patent #:
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|
Issue Dt:
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02/22/2000
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Application #:
|
09004628
|
Filing Dt:
|
01/07/1998
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Title:
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LOW VOLTAGE TRANSMISSION LINE DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
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05/30/2000
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Application #:
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09044632
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Filing Dt:
|
03/19/1998
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Title:
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DIGITALLY CONTROLLED TUNER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
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01/02/2001
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Application #:
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09044710
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Filing Dt:
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03/19/1998
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Title:
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ANALOG ADAPTIVE LINE EQUALIZER
|
|
|
Patent #:
|
|
Issue Dt:
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07/18/2000
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Application #:
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09059614
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Filing Dt:
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04/13/1998
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Title:
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METHOD AND APPARATUS FOR COMMUNICATING SIGNALS BETWEEN CIRCUITS OPERATING AT DIFFERENT FREQUENCIES
|
|
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Patent #:
|
|
Issue Dt:
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07/04/2000
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Application #:
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09059615
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Filing Dt:
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04/13/1998
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Title:
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SYSTEM BUS ARBITRATOR FOR FACILITATING MULTIPLE TRANSACTIONS IN A COMPUTER SYSTEM
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|
|
Patent #:
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|
Issue Dt:
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03/06/2001
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Application #:
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09060228
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Filing Dt:
|
04/14/1998
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Title:
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ASYNCHRONOUS TRANSFER MODE TRAFFIC SHAPERS
|
|
|
Patent #:
|
|
Issue Dt:
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02/19/2002
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Application #:
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09062301
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Filing Dt:
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04/17/1998
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Title:
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METHOD AND APPARATUS FOR FORMING A VIRTUAL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
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05/29/2001
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Application #:
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09076336
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Filing Dt:
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05/11/1998
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A LEARN INSTRUCTION IN A DEPTH CASCADED CONTENT ADDRESSABLE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
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Application #:
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09076337
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Filing Dt:
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05/11/1998
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A LEARN INSTRUCTION IN A CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
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Application #:
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09111364
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Filing Dt:
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07/06/1998
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Title:
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METHOD AND APPARATUS FOR PERFORMING A READ NEXT HIGHEST PRIORITY MATCH INSTRUCTION IN A CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09126680
|
Filing Dt:
|
07/30/1998
|
Title:
|
CIRCUIT, ARCHITECTURE AND METHOD FOR ANALYZING THE OPERATION OF A DIGITAL PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09150517
|
Filing Dt:
|
09/09/1998
|
Title:
|
TERNARY SYNCHRONOUS CONTENT ADDRESSABLE MEMORY WITH SINGLE CYCLE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09185057
|
Filing Dt:
|
11/02/1998
|
Title:
|
LOW-POWER CONTENT ADDRESSABLE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09186562
|
Filing Dt:
|
11/05/1998
|
Title:
|
TERNARY CONTENT ADDRESSABLE MEMORY (CAM) HAVING FAST INSERTION AND DELETION OF DATA VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
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Application #:
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09187285
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Filing Dt:
|
11/05/1998
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Title:
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ENHANCED BINARY CONTENT ADDRESSABLE MEMORY FOR LONGEST PREFIX ADDRESS MATCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09225918
|
Filing Dt:
|
01/05/1999
|
Title:
|
METHOD FOR LONGEST PREFIX MATCHING IN A CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09225919
|
Filing Dt:
|
01/05/1999
|
Title:
|
MATCH LINE CONTROL CIRCUIT FOR CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09232413
|
Filing Dt:
|
01/15/1999
|
Title:
|
PIPELINING A CONTENT ADDRESSABLE MEMORY CELL ARRAY FOR LOW-POWER OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09235148
|
Filing Dt:
|
01/21/1999
|
Title:
|
FLOATING-POINT AND INTEGER MULTIPLY-ADD AND MULTIPLY-ACCUMULATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09238711
|
Filing Dt:
|
01/28/1999
|
Title:
|
ARCHITECTURE OF DATA COMMUNICATIONS SWITCHING SYSTEM AND ASSOCIATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09239210
|
Filing Dt:
|
01/28/1999
|
Title:
|
CIRCUIT ARCHITECTURE AND METHOD FOR DISPLAYING PORT STATUS IN DATA COMMUNICATIONS SWITCHING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09272710
|
Filing Dt:
|
03/19/1999
|
Title:
|
PRIORITY SELECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09273422
|
Filing Dt:
|
03/19/1999
|
Title:
|
PROGRAMMABLE MULTIPLE WORD WIDTH CAM ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09276885
|
Filing Dt:
|
03/26/1999
|
Title:
|
METHOD AND APPARATUS FOR SIMULTANEOUSLY PERFORMING A PLURALITY OF COMPARE OPERATIONS IN CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09277659
|
Filing Dt:
|
03/26/1999
|
Title:
|
APPARATUS AND METHOD FOR OPERATING A DUAL PORT MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09281620
|
Filing Dt:
|
03/30/1999
|
Title:
|
PROCESSOR WITH MULTIPLE EXECUTION UNITS AND LOCAL AND GLOBAL REGISTER BYPASSES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09338452
|
Filing Dt:
|
06/22/1999
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING A LONGEST PREFIX MATCH IN A CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09345224
|
Filing Dt:
|
06/30/1999
|
Title:
|
SIX TRANSISTOR CONTENT ADDRESSABLE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09347489
|
Filing Dt:
|
07/02/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY HAVING LONGEST PREFIX MATCHING FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09351541
|
Filing Dt:
|
07/12/1999
|
Title:
|
METHOD AND APPARATUS FOR SELECTIVE MATCH LINE PRE-CHARGING IN A CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09351545
|
Filing Dt:
|
07/12/1999
|
Title:
|
METHOD OF GENERATING AN ALMOST FULL FLAG AND A FULL FLAG IN A CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09351962
|
Filing Dt:
|
07/12/1999
|
Title:
|
METHOD AND APPARATUS FOR DETECTING MULTIPLE MATCHES IN A CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09359848
|
Filing Dt:
|
07/23/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY HAVING BINARY AND TERNARY MODES OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09361680
|
Filing Dt:
|
07/27/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY WITH LONGEST MATCH DETECT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09376397
|
Filing Dt:
|
08/18/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY WITH REDUCED TRANSIENT CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09391989
|
Filing Dt:
|
09/09/1999
|
Title:
|
SELECTIVE MATCH LINE PRE-CHARGING IN A PARTITIONED CONTENT ADDRESSABLE MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09392972
|
Filing Dt:
|
09/09/1999
|
Title:
|
SELECTIVE MATCH LINE DISCHARGING IN A PARTITIONED CONTENT ADDRESSABLE MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09394232
|
Filing Dt:
|
09/13/1999
|
Title:
|
MULTIPLE SIGNAL DETECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
09406170
|
Filing Dt:
|
09/23/1999
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING PACKET CLASSIFICATION FOR POLICY-BASED PACKET ROUTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09420516
|
Filing Dt:
|
10/18/1999
|
Title:
|
ROW REDUNDANCY FOR CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09422045
|
Filing Dt:
|
10/20/1999
|
Title:
|
METHOD AND APPARATUS FOR VECTOR REGISTER WITH SCALAR VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
09427971
|
Filing Dt:
|
10/27/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY HAVING SECTIONS WITH INDEPENDENTLY CONFIGURABLE ENTRY WIDTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09439317
|
Filing Dt:
|
11/12/1999
|
Title:
|
TERNARY CONTENT ADDRESSABLE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09439834
|
Filing Dt:
|
11/12/1999
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING A LONGEST PREFIX MATCH IN A SEGMENTED CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09439968
|
Filing Dt:
|
11/12/1999
|
Title:
|
INCREASING PRIORITY ENCODER SPEED USING THE MOST SIGNIFICANT BIT OF A PRIORITY ADDRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09440682
|
Filing Dt:
|
11/16/1999
|
Title:
|
CONTENT ADDRESSABLE MEMORY HAVING PRIORITIZATION OF UNOCCUPIED ENTRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09442042
|
Filing Dt:
|
11/12/1999
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING AN EXACT MATCH IN A TERNARY CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09455726
|
Filing Dt:
|
12/06/1999
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING THE ADDRESS OF THE HIGHEST PRIORITY MATCHING ENTRY IN A SEGMENTED CONTENT ADDRESSABLE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09465638
|
Filing Dt:
|
12/17/1999
|
Title:
|
METHOD AND APPARATUS FOR ORDERING ENTRIES IN A TERNARY CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09471103
|
Filing Dt:
|
12/21/1999
|
Title:
|
MATCH LINE CONTROL CIRCUIT FOR CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09495764
|
Filing Dt:
|
02/01/2000
|
Title:
|
Priority encoder/read only memory (ROM) combination
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09519524
|
Filing Dt:
|
03/06/2000
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Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
Title:
|
METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
09519605
|
Filing Dt:
|
03/06/2000
|
Title:
|
ARCHITECTURE FOR A MIXED VOICE AND DATA NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
09519607
|
Filing Dt:
|
03/06/2000
|
Title:
|
METHOD FOR A MIXED VOICE AND DATA DEVICE IN A HOME COMMUINCATIONS NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
09519608
|
Filing Dt:
|
03/06/2000
|
Title:
|
METHOD FOR A LINK TO A WIDE AREA NETWORK DEVICE IN A HOME COMMUNICATION NETWORK
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
09534548
|
Filing Dt:
|
03/27/2000
|
Title:
|
TOKEN OVER ETHERNET PROTOCOL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09562055
|
Filing Dt:
|
05/01/2000
|
Title:
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Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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09562056
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Filing Dt:
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05/01/2000
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Title:
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FLOATING POINT PIPELINE METHOD AND CIRCUIT FOR FAST INVERSE SQUARE ROOT CALCULATIONS
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09562057
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Filing Dt:
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05/01/2000
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Title:
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Digital programmable delay element
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09562058
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Filing Dt:
|
05/01/2000
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Title:
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Reduced line select decoder for a memory array
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Patent #:
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Issue Dt:
|
05/11/2004
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Application #:
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09562061
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Filing Dt:
|
05/01/2000
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Title:
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METHOD AND SYSTEM FOR REDUCING TAKEN BRANCH PENALTY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09562062
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Filing Dt:
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05/01/2000
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Title:
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SCALABLE REPLACEMENT METHOD AND SYSTEM IN A CACHE MEMORY
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Patent #:
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Issue Dt:
|
02/03/2009
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Application #:
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09562071
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Filing Dt:
|
05/01/2000
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Title:
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LOW-POWER CACHE SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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09564715
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Filing Dt:
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05/03/2000
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Title:
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PIPELINED PROCESSING WITH COMMIT SPECULATION STAGING BUFFER AND LOAD/STORE CENTRIC EXCEPTION HANDLING
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09569543
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Filing Dt:
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05/12/2000
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Title:
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CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09569818
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Filing Dt:
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05/12/2000
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Title:
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SINGLE PHASE EDGE TRIGGER REGISTER
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09570746
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Filing Dt:
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05/13/2000
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Title:
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Selective match line discharging in a partitioned content addressable memory array
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Patent #:
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Issue Dt:
|
07/03/2001
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Application #:
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09574744
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Filing Dt:
|
05/18/2000
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Title:
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Cam array with minimum cell size
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Patent #:
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Issue Dt:
|
07/17/2001
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Application #:
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09574747
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Filing Dt:
|
05/18/2000
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Title:
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Ternary CAM array
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09579844
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Filing Dt:
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05/26/2000
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Publication #:
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Pub Dt:
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03/14/2002
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Title:
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Asynchronous transfer mode switching architectures having connection buffers
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Patent #:
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Issue Dt:
|
07/13/2004
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Application #:
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09590428
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Filing Dt:
|
06/08/2000
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Title:
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METHOD AND APPARATUS FOR ADDRESS TRANSLATION IN A PARTITIONED CAM DEVICE
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09590642
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Filing Dt:
|
06/08/2000
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Title:
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Method and apparatus for partitioning a content addressable memory device
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09590775
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Filing Dt:
|
06/08/2000
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Title:
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METHOD AND APPARATUS FOR RE-ASSIGNING PRIORITY IN A PARTITIONED CAM DEVICE
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Patent #:
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Issue Dt:
|
06/19/2001
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Application #:
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09590779
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Filing Dt:
|
06/08/2000
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Title:
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Row redundancy in a content addressable memory
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Patent #:
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Issue Dt:
|
05/08/2001
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Application #:
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09590792
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Filing Dt:
|
06/08/2000
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Title:
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Spare address decoder
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Patent #:
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Issue Dt:
|
06/15/2004
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Application #:
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09594194
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Filing Dt:
|
06/14/2000
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Title:
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METHOD AND APPARATUS FOR DETECTING A MULTIPLE MATCH IN AN INTRA-ROW CONFIGURABLE CAM SYSTEM
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Patent #:
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Issue Dt:
|
05/06/2003
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Application #:
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09594195
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Filing Dt:
|
06/14/2000
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Title:
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INTER-ROW CONFIGURABILITY OF CONTENT ADDRESSABLE MEMORY
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Patent #:
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Issue Dt:
|
06/12/2001
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Application #:
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09594199
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Filing Dt:
|
06/14/2000
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Title:
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Method and apparatus for using an inter-row configurable content addressable memory
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Patent #:
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Issue Dt:
|
09/28/2004
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Application #:
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09594201
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Filing Dt:
|
06/14/2000
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Title:
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METHOD AND APPARATUS FOR DETECTING A MATCH IN AN INTRA-ROW CONFIGURABLE CAM SYSTEM
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Patent #:
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|
Issue Dt:
|
09/21/2004
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Application #:
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09594202
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Filing Dt:
|
06/14/2000
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Title:
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METHOD AND APPARATUS FOR DETERMINING A MATCH ADDRESS IN AN INTRA-ROW CONFIGURABLE CAM DEVICE
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Patent #:
|
|
Issue Dt:
|
06/26/2001
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Application #:
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09594203
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Filing Dt:
|
06/14/2000
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Title:
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Inter-row configurability of content addressable memory
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