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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:035613/0592   Pages: 24
Recorded: 05/07/2015
Conveyance: PATENT SECURITY AGREEMENT
Total properties: 260
Page 1 of 3
Pages: 1 2 3
1
Patent #:
Issue Dt:
04/25/2006
Application #:
10008466
Filing Dt:
11/09/2001
Publication #:
Pub Dt:
10/24/2002
Title:
METHODS OF POSITIONING COMPONENTS USING LIQUID PRIME MOVERS AND RELATED STRUCTURES
2
Patent #:
Issue Dt:
11/01/2005
Application #:
10601938
Filing Dt:
06/23/2003
Publication #:
Pub Dt:
03/18/2004
Title:
ELECTRONIC STRUCTURES INCLUDING CONDUCTIVE SHUNT LAYERS
3
Patent #:
Issue Dt:
02/24/2009
Application #:
10689976
Filing Dt:
10/21/2003
Publication #:
Pub Dt:
07/01/2004
Title:
STACKED ELECTRONIC STRUCTURES INCLUDING OFFSET SUBSTRATES
4
Patent #:
Issue Dt:
07/25/2006
Application #:
10780529
Filing Dt:
02/17/2004
Publication #:
Pub Dt:
10/21/2004
Title:
METHODS OF SELECTIVELY BUMPING INTEGRATED CIRCUIT SUBSTRATES AND RELATED STRUCTURES
5
Patent #:
Issue Dt:
01/02/2007
Application #:
10790967
Filing Dt:
03/02/2004
Publication #:
Pub Dt:
09/02/2004
Title:
LOW TEMPERATURE METHODS OF BONDING COMPONENTS AND RELATED STRUCTURES
6
Patent #:
Issue Dt:
02/23/2010
Application #:
10837830
Filing Dt:
05/03/2004
Publication #:
Pub Dt:
10/21/2004
Title:
ELECTRONIC DEVICES INCLUDING METALLURGY STRUCTURES FOR WIRE AND SOLDER BONDING
7
Patent #:
Issue Dt:
07/17/2007
Application #:
10879411
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
01/27/2005
Title:
METHODS OF FORMING CONDUCTIVE STRUCTURES INCLUDING TITANIUM-TUNGSTEN BASE LAYERS AND RELATED STRUCTURES
8
Patent #:
Issue Dt:
05/23/2006
Application #:
10965640
Filing Dt:
10/13/2004
Publication #:
Pub Dt:
06/23/2005
Title:
METHODS OF PROVIDING SOLDER STRUCTURES FOR OUT PLANE CONNECTIONS
9
Patent #:
Issue Dt:
09/23/2008
Application #:
11075474
Filing Dt:
03/09/2005
Publication #:
Pub Dt:
09/29/2005
Title:
METHODS OF FORMING BUMPS USING BARRIER LAYERS AS ETCH MASKS
10
Patent #:
Issue Dt:
06/16/2009
Application #:
11170220
Filing Dt:
06/29/2005
Publication #:
Pub Dt:
02/09/2006
Title:
METHODS OF FORMING LEAD FREE SOLDER BUMPS
11
Patent #:
Issue Dt:
05/08/2007
Application #:
11213414
Filing Dt:
08/26/2005
Publication #:
Pub Dt:
12/22/2005
Title:
OPTICAL STRUCTURES INCLUDING LIQUID BUMPS AND RELATED METHODS
12
Patent #:
Issue Dt:
11/20/2007
Application #:
11226569
Filing Dt:
09/14/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS OF FORMING ELECTRONIC STRUCTURES INCLUDING CONDUCTIVE SHUNT LAYERS AND RELATED STRUCTURES
13
Patent #:
Issue Dt:
05/12/2009
Application #:
11270366
Filing Dt:
11/09/2005
Publication #:
Pub Dt:
04/13/2006
Title:
NON-CIRCULAR VIA HOLES FOR BUMPING PADS AND RELATED STRUCTURES
14
Patent #:
Issue Dt:
02/09/2010
Application #:
11362964
Filing Dt:
02/27/2006
Publication #:
Pub Dt:
06/29/2006
Title:
SOLDER STRUCTURES FOR OUT OF PLANE CONNECTIONS
15
Patent #:
Issue Dt:
08/25/2009
Application #:
11446341
Filing Dt:
06/02/2006
Publication #:
Pub Dt:
10/19/2006
Title:
ELECTRONIC DEVICES INCLUDING OFFSET CONDUCTIVE BUMPS
16
Patent #:
Issue Dt:
06/23/2009
Application #:
11765648
Filing Dt:
06/20/2007
Publication #:
Pub Dt:
10/18/2007
Title:
CONDUCTIVE STRUCTURES INCLUDING TITANIUM-TUNGSTEN BASE LAYERS
17
Patent #:
Issue Dt:
02/01/2011
Application #:
11868785
Filing Dt:
10/08/2007
Publication #:
Pub Dt:
01/31/2008
Title:
METHODS OF FORMING ELECTRONIC STRUCTURES INCLUDING CONDUCTIVE SHUNT LAYERS AND RELATED STRUCTURES
18
Patent #:
Issue Dt:
09/16/2014
Application #:
12183778
Filing Dt:
07/31/2008
Title:
STACKED INVERTED FLIP CHIP PACKAGE AND FABRICATION METHOD
19
Patent #:
Issue Dt:
11/16/2010
Application #:
12194999
Filing Dt:
08/20/2008
Publication #:
Pub Dt:
12/18/2008
Title:
ELECTRONIC STRUCTURES INCLUDING BARRIER LAYERS DEFINING LIPS
20
Patent #:
Issue Dt:
01/01/2013
Application #:
12387691
Filing Dt:
05/05/2009
Title:
BUILDUP DIELECTRIC LAYER HAVING METALLIZATION PATTERN SEMICONDUCTOR PACKAGE FABRICATION METHOD
21
Patent #:
Issue Dt:
11/23/2010
Application #:
12437632
Filing Dt:
05/08/2009
Publication #:
Pub Dt:
08/27/2009
Title:
SOLDER STRUCTURES INCLUDING BARRIER LAYERS WITH NICKEL AND/OR COPPER
22
Patent #:
Issue Dt:
01/07/2014
Application #:
12474009
Filing Dt:
05/28/2009
Title:
STACKABLE PROTRUDING VIA PACKAGE AND METHOD
23
Patent #:
Issue Dt:
10/21/2014
Application #:
12481512
Filing Dt:
06/09/2009
Title:
FRAME INTERCONNECT FOR CONCENTRATED PHOTOVOLTAIC MODULE
24
Patent #:
Issue Dt:
07/17/2012
Application #:
12483913
Filing Dt:
06/12/2009
Title:
STACKABLE VIA PACKAGE AND METHOD
25
Patent #:
Issue Dt:
06/25/2013
Application #:
12537048
Filing Dt:
08/06/2009
Title:
STACKABLE VARIABLE HEIGHT VIA PACKAGE AND METHOD
26
Patent #:
Issue Dt:
05/14/2013
Application #:
12540593
Filing Dt:
08/13/2009
Title:
SEMICONDUCTOR DEVICE WITH METAL DAM AND FABRICATING METHOD
27
Patent #:
Issue Dt:
01/29/2013
Application #:
12548354
Filing Dt:
08/26/2009
Publication #:
Pub Dt:
03/03/2011
Title:
SEMICONDUCTOR DEVICE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING
28
Patent #:
Issue Dt:
05/21/2013
Application #:
12562387
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
STACKABLE WAFER LEVEL PACKAGE AND FABRICATING METHOD THEREOF
29
Patent #:
Issue Dt:
10/08/2013
Application #:
12568041
Filing Dt:
09/28/2009
Title:
ROUTABLE SINGLE LAYER SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING SAME
30
Patent #:
Issue Dt:
04/30/2013
Application #:
12569300
Filing Dt:
09/29/2009
Title:
SHIELDED EMBEDDED ELECTRONIC COMPONENT SUBSTRATE FABRICATION METHOD AND STRUCTURE
31
Patent #:
Issue Dt:
08/05/2014
Application #:
12573466
Filing Dt:
10/05/2009
Title:
FAN OUT BUILD UP SUBSTRATE STACKABLE PACKAGE AND METHOD
32
Patent #:
Issue Dt:
09/23/2014
Application #:
12577064
Filing Dt:
10/09/2009
Title:
CONCENTRATED PHOTOVOLTAIC RECEIVER PACKAGE WITH BUILT-IN CONNECTOR
33
Patent #:
Issue Dt:
01/29/2013
Application #:
12589500
Filing Dt:
10/23/2009
Title:
SHIELDED PACKAGE HAVING SHIELD LID
34
Patent #:
Issue Dt:
10/21/2014
Application #:
12626512
Filing Dt:
11/25/2009
Title:
THROUGH WAFER VIA STRUCTURES FOR CONCENTRATED PHOTOVOLTAIC CELLS
35
Patent #:
Issue Dt:
02/05/2013
Application #:
12627484
Filing Dt:
11/30/2009
Title:
BEND TEST METHOD AND APPARATUS FOR FLIP CHIP DEVICES
36
Patent #:
Issue Dt:
01/20/2015
Application #:
12630586
Filing Dt:
12/03/2009
Title:
THIN STACKABLE PACKAGE AND METHOD
37
Patent #:
Issue Dt:
06/27/2017
Application #:
12632170
Filing Dt:
12/07/2009
Title:
METHOD OF FORMING A PLURALITY OF ELECTRONIC COMPONENT PACKAGES
38
Patent #:
Issue Dt:
01/05/2016
Application #:
12690741
Filing Dt:
01/20/2010
Title:
TRACE STACKING STRUCTURE AND METHOD
39
Patent #:
Issue Dt:
09/17/2013
Application #:
12692397
Filing Dt:
01/22/2010
Title:
FLEX CIRCUIT PACKAGE AND METHOD
40
Patent #:
Issue Dt:
07/10/2012
Application #:
12692522
Filing Dt:
01/22/2010
Title:
EDGE MOUNT SEMICONDUCTOR PACKAGE
41
Patent #:
Issue Dt:
06/12/2012
Application #:
12708033
Filing Dt:
02/18/2010
Title:
TOP FEATURE PACKAGE AND METHOD
42
Patent #:
Issue Dt:
08/07/2012
Application #:
12708385
Filing Dt:
02/18/2010
Title:
POGO PIN INSERTING DEVICE FOR TESTING SEMICONDUCTOR DEVICES AND METHOD THEREFOR
43
Patent #:
Issue Dt:
12/10/2013
Application #:
12708432
Filing Dt:
02/18/2010
Title:
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS TO PREVENT SOLDER REFLOW
44
Patent #:
Issue Dt:
12/31/2013
Application #:
12727608
Filing Dt:
03/19/2010
Title:
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
45
Patent #:
Issue Dt:
01/29/2013
Application #:
12728119
Filing Dt:
03/19/2010
Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
46
Patent #:
Issue Dt:
10/22/2013
Application #:
12730062
Filing Dt:
03/23/2010
Title:
SEMICONDUCTOR PACKAGE THERMAL TAPE WINDOW FRAME FOR HEAT SINK ATTACHMENT
47
Patent #:
Issue Dt:
10/23/2012
Application #:
12751842
Filing Dt:
03/31/2010
Title:
SEMICONDUCTOR DEVICE FOR IMPROVING ELECTRICAL AND MECHANICAL CONNECTIVITY OF CONDUCTIVE PILLERS AND METHOD THEREFOR
48
Patent #:
Issue Dt:
12/04/2012
Application #:
12754837
Filing Dt:
04/06/2010
Title:
THROUGH VIA NUB REVEAL METHOD AND STRUCTURE
49
Patent #:
Issue Dt:
02/03/2015
Application #:
12779784
Filing Dt:
05/13/2010
Title:
SHIELDED ELECTRONIC COMPONENT PACKAGE AND METHOD
50
Patent #:
Issue Dt:
10/30/2012
Application #:
12787238
Filing Dt:
05/25/2010
Title:
STACKABLE TREATED VIA PACKAGE AND METHOD
51
Patent #:
Issue Dt:
10/23/2012
Application #:
12788845
Filing Dt:
05/27/2010
Title:
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
52
Patent #:
Issue Dt:
01/15/2013
Application #:
12791472
Filing Dt:
06/01/2010
Title:
CONDUCTIVE POLYMER LID FOR A SENSOR PACKAGE AND METHOD THEREFOR
53
Patent #:
Issue Dt:
03/18/2014
Application #:
12800757
Filing Dt:
05/21/2010
Title:
BLIND VIA CAPTURE PAD STRUCTURE FABRICATION METHOD
54
Patent #:
Issue Dt:
06/07/2016
Application #:
12815260
Filing Dt:
06/14/2010
Title:
CONCENTRATED PHOTOVOLTAIC RECEIVER MODULE WITH IMPROVED OPTICAL LIGHT GUIDE ASSEMBLY
55
Patent #:
Issue Dt:
08/13/2013
Application #:
12817923
Filing Dt:
06/17/2010
Title:
SYSTEM AND METHOD FOR LOWERING CONTACT RESISTANCE OF THE RADIO FREQUENCY (RF) SHIELD TO GROUND
56
Patent #:
Issue Dt:
08/19/2014
Application #:
12830138
Filing Dt:
07/02/2010
Title:
MOLDED LIGHT GUIDE FOR CONCENTRATED PHOTOVOLTAIC RECEIVER MODULE
57
Patent #:
Issue Dt:
11/27/2012
Application #:
12832202
Filing Dt:
07/08/2010
Title:
THIN STACKED INTERPOSER PACKAGE
58
Patent #:
Issue Dt:
11/27/2012
Application #:
12832202
Filing Dt:
07/08/2010
Title:
THIN STACKED INTERPOSER PACKAGE
59
Patent #:
Issue Dt:
08/16/2016
Application #:
12834682
Filing Dt:
07/12/2010
Title:
TOP PORT MEMS MICROPHONE PACKAGE AND METHOD
60
Patent #:
Issue Dt:
12/25/2012
Application #:
12846973
Filing Dt:
07/30/2010
Title:
STACKABLE PLASMA CLEANED VIA PACKAGE AND METHOD
61
Patent #:
Issue Dt:
05/14/2013
Application #:
12848820
Filing Dt:
08/02/2010
Title:
THROUGH VIA CONNECTED BACKSIDE EMBEDDED CIRCUIT FEATURES STRUCTURE AND METHOD
62
Patent #:
Issue Dt:
05/06/2014
Application #:
12848833
Filing Dt:
08/02/2010
Title:
FINGERPRINT SENSOR PACKAGE AND METHOD
63
Patent #:
Issue Dt:
10/08/2013
Application #:
12881905
Filing Dt:
09/14/2010
Title:
CONDUCTIVE PASTE AND MOLD FOR ELECTRICAL CONNECTION OF PHOTOVOLTAIC DIE TO SUBSTRATE
64
Patent #:
Issue Dt:
07/16/2013
Application #:
12898192
Filing Dt:
10/05/2010
Title:
SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODES PROTRUDING FROM DIELECTRIC LAYER
65
Patent #:
Issue Dt:
07/16/2013
Application #:
12907430
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
02/17/2011
Title:
ELECTRONIC STRUCTURES INCLUDING BARRIER LAYERS AND/OR OXIDATION BARRIERS DEFINING LIPS AND RELATED METHODS
66
Patent #:
Issue Dt:
10/30/2012
Application #:
12912490
Filing Dt:
10/26/2010
Title:
SEMICONDUCTOR DEVICE INCLUDING LEADFRAME WITH INCREASED I/O
67
Patent #:
Issue Dt:
12/25/2012
Application #:
12913325
Filing Dt:
10/27/2010
Title:
MECHANICAL TAPE SEPARATION PACKAGE AND METHOD
68
Patent #:
Issue Dt:
03/03/2015
Application #:
12913376
Filing Dt:
10/27/2010
Title:
LOW STRESS SUBSTRATE AND FORMATION METHOD
69
Patent #:
Issue Dt:
07/09/2013
Application #:
12917185
Filing Dt:
11/01/2010
Title:
STACKABLE PACKAGE AND METHOD
70
Patent #:
Issue Dt:
06/19/2012
Application #:
12924493
Filing Dt:
09/27/2010
Title:
STACKED REDISTRIBUTION LAYER (RDL) DIE ASSEMBLY PACKAGE
71
Patent #:
Issue Dt:
06/16/2015
Application #:
12924918
Filing Dt:
10/08/2010
Title:
SHIELDED TRACE STRUCTURE AND FABRICATION METHOD
72
Patent #:
Issue Dt:
07/24/2012
Application #:
12931325
Filing Dt:
01/27/2011
Title:
STACKABLE SEMICONDUCTOR PACKAGE
73
Patent #:
Issue Dt:
06/26/2012
Application #:
12931326
Filing Dt:
01/27/2011
Title:
EXPOSED DIE OVERMOLDED FLIP CHIP PACKAGE METHOD
74
Patent #:
Issue Dt:
08/29/2017
Application #:
12939588
Filing Dt:
11/04/2010
Title:
WAFER LEVEL FAN OUT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
75
Patent #:
Issue Dt:
09/03/2013
Application #:
12943540
Filing Dt:
11/10/2010
Title:
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
76
Patent #:
Issue Dt:
12/10/2013
Application #:
12945464
Filing Dt:
11/12/2010
Title:
ELECTRONIC ASSEMBLY HAVING INCREASED STANDOFF HEIGHT
77
Patent #:
Issue Dt:
11/04/2014
Application #:
12955509
Filing Dt:
11/29/2010
Publication #:
Pub Dt:
05/31/2012
Title:
MAGNETIC FIELD SIMULATOR FOR TESTING SINGULATED OR MULTI-SITE STRIP SEMICONDUCTOR DEVICE AND METHOD THEREFOR
78
Patent #:
Issue Dt:
07/29/2014
Application #:
12959851
Filing Dt:
12/03/2010
Title:
INTEGRATED PASSIVE DEVICE STRUCTURE AND METHOD
79
Patent #:
Issue Dt:
10/15/2013
Application #:
12959911
Filing Dt:
12/03/2010
Title:
SEMICONDUCTOR DEVICE HAVING OVERLAPPED VIA APERTURES
80
Patent #:
Issue Dt:
10/23/2012
Application #:
12963005
Filing Dt:
12/08/2010
Publication #:
Pub Dt:
04/14/2011
Title:
ELECTRONIC STRUCTURES INCLUDING CONDUCTIVE LAYERS COMPRISING COPPER AND HAVING A THICKNESS OF AT LEAST 0.5 MICROMETERS
81
Patent #:
Issue Dt:
03/18/2014
Application #:
12963431
Filing Dt:
12/08/2010
Title:
SEMICONDUCTOR DEVICE INCLUDING LEADFRAME WITH DOWNSETS
82
Patent #:
Issue Dt:
09/17/2013
Application #:
12964397
Filing Dt:
12/09/2010
Title:
LIGHT EMITTING DIODE (LED) PACKAGE AND METHOD
83
Patent #:
Issue Dt:
10/09/2012
Application #:
12964453
Filing Dt:
12/09/2010
Title:
DUAL LAMINATE PACKAGE STRUCTURE WITH EMBEDDED ELEMENTS
84
Patent #:
Issue Dt:
08/06/2013
Application #:
12964468
Filing Dt:
12/09/2010
Title:
CONCENTRATED PHOTOVOLTAIC RECEIVER PACKAGE WITH STACKED INTERNAL SUPPORT FEATURES
85
Patent #:
Issue Dt:
02/04/2014
Application #:
12968794
Filing Dt:
12/15/2010
Publication #:
Pub Dt:
04/07/2011
Title:
WAFERS INCLUDING PATTERNED BACK SIDE LAYERS THEREON
86
Patent #:
Issue Dt:
03/05/2013
Application #:
12985888
Filing Dt:
01/06/2011
Title:
THROUGH VIA RECESSED REVEAL STRUCTURE AND METHOD
87
Patent #:
Issue Dt:
11/27/2012
Application #:
13009690
Filing Dt:
01/19/2011
Title:
INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME
88
Patent #:
Issue Dt:
02/11/2014
Application #:
13015071
Filing Dt:
01/27/2011
Title:
SEMICONDUCTOR DEVICE INCLUDING LEADFRAME WITH A COMBINATION OF LEADS AND LANDS
89
Patent #:
Issue Dt:
10/13/2015
Application #:
13015445
Filing Dt:
01/27/2011
Title:
SEMICONDUCTOR DEVICE
90
Patent #:
Issue Dt:
12/31/2013
Application #:
13016343
Filing Dt:
01/28/2011
Title:
TOP PORT WITH INTERPOSER MEMS MICROPHONE PACKAGE AND METHOD
91
Patent #:
Issue Dt:
12/30/2014
Application #:
13034517
Filing Dt:
02/24/2011
Title:
SEMICONDUCTOR DEVICE WITH MICRO ELECTROMECHANICAL SYSTEM DIE
92
Patent #:
Issue Dt:
04/21/2015
Application #:
13046071
Filing Dt:
03/11/2011
Title:
STACKED AND STAGGERED DIE MEMS PACKAGE AND METHOD
93
Patent #:
Issue Dt:
07/23/2013
Application #:
13049647
Filing Dt:
03/16/2011
Title:
SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING DIELECTRIC LAYER FROM CRACKING
94
Patent #:
Issue Dt:
03/05/2013
Application #:
13065298
Filing Dt:
03/18/2011
Title:
FLIP CHIP BUMP STRUCTURE AND FABRICATION METHOD
95
Patent #:
Issue Dt:
02/26/2013
Application #:
13066137
Filing Dt:
04/06/2011
Title:
METAL ETCH STOP FABRICATION METHOD AND STRUCTURE
96
Patent #:
Issue Dt:
05/20/2014
Application #:
13094728
Filing Dt:
04/26/2011
Title:
Semiconductor Package with Patterning layer and Method of Making Same
97
Patent #:
Issue Dt:
09/17/2013
Application #:
13096359
Filing Dt:
04/28/2011
Title:
METAL MESH LID MEMS PACKAGE AND METHOD
98
Patent #:
Issue Dt:
05/20/2014
Application #:
13099680
Filing Dt:
05/03/2011
Title:
CONFORMAL SHIELD ON PUNCH QFN SEMICONDUCTOR PACKAGE
99
Patent #:
Issue Dt:
05/21/2013
Application #:
13100004
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
08/25/2011
Title:
Micro-Optical Device Packaging System
100
Patent #:
Issue Dt:
05/14/2013
Application #:
13109845
Filing Dt:
05/17/2011
Title:
SIDE LEADED, BOTTOM EXPOSED PAD AND BOTTOM EXPOSED LEAD FUSION QUAD FLAT SEMICONDUCTOR PACKAGE
Assignor
1
Exec Dt:
04/09/2015
Assignee
1
901 MAIN STREET, 11TH FLOOR
DALLAS, TEXAS 75202
Correspondence name and address
STEPHEN P. DEMM - HUNTON & WILLIAMS LLP
951 EAST BYRD STREET
RIVERFRONT PLAZA - EAST TOWER
RICHMOND, VA 23219-4074

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