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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13615980
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/31/2013
| | | | |
Title:
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METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13616322
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/17/2013
| | | | |
Title:
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GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13616337
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
Title:
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ELECTRONIC ASSEMBLY WITH DETACHABLE COOLANT MANIFOLD AND COOLANT-COOLED ELECTRONIC MODULE
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Patent #:
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Issue Dt:
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11/24/2015
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Application #:
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13616394
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/03/2013
| | | | |
Title:
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SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13616418
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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DOPED GRAPHENE FILMS WITH REDUCED SHEET RESISTANCE
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13616456
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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METHOD FOR JOINT MODELING OF MEAN AND DISPERSION
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13616472
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/03/2013
| | | | |
Title:
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METHOD FOR JOINT MODELING OF MEAN AND DISPERSION
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Patent #:
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Issue Dt:
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10/18/2016
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Application #:
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13616991
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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Equivalent Device Statistical Modeling for Bitline Leakage Modeling
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13616994
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13617060
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Filing Dt:
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09/14/2012
|
Publication #:
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Pub Dt:
|
01/03/2013
| | | | |
Title:
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INTERCONNECT STRUCTURE CONTAINING A METALLIC INTERFACIAL LAYER LOCATED AT A BOTTOM OF A VIA OPENING
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13617280
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Filing Dt:
|
09/14/2012
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Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13617283
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
02/20/2014
| | | | |
Title:
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TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13617420
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Filing Dt:
|
09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/17/2013
| | | | |
Title:
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PENTACENE-CARBON NANOTUBE COMPOSITE, METHOD OF FORMING THE COMPOSITE, AND SEMICONDUCTOR DEVICE INCLUDING THE COMPOSITE
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13617426
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
04/18/2013
| | | | |
Title:
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FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP
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|
Patent #:
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Issue Dt:
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03/18/2014
|
Application #:
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13617464
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/17/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13617528
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Filing Dt:
|
09/14/2012
|
Publication #:
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Pub Dt:
|
01/10/2013
| | | | |
Title:
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METHOD FOR SELF ALIGNED METAL GATE CMOS
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|
Patent #:
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Issue Dt:
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07/08/2014
|
Application #:
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13617558
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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RECOVERING THE STRUCTURE OF SPARSE MARKOV NETWORKS FROM HIGH-DIMENSIONAL DATA
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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13617575
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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01/28/2014
|
Application #:
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13617576
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Filing Dt:
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09/14/2012
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Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13617623
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/17/2013
| | | | |
Title:
|
FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
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Issue Dt:
|
12/17/2013
|
Application #:
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13617634
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
01/17/2013
| | | | |
Title:
|
PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE USING ANTIREFLECTIVE MATERIALS
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|
Patent #:
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Issue Dt:
|
06/04/2013
|
Application #:
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13617709
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
06/27/2013
| | | | |
Title:
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METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE
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|
Patent #:
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Issue Dt:
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12/09/2014
|
Application #:
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13617743
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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Patent #:
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|
Issue Dt:
|
10/29/2013
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Application #:
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13617749
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Filing Dt:
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09/14/2012
|
Publication #:
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Pub Dt:
|
01/10/2013
| | | | |
Title:
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DESIGN-DEPENDENT INTEGRATED CIRCUIT DISPOSITION
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Patent #:
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Issue Dt:
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10/28/2014
|
Application #:
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13617781
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
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Issue Dt:
|
11/11/2014
|
Application #:
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13617819
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
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13617847
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
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|
Issue Dt:
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01/07/2014
|
Application #:
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13617866
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Filing Dt:
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09/14/2012
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Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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METHOD FOR FABRICATING SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS
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Patent #:
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Issue Dt:
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01/14/2014
|
Application #:
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13617875
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/17/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13617901
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Filing Dt:
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09/14/2012
|
Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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METHOD AND APPARATUS FOR ONLINE SAMPLE INTERVAL DETERMINATION
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Patent #:
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Issue Dt:
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01/14/2014
|
Application #:
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13617919
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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FLUORINE-FREE FUSED RING HETEROAROMATIC PHOTOACID GENERATORS AND RESIST COMPOSITIONS CONTAINING THE SAME
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|
Patent #:
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|
Issue Dt:
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02/16/2016
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Application #:
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13617981
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
Title:
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IMAGE OPTIMIZATION USING PUPIL FILTERS IN PROJECTING PRINTING SYSTEMS WITH FIXED OR RESTRICTED ILLUMINATION ANGULAR DISTRIBUTION
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Patent #:
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Issue Dt:
|
10/08/2013
|
Application #:
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13617996
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Filing Dt:
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09/14/2012
|
Publication #:
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|
Pub Dt:
|
01/10/2013
| | | | |
Title:
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION
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Patent #:
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Issue Dt:
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06/10/2014
|
Application #:
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13618035
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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03/20/2014
| | | | |
Title:
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INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13618054
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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03/28/2013
| | | | |
Title:
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METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13618186
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13618240
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/30/2014
| | | | |
Title:
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BODY CONTACTS FOR FET IN SOI SRAM ARRAY
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Patent #:
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Issue Dt:
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11/15/2016
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Application #:
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13618600
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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13618744
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Filing Dt:
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09/14/2012
|
Publication #:
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Pub Dt:
|
01/10/2013
| | | | |
Title:
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SOFTWARE FACTORY READINESS REVIEW
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|
Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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13618821
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
03/21/2013
| | | | |
Title:
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SYSTEM AND METHOD FOR PROJECTION LITHOGRAPHY WITH IMMERSED IMAGE-ALIGNED DIFFRACTIVE ELEMENT
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13619473
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/17/2013
| | | | |
Title:
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PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS
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|
Patent #:
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Issue Dt:
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04/01/2014
|
Application #:
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13619493
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Filing Dt:
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09/14/2012
|
Publication #:
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Pub Dt:
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01/10/2013
| | | | |
Title:
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PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS
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|
Patent #:
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Issue Dt:
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10/14/2014
|
Application #:
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13619588
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
|
01/10/2013
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Title:
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SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13621242
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Filing Dt:
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09/15/2012
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Publication #:
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Pub Dt:
|
09/26/2013
| | | | |
Title:
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METHOD FOR MAKING HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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13622614
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Filing Dt:
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09/19/2012
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Publication #:
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Pub Dt:
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03/20/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD WITH GREATER EPITAXIAL GROWTH ON 110 CRYSTAL PLANE
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Patent #:
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Issue Dt:
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10/08/2013
|
Application #:
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13622712
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Filing Dt:
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09/19/2012
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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LOW SERIES RESISTANCE TRANSISTOR STRUCTURE ON SILICON ON INSULATOR LAYER
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Patent #:
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Issue Dt:
|
09/16/2014
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Application #:
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13622755
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Filing Dt:
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09/19/2012
|
Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
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|
Patent #:
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|
Issue Dt:
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03/24/2015
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Application #:
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13623129
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Filing Dt:
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09/20/2012
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
Title:
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MULTIGATE FINFETS WITH EPITAXIALLY-GROWN MERGED SOURCE/DRAINS
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Patent #:
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Issue Dt:
|
12/23/2014
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Application #:
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13623132
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Filing Dt:
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09/20/2012
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Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
Title:
|
Electronic Fuse Vias in Interconnect Structures
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13623198
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Filing Dt:
|
09/20/2012
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING BACK GATING, IMPROVED ISOLATION AND REDUCED WELL RESISTANCE AND METHOD TO FABRICATE SAME
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Patent #:
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Issue Dt:
|
10/22/2013
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Application #:
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13623230
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Filing Dt:
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09/20/2012
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Title:
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AUTOMATION OF INTERCONNECT AND ROUTING CUSTOMIZATION
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Patent #:
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Issue Dt:
|
07/14/2015
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Application #:
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13623276
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Filing Dt:
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09/20/2012
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Publication #:
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|
Pub Dt:
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03/20/2014
| | | | |
Title:
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METHOD AND STRUCTURE FOR FINFET WITH FINELY CONTROLLED DEVICE WIDTH
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|
Patent #:
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|
Issue Dt:
|
12/10/2013
|
Application #:
|
13623292
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Filing Dt:
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09/20/2012
|
Title:
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RAISED TRENCH METAL SEMICONDUCTOR ALLOY FORMATION
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|
Patent #:
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|
Issue Dt:
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12/16/2014
|
Application #:
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13623314
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Filing Dt:
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09/20/2012
|
Publication #:
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|
Pub Dt:
|
03/20/2014
| | | | |
Title:
|
MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13623866
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Filing Dt:
|
09/20/2012
|
Publication #:
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|
Pub Dt:
|
03/20/2014
| | | | |
Title:
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AMORPHOUS SILICON PHOTODETECTOR WITH LOW DARK CURRENT
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|
Patent #:
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Issue Dt:
|
06/16/2015
|
Application #:
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13623873
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Filing Dt:
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09/20/2012
|
Publication #:
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Pub Dt:
|
03/20/2014
| | | | |
Title:
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A COMPOSITE WIRING BOARD WITH ELECTRICAL THROUGH CONNECTIONS
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|
Patent #:
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|
Issue Dt:
|
12/17/2013
|
Application #:
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13624251
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Filing Dt:
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09/21/2012
|
Publication #:
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|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME
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|
Patent #:
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|
Issue Dt:
|
04/07/2015
|
Application #:
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13624307
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Filing Dt:
|
09/21/2012
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Publication #:
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Pub Dt:
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06/13/2013
| | | | |
Title:
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MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME USING HARD MASK RESISTANT TO STRUCTURE RELEASE ETCH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13624466
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Filing Dt:
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09/21/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
|
METHODS FOR HARDENING AMORPHOUS DIELECTRIC FILMS IN A MAGNETIC HEAD AND OTHER STRUCTURES
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Patent #:
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|
Issue Dt:
|
06/16/2015
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Application #:
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13625286
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) DEEP TRENCH CAPACITOR
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Patent #:
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|
Issue Dt:
|
03/31/2015
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Application #:
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13625294
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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01/24/2013
| | | | |
Title:
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SILICIDE MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME
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Patent #:
|
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Issue Dt:
|
11/25/2014
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Application #:
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13625440
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
|
LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR RADIATION DOSIMETER
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Patent #:
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Issue Dt:
|
07/29/2014
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Application #:
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13625486
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Filing Dt:
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09/24/2012
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Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
|
ZINC OXIDE-CONTAINING TRANSPARENT CONDUCTIVE ELECTRODE
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Patent #:
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Issue Dt:
|
07/29/2014
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Application #:
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13626025
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
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03/27/2014
| | | | |
Title:
|
THROUGH SILICON VIA WAFER, CONTACTS AND DESIGN STRUCTURES
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Patent #:
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|
Issue Dt:
|
01/06/2015
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Application #:
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13626032
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Filing Dt:
|
09/25/2012
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Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
|
OVERCOMING CHIP WARPING TO ENHANCE WETTING OF SOLDER BUMPS AND FLIP CHIP ATTACHES IN A FLIP CHIP PACKAGE
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|
Patent #:
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|
Issue Dt:
|
04/12/2016
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Application #:
|
13626040
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
|
ON-GOING RELIABILITY MONITORING OF INTEGRATED CIRCUIT CHIPS IN THE FIELD
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|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
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Application #:
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13626242
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Filing Dt:
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09/25/2012
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13626418
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Filing Dt:
|
09/25/2012
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Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
|
TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13627179
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Filing Dt:
|
09/26/2012
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Publication #:
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|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY
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|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13628169
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Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
01/24/2013
| | | | |
Title:
|
RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13628225
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Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13628251
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Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
13628561
|
Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
01/24/2013
| | | | |
Title:
|
FINFET SPACER FORMATION BY ORIENTED IMPLANTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13628715
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Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
FERROELECTRIC RANDOM ACCESS MEMORY WITH OPTIMIZED HARDMASK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13628726
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Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
STACKED NANOWIRE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13629193
|
Filing Dt:
|
09/27/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
HIGH ASPECT RATIO SAMPLE HOLDER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13629910
|
Filing Dt:
|
09/28/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND SI NANOPHOTONICS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13630339
|
Filing Dt:
|
09/28/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
SYSTEM AND METHOD FOR DETERMINING LINE EDGE ROUGHNESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13630404
|
Filing Dt:
|
09/28/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
13632237
|
Filing Dt:
|
10/01/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY
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|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13632705
|
Filing Dt:
|
10/01/2012
|
Publication #:
|
|
Pub Dt:
|
01/23/2014
| | | | |
Title:
|
PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY
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|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13633347
|
Filing Dt:
|
10/02/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13633911
|
Filing Dt:
|
10/03/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS
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|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13633973
|
Filing Dt:
|
10/03/2012
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
TRANSISTOR FORMATION USING COLD WELDING
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|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13644234
|
Filing Dt:
|
10/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
Techniques for Thermal Modeling of Data Centers to Improve Energy Efficiency
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13644398
|
Filing Dt:
|
10/04/2012
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
Multi-Gate Field Effect Transistor with A Tapered Gate Profile
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13644531
|
Filing Dt:
|
10/04/2012
|
Title:
|
IDENTIFYING LOGIC BLOCKS IN A SYNTHESIZED LOGIC DESIGN THAT HAVE SPECIFIED INPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13644683
|
Filing Dt:
|
10/04/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
SIMULTANEOUS PHOTORESIST DEVELOPMENT AND NEUTRAL POLYMER LAYER FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13644742
|
Filing Dt:
|
10/04/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13644918
|
Filing Dt:
|
10/04/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS
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|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13645869
|
Filing Dt:
|
10/05/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
THERMALLY ADAPTIVE IN-SYSTEM ALLOCATION
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13645926
|
Filing Dt:
|
10/05/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation
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|
|
Patent #:
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|
Issue Dt:
|
08/18/2015
|
Application #:
|
13646120
|
Filing Dt:
|
10/05/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation
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|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13647538
|
Filing Dt:
|
10/09/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
METHODS FOR NORMALIZING STRAIN IN SEMICONDCUTOR DEVICES AND STRAIN NORMALIZED SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13647547
|
Filing Dt:
|
10/09/2012
|
Publication #:
|
|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
METHOD FOR RADIATION MONITORING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13647862
|
Filing Dt:
|
10/09/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
COMPRESSIVELY STRAINED SOI SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13648292
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
CHIP AUTHENTICATION USING MULTI-DOMAIN INTRINSIC IDENTIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13648321
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/10/2014
| | | | |
Title:
|
SINGLE FIN CUT EMPLOYING ANGLED PROCESSING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13648555
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13648799
|
Filing Dt:
|
10/10/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
SELF CALIBRATED, BROADBAND, TUNABLE, ACTIVE OSCILLATOR WITH UNITY GAIN CELLS FOR MULTI-STANDARD AND/OR MULTIBAND CHANNEL SELECTION
|
|