skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036797/0356   Pages: 92
Recorded: 10/06/2015
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.
Total properties: 340
Page 1 of 4
Pages: 1 2 3 4
1
Patent #:
5895503
Issue Dt:
04/20/1999
Application #:
08458479
Filing Dt:
06/02/1995
Title:
ADDRESS TRANSLATION METHOD AND MECHANISM USING PHYSICAL ADDRESS INFORMATION INCLUDING DURING A SEGMENTATION PROCESS
2
Patent #:
6031992
Issue Dt:
02/29/2000
Application #:
08678541
Filing Dt:
07/05/1996
Title:
COMBINING HARDWARE AND SOFTWARE TO PROVIDE AN IMPROVED MICROPROCESSOR
3
Patent #:
5958061
Issue Dt:
09/28/1999
Application #:
08685721
Filing Dt:
07/24/1996
Title:
HOST MICROPROCESSOR WITH APPARATUS FOR TEMPORARILY HOLDING TARGET PROCESSOR STATE
4
Patent #:
5832205
Issue Dt:
11/03/1998
Application #:
08700302
Filing Dt:
08/20/1996
Title:
A MEMORY CONTROLLER FOR A MICROPROCESSOR FOR DETECTING A FAILURE OF SPECULATION ON THE PHYSICAL NATURE OF A COMPONENT BEING ADDRESSED
5
Patent #:
6199152
Issue Dt:
03/06/2001
Application #:
08702771
Filing Dt:
08/22/1996
Title:
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
6
Patent #:
5926832
Issue Dt:
07/20/1999
Application #:
08721698
Filing Dt:
09/26/1996
Title:
NETHOD AND APPARATUS FOR ALIASING MEMORY DATA IN AN ADVANCED MICROPROCESSOR
7
Patent #:
6011908
Issue Dt:
01/04/2000
Application #:
08772686
Filing Dt:
12/23/1996
Title:
A GATED STORE BUFFER FOR AN ADVANCED MICROPROCESSOR
8
Patent #:
5905855
Issue Dt:
05/18/1999
Application #:
08807542
Filing Dt:
02/28/1997
Title:
METHOD AND APPARATUS FOR CORRECTING ERRORS IN COMPUTER SYSTEMS
9
Patent #:
6226733
Issue Dt:
05/01/2001
Application #:
08905356
Filing Dt:
08/04/1997
Title:
Address translation mechanism and method in a computer system
10
Patent #:
7089404
Issue Dt:
08/08/2006
Application #:
09332338
Filing Dt:
06/14/1999
Title:
METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR
11
Patent #:
6172925
Issue Dt:
01/09/2001
Application #:
09333178
Filing Dt:
06/14/1999
Title:
MEMORY ARRAY BITLINE TIMING CIRCUIT
12
Patent #:
7761857
Issue Dt:
07/20/2010
Application #:
09417332
Filing Dt:
10/13/1999
Title:
METHOD FOR SWITCHING BETWEEN INTERPRETATION AND DYNAMIC TRANSLATION IN A PROCESSOR SYSTEM BASED UPON CODE SEQUENCE EXECUTION COUNTS
13
Patent #:
6363336
Issue Dt:
03/26/2002
Application #:
09417356
Filing Dt:
10/13/1999
Title:
FINE GRAIN TRANSLATION DISCRIMINATION
14
Patent #:
6714904
Issue Dt:
03/30/2004
Application #:
09417358
Filing Dt:
10/13/1999
Title:
SYSTEM FOR USING RATE OF EXCEPTION EVENT GENERATION DURING EXECUTION OF TRANSLATED INSTRUCTIONS TO CONTROL OPTIMIZATION OF THE TRANSLATED INSTRUCTIONS
15
Patent #:
6880152
Issue Dt:
04/12/2005
Application #:
09417979
Filing Dt:
10/13/1999
Title:
METHOD OF OPTIMIZING COMPILER VS INTERPRETER MODE OPERATION IN A CODE TRANSLATOR BASED UPON AMOUNT OF TIME SPENT IN EACH MODE
16
Patent #:
6990658
Issue Dt:
01/24/2006
Application #:
09417980
Filing Dt:
10/13/1999
Title:
METHOD FOR TRANSLATING INSTRUCTIONS IN A SPECULATIVE MICROPROCESSOR FEATURING COMMITTING STATE
17
Patent #:
6415379
Issue Dt:
07/02/2002
Application #:
09417981
Filing Dt:
10/13/1999
Title:
METHOD AND APPARATUS FOR MAINTAINING CONTEXT WHILE EXECUTING TRANSLATED INSTRUCTIONS
18
Patent #:
6728865
Issue Dt:
04/27/2004
Application #:
09420748
Filing Dt:
10/20/1999
Title:
PIPELINE REPLAY SUPPORT FOR UNALIGNED MEMORY OPERATIONS
19
Patent #:
6748589
Issue Dt:
06/08/2004
Application #:
09421484
Filing Dt:
10/20/1999
Title:
METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION
20
Patent #:
6429491
Issue Dt:
08/06/2002
Application #:
09421614
Filing Dt:
10/20/1999
Publication #:
US20020070408
Pub Dt:
06/13/2002
Title:
ELECTROSTATIC DISCHARGE PROTECTION FOR MOSFETS
21
Patent #:
6738892
Issue Dt:
05/18/2004
Application #:
09421615
Filing Dt:
10/20/1999
Title:
USE OF ENABLE BITS TO CONTROL EXECUTION OF SELECTED INSTRUCTIONS
22
Patent #:
6604188
Issue Dt:
08/05/2003
Application #:
09421972
Filing Dt:
10/20/1999
Title:
PIPELINE REPLAY SUPPORT FOR MULTI-CYCLE OPERATIONS WHEREIN ALL VLIW INSTRUCTIONS ARE FLUSHED UPON DETECTION OF A MULTI-CYCLE ATOM OPERATION IN A VLIW INSTRUCTION
23
Patent #:
6754892
Issue Dt:
06/22/2004
Application #:
09464638
Filing Dt:
12/15/1999
Title:
INSTRUCTION PACKING FOR AN ADVANCED MICROPROCESSOR
24
Patent #:
6513110
Issue Dt:
01/28/2003
Application #:
09464644
Filing Dt:
12/15/1999
Title:
CHECK INSTRUCTION AND METHOD
25
Patent #:
6668287
Issue Dt:
12/23/2003
Application #:
09464661
Filing Dt:
12/15/1999
Title:
SOFTWARE DIRECT MEMORY ACCESS
26
Patent #:
6845353
Issue Dt:
01/18/2005
Application #:
09471447
Filing Dt:
12/23/1999
Title:
INTERPAGE PROLOGUE TO PROTECT VIRTUAL ADDRESS MAPPINGS
27
Patent #:
7100061
Issue Dt:
08/29/2006
Application #:
09484516
Filing Dt:
01/18/2000
Publication #:
US20020116650
Pub Dt:
08/22/2002
Title:
ADAPTIVE POWER CONTROL
28
Patent #:
6594821
Issue Dt:
07/15/2003
Application #:
09539987
Filing Dt:
03/30/2000
Title:
TRANSLATION CONSISTENCY CHECKING FOR MODIFIED TARGET INSTRUCTIONS BY COMPARING TO ORIGINAL COPY
29
Patent #:
6738893
Issue Dt:
05/18/2004
Application #:
09557650
Filing Dt:
04/25/2000
Title:
METHOD AND APPARATUS FOR SCHEDULING TO REDUCE SPACE AND INCREASE SPEED OF MICROPROCESSOR OPERATIONS
30
Patent #:
6571316
Issue Dt:
05/27/2003
Application #:
09595077
Filing Dt:
06/16/2000
Title:
CACHE MEMORY ARRAY FOR MULTIPLE ADDRESS SPACES
31
Patent #:
6968469
Issue Dt:
11/22/2005
Application #:
09595198
Filing Dt:
06/16/2000
Title:
SYSTEM AND METHOD FOR PRESERVING INTERNAL PROCESSOR CONTEXT WHEN THE PROCESSOR IS POWERED DOWN AND RESTORING THE INTERNAL PROCESSOR CONTEXT WHEN PROCESSOR IS RESTORED
32
Patent #:
6725361
Issue Dt:
04/20/2004
Application #:
09595199
Filing Dt:
06/16/2000
Title:
METHOD AND APPARATUS FOR EMULATING A FLOATING POINT STACK IN A TRANSLATION PROCESS
33
Patent #:
6615300
Issue Dt:
09/02/2003
Application #:
09596279
Filing Dt:
06/19/2000
Title:
FAST LOOK-UP OF INDIRECT BRANCH DESTINATION IN A DYNAMIC TRANSLATION SYSTEM
34
Patent #:
6640297
Issue Dt:
10/28/2003
Application #:
09596280
Filing Dt:
06/19/2000
Title:
LINK PIPE SYSTEM FOR STORAGE AND RETRIEVAL OF SEQUENCES OF BRANCH ADDRESSES
35
Patent #:
6826682
Issue Dt:
11/30/2004
Application #:
09603743
Filing Dt:
06/26/2000
Title:
FLOATING POINT EXCEPTION HANDLING IN PIPELINED PROCESSOR USING SPECIAL INSTRUCTION TO DETECT GENERATED EXCEPTION AND EXECUTE INSTRUCTIONS SINGLY FROM KNOWN CORRECT STATE
36
Patent #:
7260731
Issue Dt:
08/21/2007
Application #:
09694433
Filing Dt:
10/23/2000
Title:
SAVING POWER WHEN IN OR TRANSITIONING TO A STATIC MODE OF A PROCESSOR
37
Patent #:
7840776
Issue Dt:
11/23/2010
Application #:
09699947
Filing Dt:
10/30/2000
Title:
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
38
Patent #:
6820216
Issue Dt:
11/16/2004
Application #:
09822929
Filing Dt:
03/30/2001
Publication #:
US20020144179
Pub Dt:
10/03/2002
Title:
METHOD AND APPARATUS FOR ACCELERATING FAULT HANDLING
39
Patent #:
6829719
Issue Dt:
12/07/2004
Application #:
09822933
Filing Dt:
03/30/2001
Publication #:
US20020144184
Pub Dt:
10/03/2002
Title:
METHOD AND APPARATUS FOR HANDLING NESTED FAULTS
40
Patent #:
6851040
Issue Dt:
02/01/2005
Application #:
09930625
Filing Dt:
08/15/2001
Publication #:
US20030037220
Pub Dt:
02/20/2003
Title:
METHOD AND APPARATUS FOR IMPROVING SEGMENTED MEMORY ADDRESSING
41
Patent #:
6882172
Issue Dt:
04/19/2005
Application #:
10124152
Filing Dt:
04/16/2002
Title:
SYSTEM AND METHOD FOR MEASURING TRANSISTOR LEAKAGE CURRENT WITH A RING OSCILLATOR
42
Patent #:
7472033
Issue Dt:
12/30/2008
Application #:
10273681
Filing Dt:
10/17/2002
Title:
APPARATUS FOR CONTROLLING SEMICONDUCTOR CHIP CHARACTERISTICS
43
Patent #:
6940314
Issue Dt:
09/06/2005
Application #:
10334264
Filing Dt:
12/31/2002
Title:
DYNAMIC NODE KEEPER SYSTEM AND METHOD
44
Patent #:
6936898
Issue Dt:
08/30/2005
Application #:
10334272
Filing Dt:
12/31/2002
Publication #:
US20040124475
Pub Dt:
07/01/2004
Title:
DIAGONAL DEEP WELL REGION FOR ROUTING BODY-BIAS VOLTAGE FOR MOSFETS IN SURFACE WELL REGIONS
45
Patent #:
7334198
Issue Dt:
02/19/2008
Application #:
10334638
Filing Dt:
12/31/2002
Publication #:
US20040128631
Pub Dt:
07/01/2004
Title:
SOFTWARE CONTROLLED TRANSISTOR BODY BIAS
46
Patent #:
7228242
Issue Dt:
06/05/2007
Application #:
10334748
Filing Dt:
12/31/2002
Publication #:
US20040128090
Pub Dt:
07/01/2004
Title:
ADAPTIVE POWER CONTROL BASED ON PRE PACKAGE CHARACTERIZATION OF INTEGRATED CIRCUITS
47
Patent #:
7941675
Issue Dt:
05/10/2011
Application #:
10334918
Filing Dt:
12/31/2002
Publication #:
US20040128566
Pub Dt:
07/01/2004
Title:
ADAPTIVE POWER CONTROL
48
Patent #:
7953990
Issue Dt:
05/31/2011
Application #:
10334919
Filing Dt:
12/31/2002
Publication #:
US20040128567
Pub Dt:
07/01/2004
Title:
ADAPTIVE POWER CONTROL BASED ON POST PACKAGE CHARACTERIZATION OF INTEGRATED CIRCUITS
49
Patent #:
7444471
Issue Dt:
10/28/2008
Application #:
10335405
Filing Dt:
12/30/2002
Title:
METHOD AND SYSTEM FOR USING EXTERNAL STORAGE TO AMORTIZE CPU CYCLE UTILIZATION
50
Patent #:
7203932
Issue Dt:
04/10/2007
Application #:
10335459
Filing Dt:
12/30/2002
Title:
METHOD AND SYSTEM FOR USING IDIOM RECOGNITION DURING A SOFTWARE TRANSLATION PROCESS
51
Patent #:
7310723
Issue Dt:
12/18/2007
Application #:
10406022
Filing Dt:
04/02/2003
Title:
METHODS AND SYSTEMS EMPLOYING A FLAG FOR DEFERRING EXCEPTION HANDLING TO A COMMIT OR ROLLBACK POINT
52
Patent #:
7636815
Issue Dt:
12/22/2009
Application #:
10411168
Filing Dt:
04/09/2003
Title:
SYSTEM AND METHOD FOR HANDLING DIRECT MEMORY ACCESSES
53
Patent #:
7118273
Issue Dt:
10/10/2006
Application #:
10411955
Filing Dt:
04/10/2003
Title:
SYSTEM FOR ON-CHIP TEMPERATURE MEASUREMENT IN INTEGRATED CIRCUITS
54
Patent #:
7716452
Issue Dt:
05/11/2010
Application #:
10438158
Filing Dt:
05/13/2003
Title:
TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR
55
Patent #:
6930534
Issue Dt:
08/16/2005
Application #:
10439659
Filing Dt:
05/16/2003
Title:
TEMPERATURE COMPENSATED INTEGRATED CIRCUITS
56
Patent #:
6831494
Issue Dt:
12/14/2004
Application #:
10439665
Filing Dt:
05/16/2003
Title:
VOLTAGE COMPENSATED INTEGRATED CIRCUITS
57
Patent #:
7134001
Issue Dt:
11/07/2006
Application #:
10463223
Filing Dt:
06/16/2003
Title:
PIPELINE REPLAY SUPPORT FOR UNALIGNED MEMORY OPERATIONS
58
Patent #:
7111096
Issue Dt:
09/19/2006
Application #:
10463233
Filing Dt:
06/17/2003
Title:
FAST LOOK-UP OF INDIRECT BRANCH DESTINATION IN A DYNAMIC TRANSLATION SYSTEM
59
Patent #:
7685403
Issue Dt:
03/23/2010
Application #:
10463820
Filing Dt:
06/16/2003
Title:
PIPELINE REPLAY SUPPORT FOR MULTI-CYCLE OPERATIONS
60
Patent #:
7096460
Issue Dt:
08/22/2006
Application #:
10463846
Filing Dt:
06/16/2003
Title:
SWITCHING TO ORIGINAL MODIFIABLE INSTRUCTION COPY COMPARISON CHECK TO VALIDATE PRIOR TRANSLATION WHEN TRANSLATED SUB-AREA PROTECTION EXCEPTION SLOWS DOWN OPERATION
61
Patent #:
7337439
Issue Dt:
02/26/2008
Application #:
10464871
Filing Dt:
06/18/2003
Title:
METHOD FOR INCREASING THE SPEED OF SPECULATIVE EXECUTION
62
Patent #:
7249246
Issue Dt:
07/24/2007
Application #:
10600989
Filing Dt:
06/20/2003
Title:
METHODS AND SYSTEMS FOR MAINTAINING INFORMATION FOR LOCATING NON-NATIVE PROCESSOR INSTRUCTIONS WHEN EXECUTING NATIVE PROCESSOR INSTRUCTIONS
63
Patent #:
7039792
Issue Dt:
05/02/2006
Application #:
10607480
Filing Dt:
06/25/2003
Title:
METHOD AND SYSTEM FOR IMPLEMENTING A FLOATING POINT COMPARE USING RECORDED FLAGS
64
Patent #:
7111146
Issue Dt:
09/19/2006
Application #:
10607934
Filing Dt:
06/27/2003
Title:
METHOD AND SYSTEM FOR PROVIDING HARDWARE SUPPORT FOR MEMORY PROTECTION AND VIRTUAL MEMORY ADDRESS TRANSLATION FOR A VIRTUAL MACHINE
65
Patent #:
7694301
Issue Dt:
04/06/2010
Application #:
10609158
Filing Dt:
06/27/2003
Title:
METHOD AND SYSTEM FOR SUPPORTING INPUT/OUTPUT FOR A VIRTUAL MACHINE
66
Patent #:
7089397
Issue Dt:
08/08/2006
Application #:
10613801
Filing Dt:
07/03/2003
Title:
METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES
67
Patent #:
7451300
Issue Dt:
11/11/2008
Application #:
10620862
Filing Dt:
07/15/2003
Title:
EXPLICIT CONTROL OF SPECULATION
68
Patent #:
7225299
Issue Dt:
05/29/2007
Application #:
10622028
Filing Dt:
07/16/2003
Title:
SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHE
69
Patent #:
7062631
Issue Dt:
06/13/2006
Application #:
10623021
Filing Dt:
07/17/2003
Title:
METHOD AND SYSTEM FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES
70
Patent #:
7606997
Issue Dt:
10/20/2009
Application #:
10623101
Filing Dt:
07/18/2003
Title:
METHOD AND SYSTEM FOR USING ONE OR MORE ADDRESS BITS AND AN INSTRUCTION TO INCREASE AN INSTRUCTION SET
71
Patent #:
7149872
Issue Dt:
12/12/2006
Application #:
10629031
Filing Dt:
07/28/2003
Publication #:
US20050010739
Pub Dt:
01/13/2005
Title:
SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE
72
Patent #:
7149851
Issue Dt:
12/12/2006
Application #:
10646461
Filing Dt:
08/21/2003
Title:
METHOD AND SYSTEM FOR CONSERVATIVELY MANAGING STORE CAPACITY AVAILABLE TO A PROCESSOR ISSUING STORES
73
Patent #:
7698539
Issue Dt:
04/13/2010
Application #:
10672790
Filing Dt:
09/26/2003
Title:
SYSTEM AND METHOD OF INSTRUCTION MODIFICATION
74
Patent #:
6885210
Issue Dt:
04/26/2005
Application #:
10672793
Filing Dt:
09/26/2003
Title:
SYSTEM AND METHOD FOR MEASURING TRANSISTOR LEAKAGE CURRENT WITH A RING OSCILLATOR WITH BACKBIAS CONTROLS
75
Patent #:
7681046
Issue Dt:
03/16/2010
Application #:
10672796
Filing Dt:
09/26/2003
Title:
SYSTEM WITH SECURE CRYPTOGRAPHIC CAPABILITIES USING A HARDWARE SPECIFIC DIGITAL SECRET
76
Patent #:
7098512
Issue Dt:
08/29/2006
Application #:
10683732
Filing Dt:
10/10/2003
Title:
LAYOUT PATTERNS FOR DEEP WELL REGION TO FACILITATE ROUTING BODY-BIAS VOLTAGE
77
Patent #:
8350616
Issue Dt:
01/08/2013
Application #:
10712522
Filing Dt:
11/12/2003
Title:
VARIABLE OUTPUT CHARGE PUMP CIRCUIT
78
Patent #:
7642835
Issue Dt:
01/05/2010
Application #:
10712523
Filing Dt:
11/12/2003
Title:
SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS
79
Patent #:
6903564
Issue Dt:
06/07/2005
Application #:
10712847
Filing Dt:
11/12/2003
Title:
DEVICE AGING DETERMINATION CIRCUIT
80
Patent #:
7646835
Issue Dt:
01/12/2010
Application #:
10716320
Filing Dt:
11/17/2003
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE
81
Patent #:
7694151
Issue Dt:
04/06/2010
Application #:
10719879
Filing Dt:
11/20/2003
Title:
ARCHITECTURE, SYSTEM, AND METHOD FOR OPERATING ON ENCRYPTED AND /OR HIDDEN INFORMATION
82
Patent #:
7129771
Issue Dt:
10/31/2006
Application #:
10747015
Filing Dt:
12/23/2003
Title:
SERVO LOOP FOR WELL BIAS VOLTAGE SOURCE
83
Patent #:
7649402
Issue Dt:
01/19/2010
Application #:
10747016
Filing Dt:
12/23/2003
Title:
FEEDBACK-CONTROLLED BODY-BIAS VOLTAGE SOURCE
84
Patent #:
7012461
Issue Dt:
03/14/2006
Application #:
10747022
Filing Dt:
12/23/2003
Title:
STABILIZATION COMPONENT FOR A SUBSTRATE POTENTIAL REGULATION CIRCUIT
85
Patent #:
7332763
Issue Dt:
02/19/2008
Application #:
10765316
Filing Dt:
01/26/2004
Title:
SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE
86
Patent #:
6943614
Issue Dt:
09/13/2005
Application #:
10769140
Filing Dt:
01/29/2004
Title:
FRACTIONAL BIASING OF SEMICONDUCTORS
87
Patent #:
7205758
Issue Dt:
04/17/2007
Application #:
10771015
Filing Dt:
02/02/2004
Title:
SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE
88
Patent #:
7645673
Issue Dt:
01/12/2010
Application #:
10772029
Filing Dt:
02/03/2004
Title:
METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN
89
Patent #:
8209517
Issue Dt:
06/26/2012
Application #:
10783473
Filing Dt:
02/20/2004
Title:
METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR
90
Patent #:
7248988
Issue Dt:
07/24/2007
Application #:
10791099
Filing Dt:
03/01/2004
Publication #:
US20050192773
Pub Dt:
09/01/2005
Title:
SYSTEM AND METHOD FOR REDUCING TEMPERATURE VARIATION DURING BURN IN
91
Patent #:
6897671
Issue Dt:
05/24/2005
Application #:
10791241
Filing Dt:
03/01/2004
Title:
SYSTEM AND METHOD FOR REDUCING HEAT DISSIPATION DURING BURN-IN
92
Patent #:
6900650
Issue Dt:
05/31/2005
Application #:
10791459
Filing Dt:
03/01/2004
Title:
SYSTEM AND METHOD FOR CONTROLLING TEMPERATURE DURING BURN-IN
93
Patent #:
7759740
Issue Dt:
07/20/2010
Application #:
10808225
Filing Dt:
03/23/2004
Title:
DEEP WELL REGIONS FOR ROUTING BODY-BIAS VOLTAGE TO MOSFETS IN SURFACE WELL REGIONS HAVING SEPARATION WELLS OF P-TYPE BETWEEN THE SEGMENTED DEEP N WELLS.
94
Patent #:
7975108
Issue Dt:
07/05/2011
Application #:
10810196
Filing Dt:
03/25/2004
Title:
REQUEST TRACKING DATA PREFETCHER APPARATUS
95
Patent #:
7388260
Issue Dt:
06/17/2008
Application #:
10816269
Filing Dt:
03/31/2004
Title:
STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE
96
Patent #:
7330959
Issue Dt:
02/12/2008
Application #:
10830921
Filing Dt:
04/23/2004
Title:
USE OF MTRR AND PAGE ATTRIBUTE TABLE TO SUPPORT MULTIPLE BYTE ORDER FORMATS IN A COMPUTER SYSTEM
97
Patent #:
7336103
Issue Dt:
02/26/2008
Application #:
10864271
Filing Dt:
06/08/2004
Title:
STACKED INVERTER DELAY CHAIN
98
Patent #:
7329928
Issue Dt:
02/12/2008
Application #:
10866494
Filing Dt:
06/10/2004
Title:
VOLTAGE COMPENSATED INTEGRATED CIRCUITS
99
Patent #:
7071747
Issue Dt:
07/04/2006
Application #:
10869012
Filing Dt:
06/15/2004
Title:
INVERTING ZIPPER REPEATER CIRCUIT
100
Patent #:
7212022
Issue Dt:
05/01/2007
Application #:
10870751
Filing Dt:
06/16/2004
Publication #:
US20050212547
Pub Dt:
09/29/2005
Title:
SYSTEM AND METHOD FOR MEASURING TIME DEPENDENT DIELECTRIC BREAKDOWN WITH A RING OSCILLATOR
Assignor
1
INTELLECTUAL VENTURES FUNDING LLC
Exec Dt:
08/27/2015
Assignee
1
INTELLECTUAL VENTURES HOLDING 81 LLC
7251 W. LAKE MEAD BLVD
STE 300
LAS VEGAS, NEVADA 89128
Correspondence name and address
MURABITO, HAO & BARNES LLP
TWO NORTH MARKET STREET
THIRD FLOOR
SAN JOSE, CA 95113

Search Results as of: 05/20/2024 11:23 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT