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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038378/0343   Pages: 9
Recorded: 04/07/2016
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 79
1
Patent #:
6940169
Issue Dt:
09/06/2005
Application #:
10791095
Filing Dt:
03/01/2004
Publication #:
US20040178503
Pub Dt:
09/16/2004
Title:
TORCH BUMP
2
Patent #:
7994636
Issue Dt:
08/09/2011
Application #:
10849947
Filing Dt:
05/20/2004
Publication #:
US20040212101
Pub Dt:
10/28/2004
Title:
FLIP CHIP INTERCONNECTION STRUCTURE
3
Patent #:
7033859
Issue Dt:
04/25/2006
Application #:
10850093
Filing Dt:
05/20/2004
Publication #:
US20040212098
Pub Dt:
10/28/2004
Title:
FLIP CHIP INTERCONNECTION STRUCTURE
4
Patent #:
7242091
Issue Dt:
07/10/2007
Application #:
10906697
Filing Dt:
03/02/2005
Publication #:
US20060197205
Pub Dt:
09/07/2006
Title:
STACKED SEMICONDUCTOR PACKAGES AND METHOD THEREFOR
5
Patent #:
7238258
Issue Dt:
07/03/2007
Application #:
10907991
Filing Dt:
04/22/2005
Publication #:
US20060237142
Pub Dt:
10/26/2006
Title:
SYSTEM FOR PEELING SEMICONDUCTOR CHIPS FROM TAPE
6
Patent #:
7148086
Issue Dt:
12/12/2006
Application #:
10908120
Filing Dt:
04/28/2005
Publication #:
US20060246629
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING AND FABRICATION METHOD THEREFOR
7
Patent #:
7221175
Issue Dt:
05/22/2007
Application #:
10908433
Filing Dt:
05/11/2005
Publication #:
US20060255820
Pub Dt:
11/16/2006
Title:
SELF-ALIGNING DOCKING SYSTEM FOR ELECTRONIC DEVICE TESTING
8
Patent #:
6943057
Issue Dt:
09/13/2005
Application #:
10931654
Filing Dt:
08/31/2004
Title:
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
9
Patent #:
7064430
Issue Dt:
06/20/2006
Application #:
10931919
Filing Dt:
08/31/2004
Publication #:
US20060043559
Pub Dt:
03/02/2006
Title:
STACKED DIE PACKAGING AND FABRICATION METHOD
10
Patent #:
6969640
Issue Dt:
11/29/2005
Application #:
10934129
Filing Dt:
09/02/2004
Title:
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE SYSTEM
11
Patent #:
7169641
Issue Dt:
01/30/2007
Application #:
11121847
Filing Dt:
05/03/2005
Publication #:
US20060252177
Pub Dt:
11/09/2006
Title:
SEMICONDUCTOR PACKAGE WITH SELECTIVE UNDERFILL AND FABRICATION METHOD THERFOR
12
Patent #:
7211901
Issue Dt:
05/01/2007
Application #:
11145246
Filing Dt:
06/03/2005
Publication #:
US20050218515
Pub Dt:
10/06/2005
Title:
SELF-COPLANARITY BUMPING SHAPE FOR FLIP CHIP
13
Patent #:
7407877
Issue Dt:
08/05/2008
Application #:
11145247
Filing Dt:
06/03/2005
Publication #:
US20050221535
Pub Dt:
10/06/2005
Title:
Self-coplanarity bumping shape for flip chip
14
Patent #:
7271496
Issue Dt:
09/18/2007
Application #:
11162637
Filing Dt:
09/16/2005
Publication #:
US20060189033
Pub Dt:
08/24/2006
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
15
Patent #:
7274089
Issue Dt:
09/25/2007
Application #:
11162682
Filing Dt:
09/19/2005
Publication #:
US20070063320
Pub Dt:
03/22/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE RESTRAINT
16
Patent #:
7279785
Issue Dt:
10/09/2007
Application #:
11164160
Filing Dt:
11/12/2005
Publication #:
US20060180914
Pub Dt:
08/17/2006
Title:
STACKED DIE PACKAGE SYSTEM
17
Patent #:
7141886
Issue Dt:
11/28/2006
Application #:
11215090
Filing Dt:
08/29/2005
Publication #:
US20060043564
Pub Dt:
03/02/2006
Title:
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE
18
Patent #:
7279786
Issue Dt:
10/09/2007
Application #:
11257894
Filing Dt:
10/24/2005
Publication #:
US20060175696
Pub Dt:
08/10/2006
Title:
NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
19
Patent #:
7288835
Issue Dt:
10/30/2007
Application #:
11276941
Filing Dt:
03/17/2006
Publication #:
US20070216005
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
20
Patent #:
7250685
Issue Dt:
07/31/2007
Application #:
11307384
Filing Dt:
02/04/2006
Publication #:
US20070108565
Pub Dt:
05/17/2007
Title:
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
21
Patent #:
7372170
Issue Dt:
05/13/2008
Application #:
11372755
Filing Dt:
03/10/2006
Publication #:
US20060170093
Pub Dt:
08/03/2006
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
22
Patent #:
7605480
Issue Dt:
10/20/2009
Application #:
11372989
Filing Dt:
03/10/2006
Publication #:
US20060163715
Pub Dt:
07/27/2006
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
23
Patent #:
7420263
Issue Dt:
09/02/2008
Application #:
11374377
Filing Dt:
03/13/2006
Publication #:
US20060189101
Pub Dt:
08/24/2006
Title:
DBG SYSTEM AND METHOD WITH ADHESIVE LAYER SEVERING
24
Patent #:
7678611
Issue Dt:
03/16/2010
Application #:
11464631
Filing Dt:
08/15/2006
Publication #:
US20060292831
Pub Dt:
12/28/2006
Title:
SPACER DIE STRUCTURE AND METHOD FOR ATTACHING
25
Patent #:
7700407
Issue Dt:
04/20/2010
Application #:
12062293
Filing Dt:
04/03/2008
Publication #:
US20080213941
Pub Dt:
09/04/2008
Title:
A METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
26
Patent #:
7691681
Issue Dt:
04/06/2010
Application #:
12191542
Filing Dt:
08/14/2008
Publication #:
US20080299705
Pub Dt:
12/04/2008
Title:
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
27
Patent #:
7736930
Issue Dt:
06/15/2010
Application #:
12353489
Filing Dt:
01/14/2009
Publication #:
US20090162965
Pub Dt:
06/25/2009
Title:
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
28
Patent #:
8278144
Issue Dt:
10/02/2012
Application #:
12362627
Filing Dt:
01/30/2009
Publication #:
US20090184419
Pub Dt:
07/23/2009
Title:
FLIP CHIP INTERCONNECT SOLDER MASK
29
Patent #:
7960815
Issue Dt:
06/14/2011
Application #:
12398806
Filing Dt:
03/05/2009
Publication #:
US20090166821
Pub Dt:
07/02/2009
Title:
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
30
Patent #:
8129837
Issue Dt:
03/06/2012
Application #:
12432137
Filing Dt:
04/29/2009
Publication #:
US20090206493
Pub Dt:
08/20/2009
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
31
Patent #:
8119450
Issue Dt:
02/21/2012
Application #:
12472083
Filing Dt:
05/26/2009
Publication #:
US20090227072
Pub Dt:
09/10/2009
Title:
INTERCONNECTING A CHIP AND A SUBSTRATE BY BONDING PURE METAL BUMPS AND PURE METAL SPOTS
32
Patent #:
7901983
Issue Dt:
03/08/2011
Application #:
12472236
Filing Dt:
05/26/2009
Publication #:
US20090230552
Pub Dt:
09/17/2009
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
33
Patent #:
7843042
Issue Dt:
11/30/2010
Application #:
12493108
Filing Dt:
06/26/2009
Publication #:
US20090261460
Pub Dt:
10/22/2009
Title:
WAFER LEVEL INTEGRATION PACKAGE
34
Patent #:
7960841
Issue Dt:
06/14/2011
Application #:
12496046
Filing Dt:
07/01/2009
Publication #:
US20090267236
Pub Dt:
10/29/2009
Title:
THROUGH-HOLE VIA ON SAW STREETS
35
Patent #:
8017501
Issue Dt:
09/13/2011
Application #:
12533160
Filing Dt:
07/31/2009
Publication #:
US20090291526
Pub Dt:
11/26/2009
Title:
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
36
Patent #:
8021923
Issue Dt:
09/20/2011
Application #:
12533270
Filing Dt:
07/31/2009
Publication #:
US20090291527
Pub Dt:
11/26/2009
Title:
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
37
Patent #:
8017521
Issue Dt:
09/13/2011
Application #:
12533344
Filing Dt:
07/31/2009
Publication #:
US20090291528
Pub Dt:
11/26/2009
Title:
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
38
Patent #:
7875495
Issue Dt:
01/25/2011
Application #:
12571234
Filing Dt:
09/30/2009
Publication #:
US20100022050
Pub Dt:
01/28/2010
Title:
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
39
Patent #:
8564382
Issue Dt:
10/22/2013
Application #:
12579286
Filing Dt:
10/14/2009
Publication #:
US20100039185
Pub Dt:
02/18/2010
Title:
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
40
Patent #:
8803630
Issue Dt:
08/12/2014
Application #:
12579299
Filing Dt:
10/14/2009
Publication #:
US20100033289
Pub Dt:
02/11/2010
Title:
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
41
Patent #:
8228154
Issue Dt:
07/24/2012
Application #:
12579307
Filing Dt:
10/14/2009
Publication #:
US20100033290
Pub Dt:
02/11/2010
Title:
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
42
Patent #:
8823466
Issue Dt:
09/02/2014
Application #:
12606351
Filing Dt:
10/27/2009
Publication #:
US20100045398
Pub Dt:
02/25/2010
Title:
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
43
Patent #:
8129841
Issue Dt:
03/06/2012
Application #:
12624482
Filing Dt:
11/24/2009
Publication #:
US20100065966
Pub Dt:
03/18/2010
Title:
SOLDER JOINT FLIP CHIP INTERCONNECTION
44
Patent #:
7958628
Issue Dt:
06/14/2011
Application #:
12635536
Filing Dt:
12/10/2009
Publication #:
US20100083494
Pub Dt:
04/08/2010
Title:
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
45
Patent #:
8216930
Issue Dt:
07/10/2012
Application #:
12643180
Filing Dt:
12/21/2009
Publication #:
US20100099222
Pub Dt:
04/22/2010
Title:
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
46
Patent #:
7968445
Issue Dt:
06/28/2011
Application #:
12651758
Filing Dt:
01/04/2010
Publication #:
US20100105200
Pub Dt:
04/29/2010
Title:
SEMICONDUCTOR PACKAGE WITH PASSIVATION ISLAND FOR REDUCING STRESS ON SOLDER BUMPS
47
Patent #:
8304904
Issue Dt:
11/06/2012
Application #:
12700114
Filing Dt:
02/04/2010
Publication #:
US20100133687
Pub Dt:
06/03/2010
Title:
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
48
Patent #:
8097496
Issue Dt:
01/17/2012
Application #:
12703450
Filing Dt:
02/10/2010
Publication #:
US20100144100
Pub Dt:
06/10/2010
Title:
METHOD OF FORMING QUAD FLAT PACKAGE
49
Patent #:
8716853
Issue Dt:
05/06/2014
Application #:
12704345
Filing Dt:
02/11/2010
Publication #:
US20100140799
Pub Dt:
06/10/2010
Title:
Extended Redistribution Layers Bumped Wafer
50
Patent #:
8310058
Issue Dt:
11/13/2012
Application #:
12704366
Filing Dt:
02/11/2010
Publication #:
US20100140737
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING PASSIVE CIRCUIT ELEMENTS WITH THROUGH SILICON VIAS TO BACKSIDE INTERCONNECT STRUCTURES
51
Patent #:
8111112
Issue Dt:
02/07/2012
Application #:
12705790
Filing Dt:
02/15/2010
Publication #:
US20100140738
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPACT COILS FOR HIGH PERFORMANCE FILTER
52
Patent #:
8111113
Issue Dt:
02/07/2012
Application #:
12705810
Filing Dt:
02/15/2010
Publication #:
US20100140742
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THIN FILM CAPACITOR
53
Patent #:
7973406
Issue Dt:
07/05/2011
Application #:
12716455
Filing Dt:
03/03/2010
Publication #:
US20100164100
Pub Dt:
07/01/2010
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
54
Patent #:
8318537
Issue Dt:
11/27/2012
Application #:
12757889
Filing Dt:
04/09/2010
Publication #:
US20120211880
Pub Dt:
08/23/2012
Title:
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
55
Patent #:
8120183
Issue Dt:
02/21/2012
Application #:
12763386
Filing Dt:
04/20/2010
Publication #:
US20100200951
Pub Dt:
08/12/2010
Title:
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
56
Patent #:
8030769
Issue Dt:
10/04/2011
Application #:
12763390
Filing Dt:
04/20/2010
Publication #:
US20100200986
Pub Dt:
08/12/2010
Title:
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
57
Patent #:
8062929
Issue Dt:
11/22/2011
Application #:
12788785
Filing Dt:
05/27/2010
Publication #:
US20100233852
Pub Dt:
09/16/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SAME SIZE SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIA FORMED AROUND PERIPHERY OF THE DIE
58
Patent #:
8502339
Issue Dt:
08/06/2013
Application #:
12813315
Filing Dt:
06/10/2010
Publication #:
US20100244193
Pub Dt:
09/30/2010
Title:
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
59
Patent #:
8309452
Issue Dt:
11/13/2012
Application #:
12826365
Filing Dt:
06/29/2010
Publication #:
US20100264516
Pub Dt:
10/21/2010
Title:
METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
60
Patent #:
8592252
Issue Dt:
11/26/2013
Application #:
12858593
Filing Dt:
08/18/2010
Publication #:
US20100308467
Pub Dt:
12/09/2010
Title:
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
61
Patent #:
8399991
Issue Dt:
03/19/2013
Application #:
12858602
Filing Dt:
08/18/2010
Publication #:
US20100308459
Pub Dt:
12/09/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
62
Patent #:
8252666
Issue Dt:
08/28/2012
Application #:
12858615
Filing Dt:
08/18/2010
Publication #:
US20100311206
Pub Dt:
12/09/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
63
Patent #:
8247268
Issue Dt:
08/21/2012
Application #:
12896430
Filing Dt:
10/01/2010
Publication #:
US20110111591
Pub Dt:
05/12/2011
Title:
SEMICONDUCTOR WAFER HAVING THROUGH-HOLE VIAS ON SAW STREETS WITH BACKSIDE REDISTRIBUTION LAYER
64
Patent #:
8097943
Issue Dt:
01/17/2012
Application #:
12905797
Filing Dt:
10/15/2010
Publication #:
US20110024903
Pub Dt:
02/03/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING
65
Patent #:
8704366
Issue Dt:
04/22/2014
Application #:
12911592
Filing Dt:
10/25/2010
Publication #:
US20110037172
Pub Dt:
02/17/2011
Title:
Ultra Thin Bumped Wafer With Under-Film
66
Patent #:
8329554
Issue Dt:
12/11/2012
Application #:
12916758
Filing Dt:
11/01/2010
Publication #:
US20110045637
Pub Dt:
02/24/2011
Title:
ULTRA THIN BUMPED WAFER WITH UNDER-FILM
67
Patent #:
8994196
Issue Dt:
03/31/2015
Application #:
13005666
Filing Dt:
01/13/2011
Publication #:
US20110101546
Pub Dt:
05/05/2011
Title:
System and Method for Directional Grinding on Backside of a Semiconductor Wafer
68
Patent #:
8815643
Issue Dt:
08/26/2014
Application #:
13021856
Filing Dt:
02/07/2011
Publication #:
US20120244661
Pub Dt:
09/27/2012
Title:
METHOD OF FABRICATING SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
69
Patent #:
8188598
Issue Dt:
05/29/2012
Application #:
13088647
Filing Dt:
04/18/2011
Publication #:
US20110215468
Pub Dt:
09/08/2011
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
70
Patent #:
8697490
Issue Dt:
04/15/2014
Application #:
13175694
Filing Dt:
07/01/2011
Publication #:
US20110260321
Pub Dt:
10/27/2011
Title:
FLIP CHIP INTERCONNECTION STRUCTURE
71
Patent #:
8921983
Issue Dt:
12/30/2014
Application #:
13235413
Filing Dt:
09/18/2011
Publication #:
US20120001326
Pub Dt:
01/05/2012
Title:
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
72
Patent #:
8304339
Issue Dt:
11/06/2012
Application #:
13237828
Filing Dt:
09/20/2011
Publication #:
US20120009783
Pub Dt:
01/12/2012
Title:
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
73
Patent #:
8759972
Issue Dt:
06/24/2014
Application #:
13306768
Filing Dt:
11/29/2011
Publication #:
US20130277827
Pub Dt:
10/24/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
74
Patent #:
8399990
Issue Dt:
03/19/2013
Application #:
13355354
Filing Dt:
01/20/2012
Publication #:
US20120119329
Pub Dt:
05/17/2012
Title:
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
75
Patent #:
8810029
Issue Dt:
08/19/2014
Application #:
13367214
Filing Dt:
02/06/2012
Publication #:
US20120133043
Pub Dt:
05/31/2012
Title:
SOLDER JOINT FLIP CHIP INTERCONNECTION
76
Patent #:
8941235
Issue Dt:
01/27/2015
Application #:
13423262
Filing Dt:
03/18/2012
Publication #:
US20120175769
Pub Dt:
07/12/2012
Title:
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
77
Patent #:
8558378
Issue Dt:
10/15/2013
Application #:
13464979
Filing Dt:
05/05/2012
Publication #:
US20120211887
Pub Dt:
08/23/2012
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
78
Patent #:
8592311
Issue Dt:
11/26/2013
Application #:
13615308
Filing Dt:
09/13/2012
Publication #:
US20130015554
Pub Dt:
01/17/2013
Title:
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
79
Patent #:
8703548
Issue Dt:
04/22/2014
Application #:
13765478
Filing Dt:
02/12/2013
Publication #:
US20130171800
Pub Dt:
07/04/2013
Title:
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
EDWARD J. MAYLE
1850 K STREET, N.W.
SUITE 1100
WASHINGTON, DC 20006

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