Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 042671/0448 | |
| Pages: | 5 |
| | Recorded: | 06/02/2017 | | |
| Attorney Dkt #: | 1026-RT-10 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09877530
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Filing Dt:
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06/08/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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METHOD AND SYSTEM FOR EXCLUSIVE TWO-LEVEL CACHING IN A CHIP-MULTIPROCESSOR
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09877793
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Filing Dt:
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06/08/2001
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Publication #:
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Pub Dt:
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04/18/2002
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Title:
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SCALABLE ARCHITECTURE BASED ON SINGLE-CHIP MULTIPROCESSING
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09878985
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Filing Dt:
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06/11/2001
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Publication #:
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Pub Dt:
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01/17/2002
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Title:
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SYSTEM AND METHOD FOR LIMITED FANOUT DAISY CHAINING OF CACHE INVALIDATION REQUESTS IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10042008
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Filing Dt:
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01/07/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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SYSTEM FOR HANDLING COHERENCE PROTOCOL RACES IN A SCALABLE SHARED MEMORY SYSTEM BASED ON CHIP MULTIPROCESSING
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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10672960
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Filing Dt:
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09/26/2003
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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SYSTEM AND METHOD FOR LIMITED FANOUT DAISY CHAINING OF CACHE INVALIDATION REQUESTS IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10693388
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Filing Dt:
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10/24/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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SCALABLE ARCHITECTURE BASED ON SINGLE-CHIP MULTIPROCESSING
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10698130
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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07/29/2004
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Title:
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MULTIPROCESSOR CACHE COHERENCE SYSTEM AND METHOD IN WHICH PROCESSOR NODES AND INPUT/OUTPUT NODES ARE EQUAL PARTICIPANTS
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10769824
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Filing Dt:
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02/02/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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METHOD AND SYSTEM FOR EXCLUSIVE TWO-LEVEL CACHING IN A CHIP-MULTIPROCESSOR
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Assignee
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| 2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI |
| GYEONGGI-DO, KOREA, REPUBLIC OF |
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Correspondence name and address
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IP&T GROUP LLP
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8230 LEESBURG PIKE SUITE 650
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VIENNA, VA 22182
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