Total properties:
107
Page
1
of
2
Pages:
1 2
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
08946810
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
UNIT FOR PROCESSING NUMERICAL AND LOGICAL OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA -FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08946812
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
METHOD OF THE SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08946998
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
RUN-TIME RECONFIGURATION METHOD FOR PROGRAMMABLE UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
08946999
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
METHOD FOR THE AUTOMATIC ADDRESS GENERATION OF MODULES WITHIN CLUSTERS COMPRISED OF A PLURALITY OF THESE MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
08947002
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA-FLOW PROCESSORS (DFPS) AND UNITS WITH TWO-OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS AND THE LIKE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08947254
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09145139
|
Filing Dt:
|
08/28/1998
|
|
Title:
|
INTERNAL BUS SYSTEM FOR DFPS AND UNITS WITH TWO-OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES, FOR MANAGING LARGE VOLUMES OF DATA WITH A HIGH INTERCONNECTION COMPLEXITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09329132
|
Filing Dt:
|
06/09/1999
|
|
Title:
|
RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09335974
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09369653
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
09494567
|
Filing Dt:
|
01/31/2000
|
|
Title:
|
RUN-TIME RECONFIGURATION METHOD FOR PROGRAMMABLE UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09537932
|
Filing Dt:
|
03/29/2000
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09613217
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO-OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS,DPGAS, AND THE LIKE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09623052
|
Filing Dt:
|
01/09/2001
|
|
Title:
|
METHOD FOR HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO-OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGS, ETC.)--
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09623113
|
Filing Dt:
|
01/09/2001
|
|
Title:
|
METHOD FOR DEADLOCK-FREE CONFIGURATION OF DATAFLOW PROCESSORS AND MODULES WITH A TWO-OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09915213
|
Filing Dt:
|
07/25/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/25/2002
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
09967497
|
Filing Dt:
|
09/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/06/2003
| | | | |
|
Title:
|
METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
09967847
|
Filing Dt:
|
09/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
METHOD FOR TRANSLATING PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
10009649
|
Filing Dt:
|
05/29/2002
|
|
Title:
|
METHOD FOR INTERLEAVING A PROGRAM OVER A PLURALITY OF CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
10156397
|
Filing Dt:
|
05/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
RECONFIGURABLE MULTIDIMENSIONAL ARRAY PROCESSOR ALLOWING RUNTIME RECONFIGURATION OF SELECTED INDIVIDUAL ARRAY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10191926
|
Filing Dt:
|
07/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO-OR
MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10265846
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10297959
|
Filing Dt:
|
06/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
PIPELINE CONFIGURATION UNIT PROTOCOLS AND COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10304252
|
Filing Dt:
|
11/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
L/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10373595
|
Filing Dt:
|
02/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10379403
|
Filing Dt:
|
03/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
10398546
|
Filing Dt:
|
01/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
LOGIC CELL ARRAY AND BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
10469909
|
Filing Dt:
|
09/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
10471061
|
Filing Dt:
|
10/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
10480003
|
Filing Dt:
|
06/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
METHOD FOR PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
10486771
|
Filing Dt:
|
09/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
10487687
|
Filing Dt:
|
08/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10490079
|
Filing Dt:
|
11/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
ROUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
10490081
|
Filing Dt:
|
11/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
DEVICE INCLUDING A FIELD HAVING FUNCTION CELLS AND INFORMATION PROVIDING CELLS CONTROLLED BY THE FUNCTION CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
10523763
|
Filing Dt:
|
11/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
METHOD AND DEVICE FOR PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
10523764
|
Filing Dt:
|
08/02/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DATA PROCESSING METHOD AND DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
10526595
|
Filing Dt:
|
01/09/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
|
Title:
|
RECONFIGURABLE SEQUENCER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
10570173
|
Filing Dt:
|
11/10/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
|
Title:
|
DATA PROCESSING DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
10757900
|
Filing Dt:
|
01/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10764159
|
Filing Dt:
|
01/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLOW PROCESSORS AND MODULES HAVING TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAS, DPGAS, ETC.)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
10791501
|
Filing Dt:
|
03/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10792168
|
Filing Dt:
|
03/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO-OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
11122500
|
Filing Dt:
|
05/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11246617
|
Filing Dt:
|
10/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
|
Title:
|
PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
11820780
|
Filing Dt:
|
06/19/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
|
Title:
|
PROCESSOR CHIP FOR RECONFIGURABLE DATA PROCESSING, FOR PROCESSING NUMERIC AND LOGIC OPERATIONS AND INCLUDING FUNCTION AND INTERCONNECTION CONTROL UNITS.
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11820943
|
Filing Dt:
|
06/20/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11890094
|
Filing Dt:
|
08/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
12008543
|
Filing Dt:
|
01/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
12082073
|
Filing Dt:
|
04/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
|
Title:
|
RECONFIGURABLE SEQUENCER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12087916
|
Filing Dt:
|
12/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWARE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12109280
|
Filing Dt:
|
04/24/2008
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
12247076
|
Filing Dt:
|
10/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
|
Title:
|
ROUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12257075
|
Filing Dt:
|
10/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
|
Title:
|
METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12258100
|
Filing Dt:
|
10/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
|
Title:
|
DATA PROCESSING DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
|
Application #:
|
12354590
|
Filing Dt:
|
01/15/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12368709
|
Filing Dt:
|
02/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
A CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE CELLS THAT INCLUDE MULTI-BIT-WIDE INPUTS AND OUTPUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
12371040
|
Filing Dt:
|
02/13/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
LOGIC CELL ARRAY AND BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
12389274
|
Filing Dt:
|
02/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
|
Title:
|
DATA PROCESSING DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
12495465
|
Filing Dt:
|
06/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
Data Processor Having Disabled Cores
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12541299
|
Filing Dt:
|
08/14/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
|
Title:
|
RECONFIGURABLE SEQUENCER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
12570943
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
|
Title:
|
DATA PROCESSING METHOD AND DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
12570984
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12571173
|
Filing Dt:
|
09/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
RECONFIGURABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12621860
|
Filing Dt:
|
11/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
|
Title:
|
METHOD AND DEVICE FOR PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12630139
|
Filing Dt:
|
12/03/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
12720898
|
Filing Dt:
|
03/10/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
|
Title:
|
CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12836364
|
Filing Dt:
|
07/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2011
| | | | |
|
Title:
|
MULTI-CORE PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
12840477
|
Filing Dt:
|
07/21/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2010
| | | | |
|
Title:
|
A PROCESSOR CHIP INCLUDING A PLURALITY OF CACHE ELEMENTS CONNECTED TO A PLURALITY OF PROCESSOR CORES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12840742
|
Filing Dt:
|
07/21/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2010
| | | | |
|
Title:
|
I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12909061
|
Filing Dt:
|
10/21/2010
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
12909150
|
Filing Dt:
|
10/21/2010
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
12909203
|
Filing Dt:
|
10/21/2010
|
|
Title:
|
METHOD OF SELF-SYNCHRONIZATION OF CONFIGURABLE ELEMENTS OF A PROGRAMMABLE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
12944068
|
Filing Dt:
|
11/11/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
|
Title:
|
PROCESSOR ARRANGEMENT ON A CHIP INCLUDING DATA PROCESSING, MEMORY, AND INTERFACE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13023796
|
Filing Dt:
|
02/09/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
|
Title:
|
RECONFIGURABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
13040769
|
Filing Dt:
|
03/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
|
Title:
|
RECONFIGURABLE SEQUENCER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13177820
|
Filing Dt:
|
07/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
|
Title:
|
METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13279561
|
Filing Dt:
|
10/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
|
Title:
|
METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13289296
|
Filing Dt:
|
11/04/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
|
Title:
|
LOGIC CELL ARRAY AND BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13491894
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
|
Title:
|
PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13626047
|
Filing Dt:
|
09/25/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/24/2013
| | | | |
|
Title:
|
RECONFIGURABLE SEQUENCER STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13653639
|
Filing Dt:
|
10/17/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
|
Title:
|
METHODS AND DEVICES FOR TREATING AND PROCESSING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13903470
|
Filing Dt:
|
05/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
|
Title:
|
LOGICAL CELL ARRAY AND BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
14219945
|
Filing Dt:
|
03/19/2014
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
14223793
|
Filing Dt:
|
03/24/2014
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
|
Title:
|
Method for processing data
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
14231358
|
Filing Dt:
|
03/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
|
Title:
|
CHIP INCLUDING MEMORY ELEMENT STORING HIGHER LEVEL MEMORY DATA ON A PAGE BY PAGE BASIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
14263185
|
Filing Dt:
|
04/28/2014
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
|
Title:
|
RECONFIGURABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2017
|
Application #:
|
14276449
|
Filing Dt:
|
05/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2015
| | | | |
|
Title:
|
CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
14302318
|
Filing Dt:
|
06/11/2014
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2014
| | | | |
|
Title:
|
Multi-core processor having disabled cores
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14318211
|
Filing Dt:
|
06/27/2014
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2014
| | | | |
|
Title:
|
Multi-processor bus and cache interconnection system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14458099
|
Filing Dt:
|
08/12/2014
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
|
Title:
|
Multi-processor with selectively interconnected memory units
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14465157
|
Filing Dt:
|
08/21/2014
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2015
| | | | |
|
Title:
|
Parallel Processing Array of Arithmetic Unit having a Barrier Instruction
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14500618
|
Filing Dt:
|
09/29/2014
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2015
| | | | |
|
Title:
|
Method of Processing Data with an Array of Data Processors According to Application ID
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14540782
|
Filing Dt:
|
11/13/2014
|
|
Publication #:
|
|
Pub Dt:
|
03/12/2015
| | | | |
|
Title:
|
Multiprocessor Having Segmented Cache Memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14543306
|
Filing Dt:
|
11/17/2014
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2015
| | | | |
|
Title:
|
Multiprocessor Having Associated RAM Units
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14572643
|
Filing Dt:
|
12/16/2014
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2015
| | | | |
|
Title:
|
Data Processing System Having Integrated Pipelined Array Data Processor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
14718516
|
Filing Dt:
|
05/21/2015
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
|
Title:
|
DATA PROCESSOR CHIP WITH FLEXIBLE BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
14728422
|
Filing Dt:
|
06/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
|
Title:
|
Methods and Systems for Transferring Data between a Processing Device and External Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14810905
|
Filing Dt:
|
07/28/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2015
| | | | |
|
Title:
|
STACKED-DIE MULTI-PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2020
|
Application #:
|
14923702
|
Filing Dt:
|
10/27/2015
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2016
| | | | |
|
Title:
|
Integrated data processing core and array data processor and method for processing algorithms
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2021
|
Application #:
|
15000763
|
Filing Dt:
|
01/19/2016
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
|
Title:
|
PROCESSOR HAVING A PROGRAMMABLE FUNCTION UNIT
|
|
