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Total properties:
62
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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09634209
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Filing Dt:
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08/09/2000
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Title:
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DEPTH OF FOCUS (DOF) FOR TRENCH-FIRST-VIA-LAST (TFVL) DAMASCENE PROCESSING WITH HARD MASK AND LOW VISCOSITY PHOTORESIST
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09663021
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Filing Dt:
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09/15/2000
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Title:
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SELF-ALIGNED SEMICONDUCTOR INTERCONNECT BARRIER AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
|
11/11/2003
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Application #:
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09714361
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Filing Dt:
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11/15/2000
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Title:
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METHOD AND SYSTEM FOR PROVIDING SOURCE/DRAIN-GATE SPATIAL OVERLAP ENGINEERING FOR LOW-POWER DEVICES
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Patent #:
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Issue Dt:
|
06/24/2003
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Application #:
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09781436
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Filing Dt:
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02/13/2001
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Title:
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SEMICONDUCTOR DEVICES UTILIZING DIFFERENTLY COMPOSED METAL-BASED IN-LAID GATE ELECTRODES
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
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09783619
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Filing Dt:
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02/15/2001
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Title:
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CU DAMASCENE INTERCONNECTIONS USING BARRIER/CAPPING LAYER
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Patent #:
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Issue Dt:
|
07/01/2003
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Application #:
|
09793993
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Filing Dt:
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02/28/2001
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Title:
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DUAL DAMASCENE INTEGRATION SCHEME FOR PREVENTING COPPER CONTAMINATION OF DIELECTRIC LAYER
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09812521
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Filing Dt:
|
03/20/2001
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Title:
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TRANSISTOR DEVICE HAVING AN ENHANCED WIDTH DIMENSION AND A METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
|
02/04/2003
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Application #:
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09824148
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Filing Dt:
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04/02/2001
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Title:
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METHOD AND APPARATUS FOR SHIELDING ELECTROMAGNETIC EMISSIONS FROM AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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09826185
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Filing Dt:
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04/05/2001
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Title:
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SELF-ALIGNED CONDUCTIVE PLUGS IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
07/13/2004
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Application #:
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09877906
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Filing Dt:
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06/09/2001
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Publication #:
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Pub Dt:
|
12/12/2002
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Title:
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MOSFET WITH SIGE SOURCE/DRAIN REGIONS AND EPITAXIAL GATE DIELECTRIC
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Patent #:
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Issue Dt:
|
02/04/2003
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Application #:
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09892750
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Filing Dt:
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06/28/2001
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Title:
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INTEGRATION OF ORGANIC FILL FOR DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09905479
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Filing Dt:
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07/13/2001
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Title:
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INTEGRATED CIRCUIT INTERCONNECT SHUNT LAYER
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
|
10016024
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Filing Dt:
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12/12/2001
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Title:
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INTEGRATED CIRCUIT WITH LOW SOLUBILITY METAL-CONDUCTOR INTERCONNECT CAP
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10053994
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Filing Dt:
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01/18/2002
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Title:
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SEMICONDUCTOR PACKAGING APPAATS FOR CONTROLLING DIE ATTACH FILLET HEIGHT TO REDUCE DIE SHEAR STRESS
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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10163930
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Filing Dt:
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06/06/2002
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Title:
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SEMICONDUCTOR DEVICE AND FABRICATION TECHNIQUE USING A HIGH-K LINER FOR SPACER ETCH STOP
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Patent #:
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Issue Dt:
|
12/02/2003
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Application #:
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10165510
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Filing Dt:
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06/06/2002
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Title:
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CONFORMAL BARRIER LINER IN AN INTEGRATED CIRCUIT INTERCONNECT
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Patent #:
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Issue Dt:
|
03/23/2004
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Application #:
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10177336
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Filing Dt:
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06/21/2002
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Title:
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METHOD FOR MANUFACTURING A SCRIBE SEAL STRUCTURE
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10236200
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Filing Dt:
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09/06/2002
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT."
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10282980
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Filing Dt:
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10/29/2002
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Publication #:
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Pub Dt:
|
10/02/2003
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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10284651
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Filing Dt:
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10/30/2002
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10349042
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Filing Dt:
|
01/23/2003
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Publication #:
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Pub Dt:
|
07/29/2004
| | | | |
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Title:
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STRAINED CHANNEL FINFET
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10422784
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Filing Dt:
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04/25/2003
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Title:
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DUAL DAMASCENE INTEGRATION SCHEME FOR PREVENTING COPPER CONTAMINATION OF DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10429780
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Filing Dt:
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05/06/2003
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Title:
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METHOD FOR FORMING MULTIPLE FINS IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
02/15/2005
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Application #:
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10459589
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Filing Dt:
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06/12/2003
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Title:
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FINFET GATE FORMATION USING REVERSE TRIM AND OXIDE POLISH
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10618273
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Filing Dt:
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07/11/2003
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Title:
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METHOD FOR FORMING A FIELD EFFECT TRANSISTOR HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10672103
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Filing Dt:
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09/26/2003
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Title:
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CONFORMAL BARRIER LINER IN AN INTEGRATED CIRCUIT INTERCONNECT
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Patent #:
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01/11/2005
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Application #:
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10672126
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Filing Dt:
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09/26/2003
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Title:
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METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT WITH LOW SOLUBILITY METAL-CONDUCTOR INTERCONNECT CAP
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Patent #:
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07/25/2006
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10727999
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12/03/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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FORMATION OF ABRUPT JUNCTIONS IN DEVICES BY USING SILICIDE GROWTH DOPANT SNOWPLOW EFFECT
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Patent #:
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02/28/2006
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10756023
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01/12/2004
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07/14/2005
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Title:
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LOW STRESS SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
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Patent #:
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04/25/2006
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10811866
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03/30/2004
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Title:
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Patent #:
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05/24/2005
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10833112
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04/28/2004
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10/07/2004
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Title:
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STRAINED CHANNEL FINFET
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05/23/2006
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10859286
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06/01/2004
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Title:
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LOW POWER PRE-SILICIDE PROCESS IN INTEGRATED CIRCUIT TECHNOLOGY
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Patent #:
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03/07/2006
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10887836
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07/12/2004
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Patent #:
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01/31/2006
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10899955
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07/27/2004
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Title:
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08/23/2005
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10915638
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08/09/2004
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01/13/2005
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SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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01/02/2007
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10934511
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09/07/2004
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11/20/2007
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11072142
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03/04/2005
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07/14/2005
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SEMICONDUCTOR DEVICE HAVING A RETROGRADE DOPANT PROFILE IN A CHANNEL REGION
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10/02/2007
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11119660
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05/02/2005
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11/02/2006
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07/08/2008
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11150635
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06/10/2005
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05/04/2006
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01/01/2008
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07/05/2005
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07/26/2011
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11186969
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07/22/2005
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04/08/2008
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11288673
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11/29/2005
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11/02/2006
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TECHNIQUE FOR FORMING A CONTACT INSULATION LAYER WITH ENHANCED STRESS TRANSFER EFFICIENCY
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07/13/2010
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03/16/2006
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12/11/2007
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11422811
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06/07/2006
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09/21/2006
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10/28/2008
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09/18/2006
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05/29/2008
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08/26/2008
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11538111
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10/03/2006
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08/02/2007
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06/03/2008
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11/14/2006
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10/04/2007
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05/19/2009
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11/21/2006
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05/22/2008
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08/03/2010
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12/06/2006
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11/01/2007
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04/27/2010
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12/15/2006
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06/19/2008
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10/09/2012
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12/16/2006
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06/19/2008
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06/29/2010
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09/04/2007
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02/05/2013
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06/04/2009
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08/09/2011
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07/21/2008
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01/21/2010
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02/01/2011
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07/28/2008
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01/28/2010
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06/21/2016
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08/27/2008
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01/08/2009
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08/09/2011
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10/10/2008
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04/15/2010
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03/05/2013
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05/21/2009
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12/31/2009
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02/22/2011
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12/22/2009
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04/22/2010
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10/18/2011
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06/23/2010
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10/07/2010
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Title:
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TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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13176614
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Filing Dt:
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07/05/2011
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Publication #:
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Pub Dt:
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10/27/2011
| | | | |
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Title:
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METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION
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|
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Patent #:
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|
Issue Dt:
|
08/26/2014
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Application #:
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13644387
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Filing Dt:
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10/04/2012
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Publication #:
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|
Pub Dt:
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05/23/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT WITH METAL AND SEMI-CONDUCTING GATE
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