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Total properties:
26
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09285232
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Filing Dt:
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04/01/1999
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Title:
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BIT LINE CROSS-OVER LAYOUT ARRANGEMENT
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09329975
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Filing Dt:
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06/10/1999
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Title:
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HIERARCHICAL DYNAMIC MEMORY ARRAY ARCHITECTURE USING READ AMPLIFIERS SEPARATE FROM BIT LINE SENSE AMPLIFIERS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09372320
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Filing Dt:
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08/11/1999
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Title:
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DYNAMIC MEMORY ARRAY HAVING WRITE DATA APPLIED TO SELECTED BIT LINE SENSE AMPLIFIERS BEFORE SENSING TO WRITE ASSOCIATED SELECTED MEMORY CELLS
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09433245
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Filing Dt:
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11/03/1999
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Title:
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FLASH MEMORY ARCHITECTURE AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09451042
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Filing Dt:
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11/30/1999
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Title:
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EQUILIBRATION CIRCUIT AND METHOD USING A PULSED EQUILIBRATE SIGNAL AND A LEVEL EQUILIBRATE SIGNAL
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09474351
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Filing Dt:
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12/29/1999
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Title:
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PROGRAMMABLE AND ELECTRICALLY CONFIGURABLE LATCH TIMING CIRCUIT
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09499265
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Filing Dt:
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02/07/2000
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Title:
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Word line straps using two differentlayers of metal
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09502983
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Filing Dt:
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02/11/2000
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Title:
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Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09503048
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Filing Dt:
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02/12/2000
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Title:
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Merging write cycles by comparing at least a portion of the respective write cycle addresses
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09503049
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Filing Dt:
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02/12/2000
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Title:
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Intializing memory cells within a dynamic memory array prior to performing internal memory operations
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09503050
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Filing Dt:
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02/12/2000
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Title:
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Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09503108
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Filing Dt:
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02/11/2000
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Title:
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GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09503109
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Filing Dt:
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02/11/2000
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Title:
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Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09503982
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Filing Dt:
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02/14/2000
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Title:
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Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09668431
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Filing Dt:
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09/22/2000
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Title:
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AN INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09689219
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Filing Dt:
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10/11/2000
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Title:
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METHOD FOR REDUCING THE WIDTH OF A GLOBAL DATA BUS IN A MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09757088
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Filing Dt:
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01/08/2001
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Title:
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A STRUCTURE AND METHOD OF OPERATING AN ARRAY OF NON-VOLATILE MEMORY CELL WITH SOUCE-SIDE PROGRAMMING
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09938266
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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07/11/2002
| | | | |
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Title:
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NON-VOLATILE MEMORY ARCHITECTURE AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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09999563
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Filing Dt:
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11/15/2001
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Title:
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INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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10099291
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
|
07/11/2002
| | | | |
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Title:
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INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10100508
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
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Title:
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INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM USING A MEMORY CELL WITH SOURCE-SIDE PROGRAMMING
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Patent #:
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Issue Dt:
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12/29/2009
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Application #:
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11085770
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Filing Dt:
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03/21/2005
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Publication #:
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Pub Dt:
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07/28/2005
| | | | |
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Title:
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INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
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|
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Patent #:
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Issue Dt:
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04/03/2012
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Application #:
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12635543
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Filing Dt:
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12/10/2009
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Publication #:
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Pub Dt:
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04/15/2010
| | | | |
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Title:
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CONCURRENT MEMORY BANK ACCESS AND REFRESH RETIREMENT
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|
|
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Patent #:
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|
Issue Dt:
|
04/09/2013
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Application #:
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13436381
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Filing Dt:
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03/30/2012
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
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Title:
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CONCURRENT MEMORY BANK ACCESS AND REFRESH REQUEST QUEUING
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|
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Patent #:
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|
Issue Dt:
|
08/25/2015
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Application #:
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13857627
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Filing Dt:
|
04/05/2013
|
|
Publication #:
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Pub Dt:
|
08/29/2013
| | | | |
|
Title:
|
REFRESH REQUEST QUEUING CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
14830667
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Filing Dt:
|
08/19/2015
|
|
Publication #:
|
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Pub Dt:
|
06/23/2016
| | | | |
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Title:
|
REFRESH REQUEST QUEUING CIRCUITRY
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|
