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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054279/0001			Pages:	74
		Recorded:	11/02/2020
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 51

Patent #:	6959346	Issue Dt:	10/25/2005	Application #:	09741829	Filing Dt:	12/22/2000
Publication #:	US20020087708	Pub Dt:	07/04/2002
Title:	METHOD AND SYSTEM FOR PACKET ENCRYPTION

Patent #:	6522562	Issue Dt:	02/18/2003	Application #:	09894900	Filing Dt:	06/29/2001
Publication #:	US20020126519	Pub Dt:	09/12/2002
Title:	CONTENT ADDRESSABLE MEMORY CELL HAVING IMPROVED LAYOUT

Patent #:	6504775	Issue Dt:	01/07/2003	Application #:	09956917	Filing Dt:	09/21/2001
Publication #:	US20030016580	Pub Dt:	01/23/2003
Title:	BITLINE PRECHARGE

Patent #:	6967523	Issue Dt:	11/22/2005	Application #:	09966391	Filing Dt:	09/28/2001
Publication #:	US20020101744	Pub Dt:	08/01/2002
Title:	CASCADED CHARGE PUMP POWER SUPPLY

Patent #:	6538465	Issue Dt:	03/25/2003	Application #:	10084620	Filing Dt:	02/28/2002
Title:	DIGITALLY CONTROLLED PULSE WIDTH ADJUSTING CIRCUIT

Patent #:	6584003	Issue Dt:	06/24/2003	Application #:	10134753	Filing Dt:	04/30/2002
Title:	LOW POWER CONTENT ADDRESSABLE MEMORY ARCHITECTURE

Patent #:	7277426	Issue Dt:	10/02/2007	Application #:	10156725	Filing Dt:	05/24/2002
Publication #:	US20030218978	Pub Dt:	11/27/2003
Title:	METHOD AND APPARATUS FOR REORDERING ENTRIES IN A MULTI PROBE LOOKUP

Patent #:	7386705	Issue Dt:	06/10/2008	Application #:	10228933	Filing Dt:	08/27/2002
Publication #:	US20040044898	Pub Dt:	03/04/2004
Title:	Method for allocating processor resources and system for encrypting data

Patent #:	6990552	Issue Dt:	01/24/2006	Application #:	10286743	Filing Dt:	10/31/2002
Publication #:	US20040088476	Pub Dt:	05/06/2004
Title:	SORTING METHOD AND APPARATUS USING A CAM

Patent #:	6888731	Issue Dt:	05/03/2005	Application #:	10306734	Filing Dt:	11/29/2002
Publication #:	US20040105289	Pub Dt:	06/03/2004
Title:	METHOD AND APPARATUS FOR REPLACING DEFECTIVE ROWS IN A SEMICONDUCTOR MEMORY ARRAY

Patent #:	6717876	Issue Dt:	04/06/2004	Application #:	10329461	Filing Dt:	12/27/2002
Publication #:	US20030137890	Pub Dt:	07/24/2003
Title:	MATCHLINE SENSING FOR CONTENT ADDRESSABLE MEMORIES

Patent #:	7336752	Issue Dt:	02/26/2008	Application #:	10335535	Filing Dt:	12/31/2002
Publication #:	US20040125905	Pub Dt:	07/01/2004
Title:	WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Patent #:	6873532	Issue Dt:	03/29/2005	Application #:	10351593	Filing Dt:	01/27/2003
Publication #:	US20030161173	Pub Dt:	08/28/2003
Title:	CONTENT ADDRESSABLE MEMORY CELL HAVING IMPROVED LAYOUT

Patent #:	7010713	Issue Dt:	03/07/2006	Application #:	10352372	Filing Dt:	01/27/2003
Publication #:	US20040123175	Pub Dt:	06/24/2004
Title:	SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES

Patent #:	7062601	Issue Dt:	06/13/2006	Application #:	10430378	Filing Dt:	05/07/2003
Publication #:	US20040001380	Pub Dt:	01/01/2004
Title:	METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES

Patent #:	7477716	Issue Dt:	01/13/2009	Application #:	10647664	Filing Dt:	08/25/2003
Publication #:	US20040264621	Pub Dt:	12/30/2004
Title:	START UP CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	7188211	Issue Dt:	03/06/2007	Application #:	10724576	Filing Dt:	12/01/2003
Publication #:	US20050001744	Pub Dt:	01/06/2005
Title:	BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM

Patent #:	7120040	Issue Dt:	10/10/2006	Application #:	10856783	Filing Dt:	06/01/2004
Publication #:	US20050276086	Pub Dt:	12/15/2005
Title:	TERNARY CAM CELL FOR REDUCED MATCHLINE CAPACITANCE

Patent #:	7002824	Issue Dt:	02/21/2006	Application #:	10912768	Filing Dt:	08/05/2004
Publication #:	US20050068839	Pub Dt:	03/31/2005
Title:	CONTENT ADDRESSABLE MEMORY ARCHITECTURE

Patent #:	7038517	Issue Dt:	05/02/2006	Application #:	11037365	Filing Dt:	01/19/2005
Publication #:	US20050122144	Pub Dt:	06/09/2005
Title:	TIMING VERNIER USING A DELAY LOCKED LOOP

Patent #:	7631116	Issue Dt:	12/08/2009	Application #:	11257525	Filing Dt:	10/25/2005
Publication #:	US20060064510	Pub Dt:	03/23/2006
Title:	METHOD AND SYSTEM FOR PACKET ENCRYPTION

Patent #:	7124268	Issue Dt:	10/17/2006	Application #:	11263144	Filing Dt:	10/31/2005
Publication #:	US20060069858	Pub Dt:	03/30/2006
Title:	SORTING METHOD AND APPARATUS USING A CAM

Patent #:	7596710	Issue Dt:	09/29/2009	Application #:	11305433	Filing Dt:	12/14/2005
Publication #:	US20060103439	Pub Dt:	05/18/2006
Title:	SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES

Patent #:	7227766	Issue Dt:	06/05/2007	Application #:	11320746	Filing Dt:	12/30/2005
Publication #:	US20060104100	Pub Dt:	05/18/2006
Title:	MISMATCH-DEPENDENT POWER ALLOCATION TECHNIQUE FOR MATCH-LINE SENSING IN CONTENT-ADDRESSABLE MEMORIES

Patent #:	7484063	Issue Dt:	01/27/2009	Application #:	11582160	Filing Dt:	10/16/2006
Publication #:	US20070244893	Pub Dt:	10/18/2007
Title:	SORTING METHOD AND APPARATUS USING A CAM

Patent #:	7408391	Issue Dt:	08/05/2008	Application #:	11636876	Filing Dt:	12/11/2006
Publication #:	US20070080729	Pub Dt:	04/12/2007
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	7511980	Issue Dt:	03/31/2009	Application #:	11747428	Filing Dt:	05/11/2007
Publication #:	US20070206397	Pub Dt:	09/06/2007
Title:	LOW POWER MATCH-LINE SENSING CIRCUIT

Patent #:	7502245	Issue Dt:	03/10/2009	Application #:	11787667	Filing Dt:	04/17/2007
Publication #:	US20080025059	Pub Dt:	01/31/2008
Title:	CONTENT ADDRESSABLE MEMORY ARCHITECTURE

Patent #:	7830877	Issue Dt:	11/09/2010	Application #:	11839184	Filing Dt:	08/15/2007
Publication #:	US20080112401	Pub Dt:	05/15/2008
Title:	CONGESTION LEVEL MANAGEMENT IN A NETWORK DEVICE

Patent #:	7561454	Issue Dt:	07/14/2009	Application #:	11925208	Filing Dt:	10/26/2007
Publication #:	US20080049482	Pub Dt:	02/28/2008
Title:	COMPARE CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY CELL

Patent #:	8000430	Issue Dt:	08/16/2011	Application #:	11999162	Filing Dt:	12/04/2007
Publication #:	US20080089459	Pub Dt:	04/17/2008
Title:	WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Patent #:	7671650	Issue Dt:	03/02/2010	Application #:	12144186	Filing Dt:	06/23/2008
Publication #:	US20080252344	Pub Dt:	10/16/2008
Title:	TIMING VERNIER USING A DELAY LOCKED LOOP

Patent #:	7616035	Issue Dt:	11/10/2009	Application #:	12214053	Filing Dt:	06/16/2008
Publication #:	US20090201058	Pub Dt:	08/13/2009
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	7656988	Issue Dt:	02/02/2010	Application #:	12315289	Filing Dt:	12/02/2008
Publication #:	US20090086876	Pub Dt:	04/02/2009
Title:	START UP CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	7692461	Issue Dt:	04/06/2010	Application #:	12317877	Filing Dt:	12/30/2008
Publication #:	US20090121760	Pub Dt:	05/14/2009
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	8069363	Issue Dt:	11/29/2011	Application #:	12543839	Filing Dt:	08/19/2009
Publication #:	US20100033216	Pub Dt:	02/11/2010
Title:	DOUBLE DATA RATE OUTPUT LATCH FOR STATIC RAM DEVICE HAS EDGE-TRIGGERED FLIP-FLOP TO OUTPUT DDR SIGNAL TO SYNCHRONIZE WITH A SECOND CLOCK SIGNAL

Patent #:	8639912	Issue Dt:	01/28/2014	Application #:	12619355	Filing Dt:	11/16/2009
Publication #:	US20100064116	Pub Dt:	03/11/2010
Title:	METHOD AND SYSTEM FOR PACKET PROCESSING

Patent #:	8218707	Issue Dt:	07/10/2012	Application #:	12639531	Filing Dt:	12/16/2009
Publication #:	US20100109722	Pub Dt:	05/06/2010
Title:	INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	7863954	Issue Dt:	01/04/2011	Application #:	12687541	Filing Dt:	01/14/2010
Publication #:	US20100117698	Pub Dt:	05/13/2010
Title:	TIMING VERNIER USING A DELAY LOCKED LOOP

Patent #:	RE43552	Issue Dt:	07/24/2012	Application #:	12709198	Filing Dt:	02/19/2010
Title:	BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM

Patent #:	7893737	Issue Dt:	02/22/2011	Application #:	12714670	Filing Dt:	03/01/2010
Publication #:	US20100213994	Pub Dt:	08/26/2010
Title:	CHARGE PUMP FOR PLL/DLL

Patent #:	8296598	Issue Dt:	10/23/2012	Application #:	13113550	Filing Dt:	05/23/2011
Publication #:	US20110228626	Pub Dt:	09/22/2011
Title:	DOUBLE DATA RATE OUTPUT CIRCUIT AND METHOD

Patent #:	8213561	Issue Dt:	07/03/2012	Application #:	13186104	Filing Dt:	07/19/2011
Publication #:	US20110291721	Pub Dt:	12/01/2011
Title:	WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Patent #:	8718056	Issue Dt:	05/06/2014	Application #:	13437177	Filing Dt:	04/02/2012
Publication #:	US20120243411	Pub Dt:	09/27/2012
Title:	TRUNKING IN A MATRIX

Patent #:	8411812	Issue Dt:	04/02/2013	Application #:	13523406	Filing Dt:	06/14/2012
Publication #:	US20130003483	Pub Dt:	01/03/2013
Title:	WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Patent #:	8503598	Issue Dt:	08/06/2013	Application #:	13532980	Filing Dt:	06/26/2012
Publication #:	US20120306548	Pub Dt:	12/06/2012
Title:	INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	8533522	Issue Dt:	09/10/2013	Application #:	13624487	Filing Dt:	09/21/2012
Publication #:	US20130024717	Pub Dt:	01/24/2013
Title:	DOUBLE DATA RATE OUTPUT CIRCUIT

Patent #:	8855121	Issue Dt:	10/07/2014	Application #:	13795070	Filing Dt:	03/12/2013
Publication #:	US20130208596	Pub Dt:	08/15/2013
Title:	CONGESTION MANAGEMENT IN A NETWORK

Patent #:	8599984	Issue Dt:	12/03/2013	Application #:	13850500	Filing Dt:	03/26/2013
Publication #:	US20130271192	Pub Dt:	10/17/2013
Title:	WIDE FREQUENCY RANGE DELAY LOCKED LOOP

Patent #:	9325811	Issue Dt:	04/26/2016	Application #:	14148895	Filing Dt:	01/07/2014
Publication #:	US20140122582	Pub Dt:	05/01/2014
Title:	METHOD AND SYSTEM FOR PACKET PROCESSING

Patent #:	10122369	Issue Dt:	11/06/2018	Application #:	15479691	Filing Dt:	04/05/2017
Publication #:	US20170272085	Pub Dt:	09/21/2017
Title:	Wide Frequency Range Delay Locked Loop

Assignor

CPPIB CREDIT INVESTMENTS INC.

Exec Dt:

10/28/2020

Assignee

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

515 LEGGET DRIVE

SUITE 704

OTTAWA, CANADA K2K 3G4

Correspondence name and address
	CONVERSANT IP MANAGEMENT CORP
	5830 GRANITE PARKWAY #100-247
	SUITE 247
	PLANO, TX 75024

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