Total properties:
51
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11771241
|
Filing Dt:
|
06/29/2007
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11779587
|
Filing Dt:
|
07/18/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
STORAGE OF DATA IN MEMORY VIA PACKET STROBING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11779685
|
Filing Dt:
|
07/18/2007
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
11780231
|
Filing Dt:
|
07/19/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
11855496
|
Filing Dt:
|
09/14/2007
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11955754
|
Filing Dt:
|
12/13/2007
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
11978529
|
Filing Dt:
|
10/29/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
Data processing with time-based memory access
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12032249
|
Filing Dt:
|
02/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12042551
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
Title:
|
NONVOLATILE MEMORY HAVING NON-POWER OF TWO MEMORY CAPACITY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12181115
|
Filing Dt:
|
07/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12192215
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12337038
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12499577
|
Filing Dt:
|
07/08/2009
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
Title:
|
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12617459
|
Filing Dt:
|
11/12/2009
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12651707
|
Filing Dt:
|
01/04/2010
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
Title:
|
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12699627
|
Filing Dt:
|
02/03/2010
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
Title:
|
MEMORY WITH DATA CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12782047
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
MULTIPLE BIT PER CELL NON VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
12785099
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12812500
|
Filing Dt:
|
07/12/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
12832121
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12852082
|
Filing Dt:
|
08/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
13006005
|
Filing Dt:
|
01/13/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
13019100
|
Filing Dt:
|
02/01/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13046197
|
Filing Dt:
|
03/11/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13096874
|
Filing Dt:
|
04/28/2011
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
13114523
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13117715
|
Filing Dt:
|
05/27/2011
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
13117934
|
Filing Dt:
|
05/27/2011
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
13154891
|
Filing Dt:
|
06/07/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13250301
|
Filing Dt:
|
09/30/2011
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13305064
|
Filing Dt:
|
11/28/2011
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13481888
|
Filing Dt:
|
05/28/2012
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13595466
|
Filing Dt:
|
08/27/2012
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13599836
|
Filing Dt:
|
08/30/2012
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
Title:
|
Pre-Charge Voltage Generation and Power Saving Modes
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13649403
|
Filing Dt:
|
10/11/2012
|
Publication #:
|
|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13776757
|
Filing Dt:
|
02/26/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
SCALABLE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13871487
|
Filing Dt:
|
04/26/2013
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
14107735
|
Filing Dt:
|
12/16/2013
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
14158215
|
Filing Dt:
|
01/17/2014
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14216024
|
Filing Dt:
|
03/17/2014
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
Title:
|
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
14324265
|
Filing Dt:
|
07/07/2014
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
14491440
|
Filing Dt:
|
09/19/2014
|
Publication #:
|
|
Pub Dt:
|
01/08/2015
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14720317
|
Filing Dt:
|
05/22/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14828725
|
Filing Dt:
|
08/18/2015
|
Publication #:
|
|
Pub Dt:
|
02/04/2016
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY AND BOOSTED VOLTAGE PRODUCER THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14969351
|
Filing Dt:
|
12/15/2015
|
Publication #:
|
|
Pub Dt:
|
04/07/2016
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
15183162
|
Filing Dt:
|
06/15/2016
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15378650
|
Filing Dt:
|
12/14/2016
|
Publication #:
|
|
Pub Dt:
|
06/08/2017
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2018
|
Application #:
|
15401858
|
Filing Dt:
|
01/09/2017
|
Publication #:
|
|
Pub Dt:
|
04/27/2017
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2019
|
Application #:
|
15597603
|
Filing Dt:
|
05/17/2017
|
Publication #:
|
|
Pub Dt:
|
10/26/2017
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
|
Application #:
|
15655336
|
Filing Dt:
|
07/20/2017
|
Publication #:
|
|
Pub Dt:
|
11/09/2017
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2018
|
Application #:
|
15957120
|
Filing Dt:
|
04/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/01/2018
| | | | |
Title:
|
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
|
|