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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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13736512
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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PLANARIZATION OVER TOPOGRAPHY WITH MOLECULAR GLASS MATERIALS
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Patent #:
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Issue Dt:
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11/03/2015
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Application #:
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13736534
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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07/10/2014
| | | | |
Title:
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CRYSTALLINE THIN-FILM TRANSISTOR
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13736535
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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10/17/2013
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Title:
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HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13736672
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Filing Dt:
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01/08/2013
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Publication #:
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Pub Dt:
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07/10/2014
| | | | |
Title:
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PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13737002
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13737067
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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FINFET AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
|
01/06/2015
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Application #:
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13737089
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL
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Patent #:
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Issue Dt:
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09/09/2014
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Application #:
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13737099
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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DUAL MANDREL SIDEWALL IMAGE TRANSFER PROCESSES
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Patent #:
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Issue Dt:
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04/08/2014
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Application #:
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13737110
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Filing Dt:
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01/09/2013
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Title:
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MULTI-PROTOCOL DRIVER SLEW RATE CALIBRATION SYSTEM FOR CALIBRATING SLEW RATE CONTROL SIGNAL VALUES
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13737231
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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Automatic Generation of Wire Tag Lists for a Metal Stack
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13737611
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Filing Dt:
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01/09/2013
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Publication #:
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Pub Dt:
|
05/23/2013
| | | | |
Title:
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THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
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Patent #:
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Issue Dt:
|
09/30/2014
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Application #:
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13738139
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13738170
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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High-K and Metal Filled Trench-Type EDRAM Capacitor with Electrode Depth and Dimension Control
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13738270
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION
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Patent #:
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Issue Dt:
|
02/03/2015
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Application #:
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13738298
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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SELF-FORMED NANOMETER CHANNEL AT WAFER SCALE
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Patent #:
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Issue Dt:
|
10/14/2014
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Application #:
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13738367
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Filing Dt:
|
01/10/2013
|
Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
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ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
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Patent #:
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Issue Dt:
|
12/31/2013
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Application #:
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13738435
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Filing Dt:
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01/10/2013
|
Title:
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FIN REMOVAL METHOD
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13738532
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Filing Dt:
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01/10/2013
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Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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SILICON-ON-INSULATOR HEAT SINK
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13738541
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Filing Dt:
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01/10/2013
|
Publication #:
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Pub Dt:
|
07/10/2014
| | | | |
Title:
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BACKSIDE METAL GROUND PLANE WITH IMPROVED METAL ADHESION AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
|
06/10/2014
|
Application #:
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13739123
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Filing Dt:
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01/11/2013
|
Publication #:
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Pub Dt:
|
05/23/2013
| | | | |
Title:
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REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13739130
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Filing Dt:
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01/11/2013
|
Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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SEMICONDUCTOR DEVICE COMPRISING METALLIZATION LAYERS OF REDUCED INTERLAYER CAPACITANCE BY REDUCING THE AMOUNT OF ETCH STOP MATERIALS
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Patent #:
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Issue Dt:
|
02/18/2014
|
Application #:
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13739222
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Filing Dt:
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01/11/2013
|
Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
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SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13740343
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Filing Dt:
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01/14/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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SELECTIVE REMOVAL OF GATE STRUCTURE SIDEWALL(S) TO FACILITATE SIDEWALL SPACER PROTECTION
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Patent #:
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Issue Dt:
|
05/12/2015
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Application #:
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13740974
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Filing Dt:
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01/14/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SILICIDE CONTACTS
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Patent #:
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Issue Dt:
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08/25/2015
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Application #:
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13741416
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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BURIED WAVEGUIDE PHOTODETECTOR
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13741611
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13741638
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13741645
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY
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Patent #:
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Issue Dt:
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07/29/2014
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13741947
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13742465
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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13742490
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
|
08/15/2013
| | | | |
Title:
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PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13742508
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13742526
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
|
08/01/2013
| | | | |
Title:
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PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13742733
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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METHODS AND CIRCUITS FOR DISRUPTING INTEGRATED CIRCUIT FUNCTION
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13742916
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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SEALED AIR GAP FOR SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13743454
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13743642
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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DISASSEMBLABLE ELECTRONIC ASSEMBLY WITH LEAK-INHIBITING COOLANT CAPILLARIES
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13743810
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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DETERMINING OVERALL OPTIMAL YIELD POINT FOR A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13743886
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
Title:
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METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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13743935
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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06/06/2013
| | | | |
Title:
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METHOD AND APPARATUS FOR OPTICAL MODULATION
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Patent #:
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Issue Dt:
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09/27/2016
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Application #:
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13744551
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Filing Dt:
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01/18/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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02/18/2014
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Application #:
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13744606
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Filing Dt:
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01/18/2013
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Title:
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FIN DESIGN LEVEL MASK DECOMPOSITION FOR DIRECTED SELF ASSEMBLY
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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13744756
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Filing Dt:
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01/18/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13744761
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Filing Dt:
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01/18/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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MARCHAND BALUN STRUCTURE AND DESIGN METHOD
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13745221
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Filing Dt:
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01/18/2013
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Publication #:
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Pub Dt:
|
05/23/2013
| | | | |
Title:
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HIGH ENERGY DENSITY STORAGE MATERIAL DEVICE USING NANOCHANNEL STRUCTURE
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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13745547
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Filing Dt:
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01/18/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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FINFET INTEGRATED CIRCUITS WITH UNIFORM FIN HEIGHT AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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13745770
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Filing Dt:
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01/19/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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Wire-Last Integration Method and Structure for III-V Nanowire Devices
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Patent #:
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Issue Dt:
|
04/08/2014
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Application #:
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13745927
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Filing Dt:
|
01/21/2013
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Title:
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METHODS OF FORMING DIELECTRICALLY ISOLATED FINS FOR A FINFET SEMICONDUCTOR BY PERFORMING AN ETCHING PROCESS WHEREIN THE ETCH RATE IS MODIFIED VIA INCLUSION OF A DOPANT MATERIAL
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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13745929
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Filing Dt:
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01/21/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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TEST STRUCTURE AND METHOD TO FACILTIATE DEVELOPMENT/OPTIMIZATION OF PROCESS PARAMETERS
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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13745963
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Filing Dt:
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01/21/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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RACETRACK MEMORY CELLS WITH A VERTICAL NANOWIRE STORAGE ELEMENT
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13745965
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Filing Dt:
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01/21/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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LAND GRID ARRAY (LGA) SOCKET CARTRIDGE AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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02/23/2016
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Application #:
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13746359
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Filing Dt:
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01/22/2013
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Publication #:
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Pub Dt:
|
05/29/2014
| | | | |
Title:
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WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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13746463
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Filing Dt:
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01/22/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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CROSS COMMUNICATION OF COMMON PROBLEM DETERMINATION AND RESOLUTION
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13746508
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Filing Dt:
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01/22/2013
|
Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN
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Patent #:
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Issue Dt:
|
03/10/2015
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Application #:
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13746627
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Filing Dt:
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01/22/2013
|
Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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COMPOSITE COPPER WIRE INTERCONNECT STRUCTURES AND METHODS OF FORMING
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Patent #:
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Issue Dt:
|
03/22/2016
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Application #:
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13746699
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Filing Dt:
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01/22/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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METHOD AND APPARATUS FOR MEASURING ALPHA PARTICLE INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
01/13/2015
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Application #:
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13747529
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
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COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL WITH SENSE AMPLIFIER
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Patent #:
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Issue Dt:
|
01/26/2016
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Application #:
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13747579
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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07/24/2014
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Title:
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INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTIPLE EMBEDDED INTERCONNECT CONNECTION TO SAME THROUGH-SEMICONDUCTOR VIA
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Patent #:
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Issue Dt:
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03/15/2016
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Application #:
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13747798
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
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Patent #:
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Issue Dt:
|
06/23/2015
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Application #:
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13747842
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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12/19/2013
| | | | |
Title:
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BAD WORDLINE/ARRAY DETECTION IN MEMORY
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Patent #:
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Issue Dt:
|
09/16/2014
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Application #:
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13747907
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE
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Patent #:
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Issue Dt:
|
02/25/2014
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Application #:
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13748038
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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05/30/2013
| | | | |
Title:
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HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
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|
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Patent #:
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Issue Dt:
|
02/16/2016
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Application #:
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13748048
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
|
09/12/2017
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Application #:
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13748159
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH METAL LAYER CONNECTION TO THROUGH-SEMICONDUCTOR VIA
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Patent #:
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|
Issue Dt:
|
11/25/2014
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Application #:
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13748197
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Filing Dt:
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01/23/2013
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Publication #:
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Pub Dt:
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07/24/2014
| | | | |
Title:
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SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13748226
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Filing Dt:
|
01/23/2013
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
Title:
|
TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
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|
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Patent #:
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Issue Dt:
|
06/16/2015
|
Application #:
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13748662
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Filing Dt:
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01/24/2013
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
Title:
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STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
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|
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Patent #:
|
|
Issue Dt:
|
01/13/2015
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Application #:
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13748821
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Filing Dt:
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01/24/2013
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Publication #:
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Pub Dt:
|
07/24/2014
| | | | |
Title:
|
IN-SITU THERMOELECTRIC COOLING
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|
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Patent #:
|
|
Issue Dt:
|
09/16/2014
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Application #:
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13748942
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Filing Dt:
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01/24/2013
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
Title:
|
STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
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|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
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13749146
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Filing Dt:
|
01/24/2013
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Publication #:
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|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
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|
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Patent #:
|
|
Issue Dt:
|
01/12/2016
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Application #:
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13749330
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Filing Dt:
|
01/24/2013
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Publication #:
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|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING
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|
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Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13749744
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Filing Dt:
|
01/25/2013
|
Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
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|
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Patent #:
|
|
Issue Dt:
|
09/16/2014
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Application #:
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13749745
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Filing Dt:
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01/25/2013
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Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
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|
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Patent #:
|
|
Issue Dt:
|
08/09/2016
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Application #:
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13749830
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Filing Dt:
|
01/25/2013
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Publication #:
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|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
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13749851
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Filing Dt:
|
01/25/2013
|
Publication #:
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|
Pub Dt:
|
12/05/2013
| | | | |
Title:
|
POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL
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|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
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13749925
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Filing Dt:
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01/25/2013
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Publication #:
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Pub Dt:
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07/31/2014
| | | | |
Title:
|
POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPERATURE-BASED VOLTAGE CONTROL
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|
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Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13750497
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Filing Dt:
|
01/25/2013
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Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
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|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13750751
|
Filing Dt:
|
01/25/2013
|
Publication #:
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|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
INTERPOLATION TECHNIQUES USED FOR TIME ALIGNMENT OF MULTIPLE SIMULATION MODELS
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|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13751238
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
METHOD OF FORMING ELECTRONIC FUSE LINE WITH MODIFIED CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13751361
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Filing Dt:
|
01/28/2013
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Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS
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|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13751490
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Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
Nanowire Capacitor for Bidirectional Operation
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|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13751799
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Filing Dt:
|
01/28/2013
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13752567
|
Filing Dt:
|
01/29/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
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13752737
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Filing Dt:
|
01/29/2013
|
Publication #:
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|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS
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|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
13752948
|
Filing Dt:
|
01/29/2013
|
Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
EFFICIENT DATA EXTRACTION BY A REMOTE APPLICATION
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|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
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13753269
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Filing Dt:
|
01/29/2013
|
Publication #:
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|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
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Application #:
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13753989
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Filing Dt:
|
01/30/2013
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Publication #:
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Pub Dt:
|
07/31/2014
| | | | |
Title:
|
PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE
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|
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Patent #:
|
|
Issue Dt:
|
11/11/2014
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Application #:
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13754170
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Filing Dt:
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01/30/2013
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Publication #:
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Pub Dt:
|
07/31/2014
| | | | |
Title:
|
ACHIEVING GREATER PLANARITY BETWEEN UPPER SURFACES OF A LAYER AND A CONDUCTIVE STRUCTURE RESIDING THEREIN
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|
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Patent #:
|
|
Issue Dt:
|
04/07/2015
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Application #:
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13755030
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Filing Dt:
|
01/31/2013
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Publication #:
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|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
ELECTRONIC FUSE HAVING AN INSULATION LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13755192
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Filing Dt:
|
01/31/2013
|
Publication #:
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Pub Dt:
|
06/06/2013
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE
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|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13755246
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Filing Dt:
|
01/31/2013
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Publication #:
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Pub Dt:
|
07/31/2014
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS
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|
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Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13755374
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Filing Dt:
|
01/31/2013
|
Publication #:
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Pub Dt:
|
07/31/2014
| | | | |
Title:
|
AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS
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|
|
Patent #:
|
|
Issue Dt:
|
09/29/2015
|
Application #:
|
13755726
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Filing Dt:
|
01/31/2013
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION
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|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13755807
|
Filing Dt:
|
01/31/2013
|
Publication #:
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|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13756689
|
Filing Dt:
|
02/01/2013
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
DOUBLE-PATTERN GATE FORMATION PROCESSING WITH CRITICAL DIMENSION CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13756981
|
Filing Dt:
|
02/01/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13757040
|
Filing Dt:
|
02/01/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
PARALLEL OPTICAL TRANSCEIVER MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13757069
|
Filing Dt:
|
02/01/2013
|
Title:
|
METHODS OF FORMING FINS FOR A FINFET SEMICONDUCTOR DEVICE USING A MANDREL OXIDATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13757205
|
Filing Dt:
|
02/01/2013
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
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METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13757218
|
Filing Dt:
|
02/01/2013
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
PATTERN-BASED REPLACEMENT FOR LAYOUT REGULARIZATION
|
|