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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
01/12/2016
Application #:
13736512
Filing Dt:
01/08/2013
Publication #:
Pub Dt:
05/23/2013
Title:
PLANARIZATION OVER TOPOGRAPHY WITH MOLECULAR GLASS MATERIALS
2
Patent #:
Issue Dt:
11/03/2015
Application #:
13736534
Filing Dt:
01/08/2013
Publication #:
Pub Dt:
07/10/2014
Title:
CRYSTALLINE THIN-FILM TRANSISTOR
3
Patent #:
Issue Dt:
06/09/2015
Application #:
13736535
Filing Dt:
01/08/2013
Publication #:
Pub Dt:
10/17/2013
Title:
HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
4
Patent #:
Issue Dt:
08/05/2014
Application #:
13736672
Filing Dt:
01/08/2013
Publication #:
Pub Dt:
07/10/2014
Title:
PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE
5
Patent #:
Issue Dt:
04/07/2015
Application #:
13737002
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION
6
Patent #:
Issue Dt:
03/17/2015
Application #:
13737067
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
FINFET AND METHOD OF FABRICATION
7
Patent #:
Issue Dt:
01/06/2015
Application #:
13737089
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
STRAINED FINFET WITH AN ELECTRICALLY ISOLATED CHANNEL
8
Patent #:
Issue Dt:
09/09/2014
Application #:
13737099
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
DUAL MANDREL SIDEWALL IMAGE TRANSFER PROCESSES
9
Patent #:
Issue Dt:
04/08/2014
Application #:
13737110
Filing Dt:
01/09/2013
Title:
MULTI-PROTOCOL DRIVER SLEW RATE CALIBRATION SYSTEM FOR CALIBRATING SLEW RATE CONTROL SIGNAL VALUES
10
Patent #:
Issue Dt:
07/01/2014
Application #:
13737231
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
Automatic Generation of Wire Tag Lists for a Metal Stack
11
Patent #:
Issue Dt:
06/16/2015
Application #:
13737611
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
05/23/2013
Title:
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
12
Patent #:
Issue Dt:
09/30/2014
Application #:
13738139
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS
13
Patent #:
Issue Dt:
06/16/2015
Application #:
13738170
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
High-K and Metal Filled Trench-Type EDRAM Capacitor with Electrode Depth and Dimension Control
14
Patent #:
Issue Dt:
12/02/2014
Application #:
13738270
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION
15
Patent #:
Issue Dt:
02/03/2015
Application #:
13738298
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
SELF-FORMED NANOMETER CHANNEL AT WAFER SCALE
16
Patent #:
Issue Dt:
10/14/2014
Application #:
13738367
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
05/16/2013
Title:
ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
17
Patent #:
Issue Dt:
12/31/2013
Application #:
13738435
Filing Dt:
01/10/2013
Title:
FIN REMOVAL METHOD
18
Patent #:
Issue Dt:
06/16/2015
Application #:
13738532
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
SILICON-ON-INSULATOR HEAT SINK
19
Patent #:
Issue Dt:
12/16/2014
Application #:
13738541
Filing Dt:
01/10/2013
Publication #:
Pub Dt:
07/10/2014
Title:
BACKSIDE METAL GROUND PLANE WITH IMPROVED METAL ADHESION AND DESIGN STRUCTURES
20
Patent #:
Issue Dt:
06/10/2014
Application #:
13739123
Filing Dt:
01/11/2013
Publication #:
Pub Dt:
05/23/2013
Title:
REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS
21
Patent #:
Issue Dt:
12/30/2014
Application #:
13739130
Filing Dt:
01/11/2013
Publication #:
Pub Dt:
07/17/2014
Title:
SEMICONDUCTOR DEVICE COMPRISING METALLIZATION LAYERS OF REDUCED INTERLAYER CAPACITANCE BY REDUCING THE AMOUNT OF ETCH STOP MATERIALS
22
Patent #:
Issue Dt:
02/18/2014
Application #:
13739222
Filing Dt:
01/11/2013
Publication #:
Pub Dt:
05/16/2013
Title:
SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP
23
Patent #:
Issue Dt:
03/31/2015
Application #:
13740343
Filing Dt:
01/14/2013
Publication #:
Pub Dt:
07/17/2014
Title:
SELECTIVE REMOVAL OF GATE STRUCTURE SIDEWALL(S) TO FACILITATE SIDEWALL SPACER PROTECTION
24
Patent #:
Issue Dt:
05/12/2015
Application #:
13740974
Filing Dt:
01/14/2013
Publication #:
Pub Dt:
07/17/2014
Title:
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SILICIDE CONTACTS
25
Patent #:
Issue Dt:
08/25/2015
Application #:
13741416
Filing Dt:
01/15/2013
Publication #:
Pub Dt:
07/17/2014
Title:
BURIED WAVEGUIDE PHOTODETECTOR
26
Patent #:
Issue Dt:
03/24/2015
Application #:
13741611
Filing Dt:
01/15/2013
Publication #:
Pub Dt:
07/17/2014
Title:
LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK
27
Patent #:
Issue Dt:
03/24/2015
Application #:
13741638
Filing Dt:
01/15/2013
Publication #:
Pub Dt:
07/17/2014
Title:
TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING
28
Patent #:
Issue Dt:
10/21/2014
Application #:
13741645
Filing Dt:
01/15/2013
Publication #:
Pub Dt:
07/17/2014
Title:
AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY
29
Patent #:
Issue Dt:
07/29/2014
Application #:
13741947
Filing Dt:
01/15/2013
Publication #:
Pub Dt:
07/17/2014
Title:
HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION
30
Patent #:
Issue Dt:
02/03/2015
Application #:
13742465
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
07/25/2013
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
31
Patent #:
Issue Dt:
04/14/2015
Application #:
13742490
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
08/15/2013
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
32
Patent #:
Issue Dt:
01/28/2014
Application #:
13742508
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
05/23/2013
Title:
SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE
33
Patent #:
Issue Dt:
03/17/2015
Application #:
13742526
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
08/01/2013
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
34
Patent #:
Issue Dt:
06/16/2015
Application #:
13742733
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
07/17/2014
Title:
METHODS AND CIRCUITS FOR DISRUPTING INTEGRATED CIRCUIT FUNCTION
35
Patent #:
Issue Dt:
10/28/2014
Application #:
13742916
Filing Dt:
01/16/2013
Publication #:
Pub Dt:
05/23/2013
Title:
SEALED AIR GAP FOR SEMICONDUCTOR CHIP
36
Patent #:
Issue Dt:
01/06/2015
Application #:
13743454
Filing Dt:
01/17/2013
Publication #:
Pub Dt:
07/17/2014
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE
37
Patent #:
Issue Dt:
06/23/2015
Application #:
13743642
Filing Dt:
01/17/2013
Publication #:
Pub Dt:
07/17/2014
Title:
DISASSEMBLABLE ELECTRONIC ASSEMBLY WITH LEAK-INHIBITING COOLANT CAPILLARIES
38
Patent #:
Issue Dt:
09/16/2014
Application #:
13743810
Filing Dt:
01/17/2013
Publication #:
Pub Dt:
07/17/2014
Title:
DETERMINING OVERALL OPTIMAL YIELD POINT FOR A SEMICONDUCTOR WAFER
39
Patent #:
Issue Dt:
12/23/2014
Application #:
13743886
Filing Dt:
01/17/2013
Publication #:
Pub Dt:
07/17/2014
Title:
METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE
40
Patent #:
Issue Dt:
09/27/2016
Application #:
13743935
Filing Dt:
01/17/2013
Publication #:
Pub Dt:
06/06/2013
Title:
METHOD AND APPARATUS FOR OPTICAL MODULATION
41
Patent #:
Issue Dt:
09/27/2016
Application #:
13744551
Filing Dt:
01/18/2013
Publication #:
Pub Dt:
07/24/2014
Title:
THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME
42
Patent #:
Issue Dt:
02/18/2014
Application #:
13744606
Filing Dt:
01/18/2013
Title:
FIN DESIGN LEVEL MASK DECOMPOSITION FOR DIRECTED SELF ASSEMBLY
43
Patent #:
Issue Dt:
05/10/2016
Application #:
13744756
Filing Dt:
01/18/2013
Publication #:
Pub Dt:
07/24/2014
Title:
METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT
44
Patent #:
Issue Dt:
06/16/2015
Application #:
13744761
Filing Dt:
01/18/2013
Publication #:
Pub Dt:
07/24/2014
Title:
MARCHAND BALUN STRUCTURE AND DESIGN METHOD
45
Patent #:
Issue Dt:
10/22/2013
Application #:
13745221
Filing Dt:
01/18/2013
Publication #:
Pub Dt:
05/23/2013
Title:
HIGH ENERGY DENSITY STORAGE MATERIAL DEVICE USING NANOCHANNEL STRUCTURE
46
Patent #:
Issue Dt:
06/30/2015
Application #:
13745547
Filing Dt:
01/18/2013
Publication #:
Pub Dt:
07/24/2014
Title:
FINFET INTEGRATED CIRCUITS WITH UNIFORM FIN HEIGHT AND METHODS FOR FABRICATING THE SAME
47
Patent #:
Issue Dt:
03/03/2015
Application #:
13745770
Filing Dt:
01/19/2013
Publication #:
Pub Dt:
07/24/2014
Title:
Wire-Last Integration Method and Structure for III-V Nanowire Devices
48
Patent #:
Issue Dt:
04/08/2014
Application #:
13745927
Filing Dt:
01/21/2013
Title:
METHODS OF FORMING DIELECTRICALLY ISOLATED FINS FOR A FINFET SEMICONDUCTOR BY PERFORMING AN ETCHING PROCESS WHEREIN THE ETCH RATE IS MODIFIED VIA INCLUSION OF A DOPANT MATERIAL
49
Patent #:
Issue Dt:
03/10/2015
Application #:
13745929
Filing Dt:
01/21/2013
Publication #:
Pub Dt:
07/24/2014
Title:
TEST STRUCTURE AND METHOD TO FACILTIATE DEVELOPMENT/OPTIMIZATION OF PROCESS PARAMETERS
50
Patent #:
Issue Dt:
09/01/2015
Application #:
13745963
Filing Dt:
01/21/2013
Publication #:
Pub Dt:
07/24/2014
Title:
RACETRACK MEMORY CELLS WITH A VERTICAL NANOWIRE STORAGE ELEMENT
51
Patent #:
Issue Dt:
06/16/2015
Application #:
13745965
Filing Dt:
01/21/2013
Publication #:
Pub Dt:
07/24/2014
Title:
LAND GRID ARRAY (LGA) SOCKET CARTRIDGE AND METHOD OF FORMING
52
Patent #:
Issue Dt:
02/23/2016
Application #:
13746359
Filing Dt:
01/22/2013
Publication #:
Pub Dt:
05/29/2014
Title:
WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION
53
Patent #:
Issue Dt:
12/08/2015
Application #:
13746463
Filing Dt:
01/22/2013
Publication #:
Pub Dt:
07/24/2014
Title:
CROSS COMMUNICATION OF COMMON PROBLEM DETERMINATION AND RESOLUTION
54
Patent #:
Issue Dt:
09/16/2014
Application #:
13746508
Filing Dt:
01/22/2013
Publication #:
Pub Dt:
07/24/2014
Title:
SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN
55
Patent #:
Issue Dt:
03/10/2015
Application #:
13746627
Filing Dt:
01/22/2013
Publication #:
Pub Dt:
07/24/2014
Title:
COMPOSITE COPPER WIRE INTERCONNECT STRUCTURES AND METHODS OF FORMING
56
Patent #:
Issue Dt:
03/22/2016
Application #:
13746699
Filing Dt:
01/22/2013
Publication #:
Pub Dt:
07/24/2014
Title:
METHOD AND APPARATUS FOR MEASURING ALPHA PARTICLE INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES
57
Patent #:
Issue Dt:
01/13/2015
Application #:
13747529
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL WITH SENSE AMPLIFIER
58
Patent #:
Issue Dt:
01/26/2016
Application #:
13747579
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTIPLE EMBEDDED INTERCONNECT CONNECTION TO SAME THROUGH-SEMICONDUCTOR VIA
59
Patent #:
Issue Dt:
03/15/2016
Application #:
13747798
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
05/23/2013
Title:
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
60
Patent #:
Issue Dt:
06/23/2015
Application #:
13747842
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
12/19/2013
Title:
BAD WORDLINE/ARRAY DETECTION IN MEMORY
61
Patent #:
Issue Dt:
09/16/2014
Application #:
13747907
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE
62
Patent #:
Issue Dt:
02/25/2014
Application #:
13748038
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
05/30/2013
Title:
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
63
Patent #:
Issue Dt:
02/16/2016
Application #:
13748048
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE
64
Patent #:
Issue Dt:
09/12/2017
Application #:
13748159
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH METAL LAYER CONNECTION TO THROUGH-SEMICONDUCTOR VIA
65
Patent #:
Issue Dt:
11/25/2014
Application #:
13748197
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
07/24/2014
Title:
SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY
66
Patent #:
Issue Dt:
12/16/2014
Application #:
13748226
Filing Dt:
01/23/2013
Publication #:
Pub Dt:
05/30/2013
Title:
TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
67
Patent #:
Issue Dt:
06/16/2015
Application #:
13748662
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
05/30/2013
Title:
STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
68
Patent #:
Issue Dt:
01/13/2015
Application #:
13748821
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
07/24/2014
Title:
IN-SITU THERMOELECTRIC COOLING
69
Patent #:
Issue Dt:
09/16/2014
Application #:
13748942
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
05/30/2013
Title:
STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
70
Patent #:
Issue Dt:
09/30/2014
Application #:
13749146
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
05/30/2013
Title:
METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
71
Patent #:
Issue Dt:
01/12/2016
Application #:
13749330
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
10/24/2013
Title:
LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING
72
Patent #:
Issue Dt:
11/25/2014
Application #:
13749744
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
06/06/2013
Title:
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
73
Patent #:
Issue Dt:
09/16/2014
Application #:
13749745
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
06/06/2013
Title:
CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
74
Patent #:
Issue Dt:
08/09/2016
Application #:
13749830
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
07/31/2014
Title:
SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD
75
Patent #:
Issue Dt:
09/16/2014
Application #:
13749851
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
12/05/2013
Title:
POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL
76
Patent #:
Issue Dt:
09/16/2014
Application #:
13749925
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
07/31/2014
Title:
POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPERATURE-BASED VOLTAGE CONTROL
77
Patent #:
Issue Dt:
12/17/2013
Application #:
13750497
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
05/30/2013
Title:
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
78
Patent #:
Issue Dt:
12/01/2015
Application #:
13750751
Filing Dt:
01/25/2013
Publication #:
Pub Dt:
07/31/2014
Title:
INTERPOLATION TECHNIQUES USED FOR TIME ALIGNMENT OF MULTIPLE SIMULATION MODELS
79
Patent #:
Issue Dt:
11/18/2014
Application #:
13751238
Filing Dt:
01/28/2013
Publication #:
Pub Dt:
07/31/2014
Title:
METHOD OF FORMING ELECTRONIC FUSE LINE WITH MODIFIED CAP
80
Patent #:
Issue Dt:
12/30/2014
Application #:
13751361
Filing Dt:
01/28/2013
Publication #:
Pub Dt:
06/06/2013
Title:
STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS
81
Patent #:
Issue Dt:
06/23/2015
Application #:
13751490
Filing Dt:
01/28/2013
Publication #:
Pub Dt:
07/31/2014
Title:
Nanowire Capacitor for Bidirectional Operation
82
Patent #:
Issue Dt:
06/16/2015
Application #:
13751799
Filing Dt:
01/28/2013
Publication #:
Pub Dt:
05/15/2014
Title:
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
83
Patent #:
Issue Dt:
05/26/2015
Application #:
13752567
Filing Dt:
01/29/2013
Publication #:
Pub Dt:
06/06/2013
Title:
STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
84
Patent #:
Issue Dt:
02/10/2015
Application #:
13752737
Filing Dt:
01/29/2013
Publication #:
Pub Dt:
07/31/2014
Title:
ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS
85
Patent #:
Issue Dt:
04/05/2016
Application #:
13752948
Filing Dt:
01/29/2013
Publication #:
Pub Dt:
06/06/2013
Title:
EFFICIENT DATA EXTRACTION BY A REMOTE APPLICATION
86
Patent #:
Issue Dt:
09/09/2014
Application #:
13753269
Filing Dt:
01/29/2013
Publication #:
Pub Dt:
07/31/2014
Title:
METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES
87
Patent #:
Issue Dt:
01/13/2015
Application #:
13753989
Filing Dt:
01/30/2013
Publication #:
Pub Dt:
07/31/2014
Title:
PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE
88
Patent #:
Issue Dt:
11/11/2014
Application #:
13754170
Filing Dt:
01/30/2013
Publication #:
Pub Dt:
07/31/2014
Title:
ACHIEVING GREATER PLANARITY BETWEEN UPPER SURFACES OF A LAYER AND A CONDUCTIVE STRUCTURE RESIDING THEREIN
89
Patent #:
Issue Dt:
04/07/2015
Application #:
13755030
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
07/31/2014
Title:
ELECTRONIC FUSE HAVING AN INSULATION LAYER
90
Patent #:
Issue Dt:
04/29/2014
Application #:
13755192
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
06/06/2013
Title:
BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE
91
Patent #:
Issue Dt:
08/26/2014
Application #:
13755246
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
07/31/2014
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS
92
Patent #:
Issue Dt:
12/30/2014
Application #:
13755374
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
07/31/2014
Title:
AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS
93
Patent #:
Issue Dt:
09/29/2015
Application #:
13755726
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
06/19/2014
Title:
ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION
94
Patent #:
Issue Dt:
10/21/2014
Application #:
13755807
Filing Dt:
01/31/2013
Publication #:
Pub Dt:
06/06/2013
Title:
METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS
95
Patent #:
Issue Dt:
11/04/2014
Application #:
13756689
Filing Dt:
02/01/2013
Publication #:
Pub Dt:
08/07/2014
Title:
DOUBLE-PATTERN GATE FORMATION PROCESSING WITH CRITICAL DIMENSION CONTROL
96
Patent #:
Issue Dt:
03/25/2014
Application #:
13756981
Filing Dt:
02/01/2013
Publication #:
Pub Dt:
06/06/2013
Title:
METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE
97
Patent #:
Issue Dt:
09/17/2013
Application #:
13757040
Filing Dt:
02/01/2013
Publication #:
Pub Dt:
06/06/2013
Title:
PARALLEL OPTICAL TRANSCEIVER MODULE
98
Patent #:
Issue Dt:
05/06/2014
Application #:
13757069
Filing Dt:
02/01/2013
Title:
METHODS OF FORMING FINS FOR A FINFET SEMICONDUCTOR DEVICE USING A MANDREL OXIDATION PROCESS
99
Patent #:
Issue Dt:
05/12/2015
Application #:
13757205
Filing Dt:
02/01/2013
Publication #:
Pub Dt:
08/07/2014
Title:
METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER
100
Patent #:
Issue Dt:
09/02/2014
Application #:
13757218
Filing Dt:
02/01/2013
Publication #:
Pub Dt:
08/07/2014
Title:
PATTERN-BASED REPLACEMENT FOR LAYOUT REGULARIZATION
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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