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Patent #:
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Issue Dt:
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10/23/2018
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13775416
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Filing Dt:
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02/25/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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METHOD OF FORMING A HIGH QUALITY INTERFACIAL LAYER FOR A SEMICONDUCTOR DEVICE BY PERFORMING A LOW TEMPERATURE ALD PROCESS
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Patent #:
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12/02/2014
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13775430
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Filing Dt:
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02/25/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
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05/06/2014
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13775570
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02/25/2013
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
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02/17/2015
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13775917
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02/25/2013
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Pub Dt:
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08/28/2014
| | | | |
Title:
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U-SHAPED SEMICONDUCTOR STRUCTURE
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02/18/2014
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13775958
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02/25/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES
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08/19/2014
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13775968
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02/25/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER
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12/01/2015
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13775988
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02/25/2013
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Pub Dt:
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11/21/2013
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Title:
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MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
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06/03/2014
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13776016
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02/25/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES
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Patent #:
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12/09/2014
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13776324
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Filing Dt:
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02/25/2013
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Publication #:
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Pub Dt:
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08/28/2014
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Title:
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SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION
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Patent #:
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Issue Dt:
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09/27/2016
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13776902
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02/26/2013
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Pub Dt:
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08/28/2014
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Title:
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CHARACTERIZATION OF INTERFACE RESISTANCE IN A MULTI-LAYER CONDUCTIVE STRUCTURE
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Patent #:
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06/16/2015
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13776911
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02/26/2013
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Publication #:
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Pub Dt:
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01/23/2014
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Title:
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SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
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Patent #:
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07/28/2015
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13777353
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02/26/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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EPITAXIAL EXTENSION CMOS TRANSISTOR
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Issue Dt:
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07/21/2015
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13777364
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02/26/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER
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Patent #:
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02/11/2014
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13777402
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF
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12/16/2014
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13777493
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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09/23/2014
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13777506
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02/26/2013
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Pub Dt:
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04/03/2014
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Title:
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POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13778314
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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STRESS MEMORIZATION IN RMG FINFETS
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13778321
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13778322
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS
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Patent #:
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Issue Dt:
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04/05/2016
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13778419
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02/27/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13778479
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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BI-DIRECTIONAL SILICON CONTROLLED RECTIFIER STRUCTURE
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13778558
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13779036
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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INFORMATION ENCODING USING WIREBONDS
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Patent #:
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Issue Dt:
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03/22/2016
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13780003
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13780205
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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06/12/2014
| | | | |
Title:
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DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
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Patent #:
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Issue Dt:
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04/28/2015
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Application #:
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13780449
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/18/2013
| | | | |
Title:
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DEPOSITION CHAMBER CLEANING METHOD INCLUDING STRESSED CLEANING LAYER
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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13780454
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SINGLE-JUNCTION PHOTOVOLTAIC CELL
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13780762
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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13780877
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13780887
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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01/02/2014
| | | | |
Title:
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INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING
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Patent #:
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Issue Dt:
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12/15/2015
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Application #:
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13780912
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13781874
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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METHODS OF FORMING ASYMMETRIC SPACERS ON VARIOUS STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13781907
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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METAL GATE STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13781921
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13782094
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION
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Patent #:
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NONE
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Application #:
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13782106
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS
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Patent #:
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Issue Dt:
|
06/30/2015
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Application #:
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13782364
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN DISK DRIVE
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13782452
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
09/05/2013
| | | | |
Title:
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SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
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Patent #:
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Issue Dt:
|
05/05/2015
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Application #:
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13782467
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13782537
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13782561
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13782678
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
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Patent #:
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Issue Dt:
|
05/27/2014
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Application #:
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13782826
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Filing Dt:
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03/01/2013
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Title:
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METHODS OF MODIFYING A PHYSICAL DESIGN OF AN ELECTRICAL CIRCUIT USED IN THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
02/18/2014
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Application #:
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13783388
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Filing Dt:
|
03/03/2013
|
Title:
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SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
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Patent #:
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Issue Dt:
|
04/01/2014
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Application #:
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13783438
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Filing Dt:
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03/04/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
|
04/21/2015
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Application #:
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13783517
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Filing Dt:
|
03/04/2013
|
Publication #:
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|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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CHANNEL SIGE REMOVAL FROM PFET SOURCE/DRAIN REGION FOR IMPROVED SILICIDE FORMATION IN HKMG TECHNOLOGIES WITHOUT EMBEDDED SIGE
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Patent #:
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Issue Dt:
|
12/31/2013
|
Application #:
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13783526
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Filing Dt:
|
03/04/2013
|
Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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FIELD EFFECT TRANSISTOR DEVICE
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Patent #:
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Issue Dt:
|
12/16/2014
|
Application #:
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13783562
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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DEFECT REMOVAL PROCESS
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13783705
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Filing Dt:
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03/04/2013
|
Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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PLANAR QUBITS HAVING INCREASED COHERENCE TIMES
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Patent #:
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Issue Dt:
|
08/26/2014
|
Application #:
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13783715
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Filing Dt:
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03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
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Patent #:
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Issue Dt:
|
03/31/2015
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Application #:
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13783729
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
07/03/2014
| | | | |
Title:
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HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13783943
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
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Patent #:
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Issue Dt:
|
02/03/2015
|
Application #:
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13784220
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Filing Dt:
|
03/04/2013
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Publication #:
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Pub Dt:
|
09/04/2014
| | | | |
Title:
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CONTACT POWER RAIL
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Patent #:
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Issue Dt:
|
03/04/2014
|
Application #:
|
13785109
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Filing Dt:
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03/05/2013
|
Title:
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TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
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Patent #:
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Issue Dt:
|
01/27/2015
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Application #:
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13785403
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Filing Dt:
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03/05/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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Patent #:
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Issue Dt:
|
03/18/2014
|
Application #:
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13785438
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Filing Dt:
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03/05/2013
|
Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
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|
Patent #:
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Issue Dt:
|
02/03/2015
|
Application #:
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13785468
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Filing Dt:
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03/05/2013
|
Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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Patent #:
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|
Issue Dt:
|
02/10/2015
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Application #:
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13785480
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Filing Dt:
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03/05/2013
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Publication #:
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|
Pub Dt:
|
07/25/2013
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Title:
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SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS
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Patent #:
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Issue Dt:
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09/02/2014
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Application #:
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13785602
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Filing Dt:
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03/05/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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MEMORY STATE SENSING BASED ON CELL CAPACITANCE
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Patent #:
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Issue Dt:
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09/02/2014
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Application #:
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13785816
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Filing Dt:
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03/05/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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FRONT SIDE WAFER ID PROCESSING
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13785934
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Filing Dt:
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03/05/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13786627
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Filing Dt:
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03/06/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS
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Patent #:
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Issue Dt:
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10/25/2016
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Application #:
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13787090
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Filing Dt:
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03/06/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13787384
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Filing Dt:
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03/06/2013
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Title:
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METHODS OF SELECTIVELY FORMING RUTHENIUM LINER LAYER
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13787521
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Filing Dt:
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03/06/2013
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13788406
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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07/18/2013
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Title:
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High Density Memory Cells Using Lateral Epitaxy
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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13788450
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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APPARATUS AND METHOD FOR CONTROLLED ACCESS TO PRESSURIZED FLUID LINES AND TO EXHAUSTED LINES
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Patent #:
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Issue Dt:
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12/15/2015
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Application #:
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13788689
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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11/28/2013
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Title:
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STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs)
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13788719
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE STRUCTURES
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13788744
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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12/19/2013
| | | | |
Title:
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BITLINE DELETION
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13788980
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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07/18/2013
| | | | |
Title:
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HIGH CAPACITANCE TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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13789018
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Filing Dt:
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03/07/2013
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Publication #:
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Pub Dt:
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08/01/2013
| | | | |
Title:
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REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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13789792
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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Self-aligned Contacts For Replacement Metal Gate Transistors
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13790399
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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ELECTRONIC FUSE WITH RESISTIVE HEATER
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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13790727
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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SCATTERING ENHANCED THIN ABSORBER FOR EUV RETICLE AND A METHOD OF MAKING
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13791502
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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08/15/2013
| | | | |
Title:
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AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13791520
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
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Patent #:
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Issue Dt:
|
11/18/2014
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Application #:
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13791545
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Filing Dt:
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03/08/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
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|
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Patent #:
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Issue Dt:
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12/29/2015
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Application #:
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13792540
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS
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|
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Patent #:
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|
Issue Dt:
|
08/09/2016
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Application #:
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13792730
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13792933
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
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|
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13792946
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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13792950
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS
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|
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Patent #:
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|
Issue Dt:
|
08/26/2014
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Application #:
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13793082
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL
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Patent #:
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Issue Dt:
|
02/24/2015
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Application #:
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13793185
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
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|
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13793363
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
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Patent #:
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|
Issue Dt:
|
05/24/2016
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Application #:
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13793645
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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10/17/2013
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICES COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS
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Patent #:
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Issue Dt:
|
04/14/2015
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Application #:
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13793804
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Filing Dt:
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03/11/2013
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Publication #:
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Pub Dt:
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09/11/2014
| | | | |
Title:
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MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
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Patent #:
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Issue Dt:
|
09/09/2014
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Application #:
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13795030
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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FLUID DISTRIBUTION METHOD FACILITATING COOLING OF ELECTRONICS RACK(S) AND SIMULATING HEATED AIRFLOW EXHAUST OF ELECTRONICS RACK(S)
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Patent #:
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Issue Dt:
|
06/10/2014
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Application #:
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13795198
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Filing Dt:
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03/12/2013
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Title:
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HIERARCHICAL LAYOUT VERSUS SCHEMATIC (LVS) COMPARISON WITH EXTRANEOUS DEVICE ELIMINATION
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Patent #:
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Issue Dt:
|
02/17/2015
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Application #:
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13795513
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
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10/03/2013
| | | | |
Title:
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MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM
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Patent #:
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Issue Dt:
|
06/03/2014
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Application #:
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13796154
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
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|
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Patent #:
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Issue Dt:
|
09/09/2014
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Application #:
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13796259
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
|
12/02/2014
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Application #:
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13796278
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Filing Dt:
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03/12/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS
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Patent #:
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Issue Dt:
|
07/15/2014
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Application #:
|
13796418
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Filing Dt:
|
03/12/2013
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Title:
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NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH EPITIXIALLY GROWN SOURCE AND DRAIN
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Patent #:
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Issue Dt:
|
02/23/2016
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Application #:
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13796674
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Filing Dt:
|
03/12/2013
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Publication #:
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Pub Dt:
|
08/15/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
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Application #:
|
13797001
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Filing Dt:
|
03/12/2013
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Publication #:
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|
Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
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|
|
Patent #:
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Issue Dt:
|
01/20/2015
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Application #:
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13797117
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Filing Dt:
|
03/12/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING FINFET DEVICES WITH A SHARED GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
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13798429
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Filing Dt:
|
03/13/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
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METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
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Application #:
|
13798446
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Filing Dt:
|
03/13/2013
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HIGH DENSITY MULTI-ELECTRODE ARRAY
|
|