|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13798449
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
Method and System for Improving Alignment Precision of Parts in MEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13798573
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13798616
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE BY PERFORMING AN ANNEAL PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
13798643
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13798690
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A MASKING LAYER FOR PATTERNING UNDERLYING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
|
Application #:
|
13798764
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A PROTECTION LAYER TO PROTECT A METAL HARD MASK LAYER DURING LITHOGRAPHY REWORKING PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13799148
|
Filing Dt:
|
03/13/2013
|
Title:
|
THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13799165
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
RETICLE DEFECT CORRECTION BY SECOND EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13799239
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
TECHNIQUE FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13799508
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
HARD MASK REMOVAL DURING FINFET FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13799539
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13799741
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13799814
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING CONTROLLED FINAL METAL CRITICAL DIMENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13800091
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FABRICATING BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13800966
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13803048
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT)
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13803281
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
HIGHLY SCALABLE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13803293
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
HYBRID METHOD FOR PERFORMING FULL FIELD OPTICAL PROXIMITY CORRECTION FOR FINFET MANDREL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13803856
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
13804112
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING GUIDE PATTERNS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH GUIDE PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13826316
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
DYNAMIC PEAK TRACKING IN X-RAY PHOTOELECTRON SPECTROSCOPY MEASUREMENT TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13826628
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
ELECTRICAL LEAKAGE REDUCTION IN STACKED INTEGRATED CIRCUITS HAVING THROUGH-SILICON-VIA (TSV) STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13826631
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13826830
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13826874
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
METHOD FOR FORMING SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13826936
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13827690
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
IMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13827786
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL-INSULATOR-METAL CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13828276
|
Filing Dt:
|
03/14/2013
|
Title:
|
DOPING OF FINFET STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
13828650
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13828936
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
DUAL THREE-DIMENSIONAL (3D) RESISTOR AND METHODS OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13832442
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13832929
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
LOW HARMONIC RF SWITCH IN SOI
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13832994
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING MULTI-PATTERNING OF MASKS FOR EXTREME ULTRAVIOLET LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13833104
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROVIDING METRIC RELATING TWO OR MORE PROCESS PARAMETERS TO YIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
13833139
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
13833317
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
WET STRIP PROCESS FOR AN ANTIREFLECTIVE COATING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13833656
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR PFET JUNCTION PROFILE WITH SIGE CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13833713
|
Filing Dt:
|
03/15/2013
|
Title:
|
FACILITATING THE DESIGN OF A CLOCK GRID IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13833735
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13833932
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS AND SYSTEMS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING UNIVERSAL AND LOCAL PROCESSING MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13834019
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13834058
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13834410
|
Filing Dt:
|
03/15/2013
|
Title:
|
METHODS OF FORMING ISOLATION STRUCTURES AND FINS ON A FINFET SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
13834608
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13834946
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
13835166
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PASSIVE COMPRESSED GAS STORAGE CONTAINER TEMPERATURE STABILIZER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13835358
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13835463
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
13835944
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13836057
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13837624
|
Filing Dt:
|
03/15/2013
|
Title:
|
VIA NON-STANDARD LIMITING PARAMETERS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13837763
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS)
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13837810
|
Filing Dt:
|
03/15/2013
|
Title:
|
SELF ALIGNED CAPACITOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13838378
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13838956
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13839020
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13839100
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13839161
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13839213
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
Title:
|
THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13839275
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13839284
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13839626
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13839802
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13840132
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
CAPACITOR USING BARRIER LAYER METALLURGY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13840692
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
WRAP AROUND STRESSOR FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13840790
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING EUV MASKS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH EUV MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13841694
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13841919
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES USING DIFFERENT METROLOGY TOOLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
13842077
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SEMICONDUCTOR SUBSTRATE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13842103
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH GATE ELECTRODE STRUCTURE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13842217
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13842564
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13845506
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13845560
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13846044
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13846158
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
FORMING CONSTANT DIAMETER SPHERICAL METAL BALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13846229
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13847662
|
Filing Dt:
|
03/20/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13847695
|
Filing Dt:
|
03/20/2013
|
Publication #:
|
|
Pub Dt:
|
09/25/2014
| | | | |
Title:
|
SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13849565
|
Filing Dt:
|
03/25/2013
|
Publication #:
|
|
Pub Dt:
|
09/25/2014
| | | | |
Title:
|
WORKFUNCTION MODULATION-BASED SENSOR TO MEASURE PRESSURE AND TEMPERATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13849575
|
Filing Dt:
|
03/25/2013
|
Publication #:
|
|
Pub Dt:
|
09/25/2014
| | | | |
Title:
|
EVALUATION OF PIN GEOMETRY ACCESSIBILITY IN A LAYER OF CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13849764
|
Filing Dt:
|
03/25/2013
|
Title:
|
GENERATION OF DESIGN SHAPES FOR CONFINING STITCH-INDUCED VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13850470
|
Filing Dt:
|
03/26/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
SPACER REPLACEMENT FOR REPLACEMENT METAL GATE SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13851202
|
Filing Dt:
|
03/27/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
SIGNAL MARGIN CENTERING FOR SINGLE-ENDED EDRAM SENSE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13851333
|
Filing Dt:
|
03/27/2013
|
Title:
|
COMPUTATIONAL THERMAL ANALYSIS DURING MICROCHIP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13851810
|
Filing Dt:
|
03/27/2013
|
Title:
|
INTEGRATED CIRCUITS HAVING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13852043
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
METHODS OF FORMING MASKING LAYERS FOR USE IN FORMING INTEGRATED CIRCUIT PRODUCTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13852084
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
METHODS OF FORMING A BARRIER SYSTEM CONTAINING AN ALLOY OF METALS INTRODUCED INTO THE BARRIER SYSTEM, AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH A BARRIER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13852086
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
FET SEMICONDUCTOR DEVICE WITH LOW RESISTANCE AND ENHANCED METAL FILL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13852103
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13852428
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13852496
|
Filing Dt:
|
03/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13853178
|
Filing Dt:
|
03/29/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
THROUGH-SILICON VIA WITH SIDEWALL AIR GAP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13853301
|
Filing Dt:
|
03/29/2013
|
Publication #:
|
|
Pub Dt:
|
10/02/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH METAL LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13858198
|
Filing Dt:
|
04/08/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE COMPRISING AN INTER-DIE CONNECTION ON THE BASIS OF FUNCTIONAL MOLECULES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13859284
|
Filing Dt:
|
04/09/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
SELF-ALIGNED CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13859738
|
Filing Dt:
|
04/10/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13859773
|
Filing Dt:
|
04/10/2013
|
Publication #:
|
|
Pub Dt:
|
10/16/2014
| | | | |
Title:
|
SYSTEM FOR SEPARATELY HANDLING DIFFERENT SIZE FOUPS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13859802
|
Filing Dt:
|
04/10/2013
|
Publication #:
|
|
Pub Dt:
|
10/16/2014
| | | | |
Title:
|
REPLACEMENT GATE INTEGRATION SCHEME EMPLOYING MULTIPLE TYPES OF DISPOSABLE GATE STRUCTURES
|
|