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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 11 of 146
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1
Patent #:
6658610
Issue Dt:
12/02/2003
Application #:
09669117
Filing Dt:
09/25/2000
Title:
COMPILABLE ADDRESS MAGNITUDE COMPARATOR FOR MEMORY ARRAY SELF-TESTING
2
Patent #:
6586746
Issue Dt:
07/01/2003
Application #:
09670728
Filing Dt:
09/27/2000
Title:
MULTIPOLE ELECTROSTATIC E-BEAM DEFLECTOR
3
Patent #:
6509226
Issue Dt:
01/21/2003
Application #:
09670741
Filing Dt:
09/27/2000
Title:
PROCESS FOR PROTECTING ARRAY TOP OXIDE
4
Patent #:
6522014
Issue Dt:
02/18/2003
Application #:
09670968
Filing Dt:
09/27/2000
Title:
FABRICATION OF A METALIZED BLIND VIA
5
Patent #:
6518648
Issue Dt:
02/11/2003
Application #:
09671944
Filing Dt:
09/27/2000
Title:
SUPERCONDUCTOR BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
6
Patent #:
6509624
Issue Dt:
01/21/2003
Application #:
09675246
Filing Dt:
09/29/2000
Title:
SEMICONDUCTOR FUSES AND ANTIFUSES IN VERTICAL DRAMS
7
Patent #:
6794242
Issue Dt:
09/21/2004
Application #:
09675435
Filing Dt:
09/29/2000
Title:
EXTENDIBLE PROCESS FOR IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS WHILE PROVIDING SELF-ALIGNED GATE CONTACTS
8
Patent #:
6601223
Issue Dt:
07/29/2003
Application #:
09675634
Filing Dt:
09/29/2000
Title:
SYSTEM AND METHOD FOR FAST INTERCONNECT DELAY ESTIMATION THROUGH ITERATIVE REFINEMENT
9
Patent #:
6524935
Issue Dt:
02/25/2003
Application #:
09675840
Filing Dt:
09/29/2000
Title:
PREPARATION OF STRAINED SI/SIGE ON INSULATOR BY HYDROGEN INDUCED LAYER TRANSFER TECHNIQUE
10
Patent #:
6664186
Issue Dt:
12/16/2003
Application #:
09676882
Filing Dt:
09/29/2000
Title:
METHOD OF FILM DEPOSITION, AND FABRICATION OF STRUCTURES
11
Patent #:
6668078
Issue Dt:
12/23/2003
Application #:
09676883
Filing Dt:
09/29/2000
Title:
SYSTEM AND METHOD FOR SEGMENTATION OF IMAGES OF OBJECTS THAT ARE OCCLUDED BY A SEMI-TRANSPARENT MATERIAL
12
Patent #:
6277661
Issue Dt:
08/21/2001
Application #:
09677955
Filing Dt:
10/02/2000
Title:
Method for detecting sloped contact holes using a critical-dimension waveform
13
Patent #:
6538299
Issue Dt:
03/25/2003
Application #:
09678315
Filing Dt:
10/03/2000
Title:
SILICON-ON-INSULATOR (SOI) TRENCH PHOTODIODE
14
Patent #:
6419785
Issue Dt:
07/16/2002
Application #:
09678633
Filing Dt:
10/03/2000
Title:
ENDPOINT DETECTION BY CHEMICAL REACTION
15
Patent #:
6501177
Issue Dt:
12/31/2002
Application #:
09678946
Filing Dt:
10/03/2000
Title:
ATOMIC LAYER BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
16
Patent #:
6343044
Issue Dt:
01/29/2002
Application #:
09679124
Filing Dt:
10/04/2000
Title:
Super low-power generator system for embedded applications
17
Patent #:
6465334
Issue Dt:
10/15/2002
Application #:
09679369
Filing Dt:
10/05/2000
Title:
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
18
Patent #:
6451693
Issue Dt:
09/17/2002
Application #:
09679370
Filing Dt:
10/05/2000
Title:
DOUBLE SILICIDE FORMATION IN POLYSILICON GATE WITHOUT SILICIDE IN SOURCE/DRAIN EXTENSIONS
19
Patent #:
6483154
Issue Dt:
11/19/2002
Application #:
09679373
Filing Dt:
10/05/2000
Title:
NITROGEN OXIDE PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
20
Patent #:
6383880
Issue Dt:
05/07/2002
Application #:
09679374
Filing Dt:
10/05/2000
Title:
NH3/N2-PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
21
Patent #:
6545370
Issue Dt:
04/08/2003
Application #:
09679375
Filing Dt:
10/05/2000
Title:
COMPOSITE SILICON NITRIDE SIDEWALL SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
22
Patent #:
6436823
Issue Dt:
08/20/2002
Application #:
09679738
Filing Dt:
10/05/2000
Title:
METHOD FOR FORMING A TIN LAYER ON TOP OF A METAL SILICIDE LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURE FORMED
23
Patent #:
6300203
Issue Dt:
10/09/2001
Application #:
09679872
Filing Dt:
10/05/2000
Title:
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
24
Patent #:
6521529
Issue Dt:
02/18/2003
Application #:
09679880
Filing Dt:
10/05/2000
Title:
HDP TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
25
Patent #:
6587530
Issue Dt:
07/01/2003
Application #:
09680819
Filing Dt:
10/05/2000
Title:
METHOD AND APPARATUS FOR SIGNAL INTEGRITY VERIFICATION
26
Patent #:
6545333
Issue Dt:
04/08/2003
Application #:
09681541
Filing Dt:
04/25/2001
Title:
LIGHT CONTROLLED SILICON ON INSULATOR DEVICE
27
Patent #:
6441462
Issue Dt:
08/27/2002
Application #:
09682016
Filing Dt:
07/10/2001
Title:
SELF-ALIGNED SIGE NPN WITH IMPROVED ESD ROBUSTNESS USING WIDE EMITTER POLYSILICON EXTENSION
28
Patent #:
6430072
Issue Dt:
08/06/2002
Application #:
09682638
Filing Dt:
10/01/2001
Title:
EMBEDDED CAM TEST STRUCTURE FOR FULLY TESTING ALL MATCHLINES
29
Patent #:
6651229
Issue Dt:
11/18/2003
Application #:
09682707
Filing Dt:
10/09/2001
Publication #:
US20030070150
Pub Dt:
04/10/2003
Title:
GENERATION OF REFINED SWITCHING WINDOWS IN STATIC TIMING ANALYSIS
30
Patent #:
6469350
Issue Dt:
10/22/2002
Application #:
09682868
Filing Dt:
10/26/2001
Title:
ACTIVE WELL SCHEMES FOR SOI TECHNOLOGY
31
Patent #:
6834360
Issue Dt:
12/21/2004
Application #:
09683091
Filing Dt:
11/16/2001
Publication #:
US20030097615
Pub Dt:
05/22/2003
Title:
ON-CHIP LOGIC ANALYZER
32
Patent #:
6433609
Issue Dt:
08/13/2002
Application #:
09683105
Filing Dt:
11/19/2001
Title:
DOUBLE-GATE LOW POWER SOI ACTIVE CLAMP NETWORK FOR SINGLE POWER SUPPLY AND MULTIPLE POWER SUPPLY APPLICATIONS
33
Patent #:
6800905
Issue Dt:
10/05/2004
Application #:
09683328
Filing Dt:
12/14/2001
Publication #:
US20030113970
Pub Dt:
06/19/2003
Title:
IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
34
Patent #:
6774437
Issue Dt:
08/10/2004
Application #:
09683486
Filing Dt:
01/07/2002
Publication #:
US20030127690
Pub Dt:
07/10/2003
Title:
FIN-BASED DOUBLE POLY DYNAMIC THRESHOLD CMOS FET WITH SPACER GATE AND METHOD OF FABRICATION
35
Patent #:
6670654
Issue Dt:
12/30/2003
Application #:
09683498
Filing Dt:
01/09/2002
Publication #:
US20030129802
Pub Dt:
07/10/2003
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
36
Patent #:
6583469
Issue Dt:
06/24/2003
Application #:
09683626
Filing Dt:
01/28/2002
Title:
SELF-ALIGNED DOG-BONE STRUCTURE FOR FINFET APPLICATIONS AND METHODS TO FABRICATE THE SAME
37
Patent #:
6624478
Issue Dt:
09/23/2003
Application #:
09683656
Filing Dt:
01/30/2002
Publication #:
US20030141548
Pub Dt:
07/31/2003
Title:
HIGH MOBILITY TRANSISTORS IN SOI AND METHOD FOR FORMING
38
Patent #:
7353156
Issue Dt:
04/01/2008
Application #:
09683677
Filing Dt:
02/01/2002
Publication #:
US20030149946
Pub Dt:
08/07/2003
Title:
METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM
39
Patent #:
6621324
Issue Dt:
09/16/2003
Application #:
09683808
Filing Dt:
02/19/2002
Publication #:
US20030155961
Pub Dt:
08/21/2003
Title:
REDUNDANT ANTIFUSE SEGMENTS FOR IMPROVED PROGRAMMING EFFICIENCY
40
Patent #:
6518614
Issue Dt:
02/11/2003
Application #:
09683809
Filing Dt:
02/19/2002
Title:
EMBEDDED ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY USING PROMPT SHIFT DEVICE
41
Patent #:
6724029
Issue Dt:
04/20/2004
Application #:
09683831
Filing Dt:
02/21/2002
Publication #:
US20030155599
Pub Dt:
08/21/2003
Title:
TWIN-CELL FLASH MEMORY STRUCTURE AND METHOD
42
Patent #:
6744079
Issue Dt:
06/01/2004
Application #:
09683983
Filing Dt:
03/08/2002
Publication #:
US20030170960
Pub Dt:
09/11/2003
Title:
OPTIMIZED BLOCKING IMPURITY PLACEMENT FOR SIGE HBTS
43
Patent #:
7384854
Issue Dt:
06/10/2008
Application #:
09683985
Filing Dt:
03/08/2002
Publication #:
US20030168701
Pub Dt:
09/11/2003
Title:
METHOD OF FORMING LOW CAPACITANCE ESD ROBUST DIODES
44
Patent #:
6586818
Issue Dt:
07/01/2003
Application #:
09683986
Filing Dt:
03/08/2002
Title:
SELF-ALIGNED SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE WITH ELECTROSTATIC DISCHARGE CREVICE COVER FOR SALICIDE DISPLACEMENT
45
Patent #:
6784516
Issue Dt:
08/31/2004
Application #:
09684463
Filing Dt:
10/06/2000
Title:
INSULATIVE CAP FOR LASER FUSING
46
Patent #:
6624651
Issue Dt:
09/23/2003
Application #:
09684849
Filing Dt:
10/06/2000
Title:
KERF CIRCUIT FOR MODELING OF BEOL CAPACITANCES
47
Patent #:
6380041
Issue Dt:
04/30/2002
Application #:
09686476
Filing Dt:
10/10/2000
Title:
SEMICONDUCTOR WITH LATERALLY NON-UNIFORM CHANNEL DOPING PROFILE AND MANUFACTURING METHOD THEREFOR
48
Patent #:
6570568
Issue Dt:
05/27/2003
Application #:
09686720
Filing Dt:
10/10/2000
Title:
SYSTEM AND METHOD FOR THE COORDINATED SIMPLIFICATION OF SURFACE AND WIRE-FRAME DESCRIPTIONS OF A GEOMETRIC MODEL
49
Patent #:
6700203
Issue Dt:
03/02/2004
Application #:
09686742
Filing Dt:
10/11/2000
Title:
SEMICONDUCTOR STRUCTURE HAVING IN-SITU FORMED UNIT RESISTORS AND METHOD FOR FABRICATION
50
Patent #:
6472755
Issue Dt:
10/29/2002
Application #:
09688928
Filing Dt:
10/17/2000
Title:
SEMICONDUCTOR DEVICE COMPRISING COPPER INTERCONNECTS WITH REDUCED IN-LINE COPPER DIFFUSION
51
Patent #:
6350653
Issue Dt:
02/26/2002
Application #:
09689096
Filing Dt:
10/12/2000
Title:
Embedded dram on silicon-on-insulator substrate
52
Patent #:
6351023
Issue Dt:
02/26/2002
Application #:
09689660
Filing Dt:
10/13/2000
Title:
Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
53
Patent #:
6312998
Issue Dt:
11/06/2001
Application #:
09690073
Filing Dt:
10/16/2000
Title:
Field effect transistor with spacers that are removable with preservation of the gate dielectric
54
Patent #:
6555891
Issue Dt:
04/29/2003
Application #:
09690674
Filing Dt:
10/17/2000
Title:
SOI HYBRID STRUCTURE WITH SELECTIVE EPITAXIAL GROWTH OF SILICON
55
Patent #:
6554951
Issue Dt:
04/29/2003
Application #:
09690704
Filing Dt:
10/16/2000
Title:
CHEMICAL-MECHANICAL POLISHING PAD CONDITIONING SYSTEM AND METHOD
56
Patent #:
6528362
Issue Dt:
03/04/2003
Application #:
09691181
Filing Dt:
10/19/2000
Title:
METAL GATE WITH CVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
57
Patent #:
6392280
Issue Dt:
05/21/2002
Application #:
09691224
Filing Dt:
10/19/2000
Title:
METAL GATE WITH PVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
58
Patent #:
6589866
Issue Dt:
07/08/2003
Application #:
09691226
Filing Dt:
10/19/2000
Title:
METAL GATE WITH PVD AMORPHOUS SILICON LAYER HAVING IMPLANTED DOPANTS FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
59
Patent #:
6642590
Issue Dt:
11/04/2003
Application #:
09691227
Filing Dt:
10/19/2000
Title:
METAL GATE WITH PVD AMORPHOUS SILICON LAYER AND BARRIER LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
60
Patent #:
6297107
Issue Dt:
10/02/2001
Application #:
09691228
Filing Dt:
10/19/2000
Title:
High dielectric constant materials as gate dielectrics
61
Patent #:
7163864
Issue Dt:
01/16/2007
Application #:
09691353
Filing Dt:
10/18/2000
Title:
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
62
Patent #:
6735664
Issue Dt:
05/11/2004
Application #:
09691377
Filing Dt:
10/18/2000
Title:
INDIRECT ADDRESSING METHOD AND DEVICE INCORPORATING THE SAME
63
Patent #:
6504204
Issue Dt:
01/07/2003
Application #:
09693047
Filing Dt:
10/21/2000
Title:
COMPACT DUAL-PORT DRAM ARCHITECTURE SYSTEM AND METHOD FOR MAKING SAME
64
Patent #:
6620639
Issue Dt:
09/16/2003
Application #:
09693292
Filing Dt:
10/19/2000
Title:
APPARATUS TO EVALUATE HOT CARRIER INJECTION PERFORMANCE DEGRADATION AND METHOD THEREFOR
65
Patent #:
6452875
Issue Dt:
09/17/2002
Application #:
09693815
Filing Dt:
10/23/2000
Title:
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY BY SETTING AUDIO CLIP LEVELS FOR FREQUENCY RANGES OF INTEREST IN THE MEDIA
66
Patent #:
6377519
Issue Dt:
04/23/2002
Application #:
09693926
Filing Dt:
10/23/2000
Title:
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY FOR ANALYZING
67
Patent #:
6414914
Issue Dt:
07/02/2002
Application #:
09693966
Filing Dt:
10/23/2000
Title:
MULTIMEDIA SEARCH AND INDEXING FOR AUTOMATIC SELECTION OF SCENES AND/OR SOUNDS RECORDED IN A MEDIA FOR REPLAY USING AUDIO CUES
68
Patent #:
6304999
Issue Dt:
10/16/2001
Application #:
09694139
Filing Dt:
10/23/2000
Title:
Method and apparatus for embedded process control framework in tool systems
69
Patent #:
6333253
Issue Dt:
12/25/2001
Application #:
09696049
Filing Dt:
10/26/2000
Title:
Pattern-block flux deposition
70
Patent #:
6442093
Issue Dt:
08/27/2002
Application #:
09696054
Filing Dt:
10/25/2000
Title:
CASCODE BARREL READ
71
Patent #:
6452240
Issue Dt:
09/17/2002
Application #:
09699651
Filing Dt:
10/30/2000
Title:
INCREASED DAMPING OF MAGNETIZATION IN MAGNETIC MATERIALS
72
Patent #:
6448176
Issue Dt:
09/10/2002
Application #:
09699900
Filing Dt:
10/30/2000
Title:
DUAL DAMASCENE PROCESSING FOR SEMICONDUCTOR CHIP INTERCONNECTS
73
Patent #:
6612028
Issue Dt:
09/02/2003
Application #:
09699977
Filing Dt:
10/30/2000
Title:
A METHOD FOR MANUFACTURING A BUILT-UP CIRCUIT BOARD
74
Patent #:
6360317
Issue Dt:
03/19/2002
Application #:
09702220
Filing Dt:
10/30/2000
Title:
PREDECODING MULTIPLE INSTRUCTIONS AS ONE COMBINED INSTRUCTION AND DETECTING BRANCH TO ONE OF THE INSTRUCTIONS
75
Patent #:
6498056
Issue Dt:
12/24/2002
Application #:
09702406
Filing Dt:
10/31/2000
Title:
APPARATUS AND METHOD FOR ANTIFUSE WITH ELECTROSTATIC ASSIST
76
Patent #:
6600224
Issue Dt:
07/29/2003
Application #:
09703062
Filing Dt:
10/31/2000
Title:
THIN FILM ATTACHMENT TO LAMINATE USING A DENDRITIC INTERCONNECTION
77
Patent #:
6440640
Issue Dt:
08/27/2002
Application #:
09703092
Filing Dt:
10/31/2000
Title:
THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
78
Patent #:
6380038
Issue Dt:
04/30/2002
Application #:
09703512
Filing Dt:
10/30/2000
Title:
TRANSISTOR WITH ELECTRICALLY INDUCED SOURCE/DRAIN EXTENSIONS
79
Patent #:
6383947
Issue Dt:
05/07/2002
Application #:
09703513
Filing Dt:
10/31/2000
Title:
Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies
80
Patent #:
6417566
Issue Dt:
07/09/2002
Application #:
09705121
Filing Dt:
11/01/2000
Title:
VOID ELIMINATING SEED LAYER AND CONDUCTOR CORE INTEGRATED CIRCUIT INTERCONNECTS
81
Patent #:
6261894
Issue Dt:
07/17/2001
Application #:
09706492
Filing Dt:
11/03/2000
Title:
Method for forming dual workfunction high-performance support mosfets in EDRAM arrays
82
Patent #:
6544885
Issue Dt:
04/08/2003
Application #:
09706498
Filing Dt:
11/03/2000
Title:
POLISHED HARD MASK PROCESS FOR CONDUCTOR LAYER PATTERNING
83
Patent #:
6593210
Issue Dt:
07/15/2003
Application #:
09707214
Filing Dt:
11/06/2000
Title:
SELF-ALIGNED/MASKLESS REVERSE ETCH PROCESS USING AN INORGANIC FILM
84
Patent #:
6274289
Issue Dt:
08/14/2001
Application #:
09708104
Filing Dt:
11/03/2000
Title:
Chemical resist thickness reduction process
85
Patent #:
6549450
Issue Dt:
04/15/2003
Application #:
09708142
Filing Dt:
11/08/2000
Title:
METHOD AND SYSTEM FOR IMPROVING THE PERFORMANCE ON SOI MEMORY ARRAYS IN AN SRAM ARCHITECTURE SYSTEM
86
Patent #:
6457117
Issue Dt:
09/24/2002
Application #:
09708216
Filing Dt:
11/07/2000
Title:
PROCESSOR CONFIGURED TO PREDECODE RELATIVE CONTROL TRANSFER INSTRUCTIONS AND REPLACE DISPLACEMENTS THEREIN WITH A TARGET ADDRESS
87
Patent #:
6985988
Issue Dt:
01/10/2006
Application #:
09708494
Filing Dt:
11/09/2000
Title:
SYSTEM-ON-A-CHIP STRUCTURE HAVING A MULTIPLE CHANNEL BUS BRIDGE
88
Patent #:
6396108
Issue Dt:
05/28/2002
Application #:
09711328
Filing Dt:
11/13/2000
Title:
Self-aligned double gate silicon-on-insulator (SOI) device
89
Patent #:
6429052
Issue Dt:
08/06/2002
Application #:
09711401
Filing Dt:
11/13/2000
Title:
METHOD OF MAKING HIGH PERFORMANCE TRANSISTOR WITH A REDUCED WIDTH GATE ELECTRODE AND DEVICE COMPRISING SAME
90
Patent #:
6479866
Issue Dt:
11/12/2002
Application #:
09712320
Filing Dt:
11/14/2000
Title:
SOI DEVICE WITH SELF-ALIGNED SELECTIVE DAMAGE IMPLANT, AND METHOD
91
Patent #:
6730984
Issue Dt:
05/04/2004
Application #:
09712391
Filing Dt:
11/14/2000
Title:
INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION
92
Patent #:
6553390
Issue Dt:
04/22/2003
Application #:
09712646
Filing Dt:
11/14/2000
Title:
METHOD AND APPARATUS FOR SIMULTANEOUS ONLINE ACCESS OF VOLUME-MANAGED DATA STORAGE
93
Patent #:
6376320
Issue Dt:
04/23/2002
Application #:
09712995
Filing Dt:
11/15/2000
Title:
METHOD FOR FORMING FIELD EFFECT TRANSISTOR WITH SILICIDES OF DIFFERENT THICKNESS AND OF DIFFERENT MATERIALS FOR THE SOURCE/DRAIN AND THE GATE
94
Patent #:
6548395
Issue Dt:
04/15/2003
Application #:
09713313
Filing Dt:
11/16/2000
Title:
METHOD OF PROMOTING VOID FREE COPPER INTERCONNECTS
95
Patent #:
6891235
Issue Dt:
05/10/2005
Application #:
09713830
Filing Dt:
11/15/2000
Title:
FET WITH T-SHAPED GATE
96
Patent #:
6988241
Issue Dt:
01/17/2006
Application #:
09714024
Filing Dt:
11/15/2000
Title:
CLIENT SIDE, WEB-BASED SPREADSHEET
97
Patent #:
6816385
Issue Dt:
11/09/2004
Application #:
09714373
Filing Dt:
11/16/2000
Title:
COMPLIANT LAMINATE CONNECTOR
98
Patent #:
6399496
Issue Dt:
06/04/2002
Application #:
09714504
Filing Dt:
11/16/2000
Title:
COPPER INTERCONNECTION STRUCTURE INCORPORATING A METAL SEED LAYER
99
Patent #:
6712681
Issue Dt:
03/30/2004
Application #:
09715184
Filing Dt:
11/20/2000
Title:
POLISHING PADS WITH POLYMER FILLED FIBROUS WEB, AND METHODS FOR FABRICATING AND USING SAME
100
Patent #:
6577011
Issue Dt:
06/10/2003
Application #:
09715559
Filing Dt:
11/17/2000
Title:
CHIP INTERCONNECT WIRING STRUCTURE WITH LOW DIELECTRIC CONSTANT INSULATOR AND METHODS FOR FABRICATING THE SAME
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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