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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 119 of 146
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Patent #:	9466701	Issue Dt:	10/11/2016	Application #:	14244261	Filing Dt:	04/03/2014
Publication #:	US20150287795	Pub Dt:	10/08/2015
Title:	PROCESSES FOR PREPARING INTEGRATED CIRCUITS WITH IMPROVED SOURCE/DRAIN CONTACT STRUCTURES AND INTEGRATED CIRCUITS PREPARED ACCORDING TO SUCH PROCESSES

Patent #:	9040403	Issue Dt:	05/26/2015	Application #:	14244611	Filing Dt:	04/03/2014
Publication #:	US20140220759	Pub Dt:	08/07/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS

Patent #:	9312189	Issue Dt:	04/12/2016	Application #:	14244651	Filing Dt:	04/03/2014
Publication #:	US20150287646	Pub Dt:	10/08/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES

Patent #:	9401362	Issue Dt:	07/26/2016	Application #:	14245656	Filing Dt:	04/04/2014
Publication #:	US20150287725	Pub Dt:	10/08/2015
Title:	MULTIPLE THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE

Patent #:	9582629	Issue Dt:	02/28/2017	Application #:	14245868	Filing Dt:	04/04/2014
Publication #:	US20150286764	Pub Dt:	10/08/2015
Title:	METHODS OF GENERATING CIRCUIT LAYOUTS USING SELF-ALLIGNED DOUBLE PATTERNING (SADP) TECHNIQUES

Patent #:	9352286	Issue Dt:	05/31/2016	Application #:	14246041	Filing Dt:	04/05/2014
Publication #:	US20140217014	Pub Dt:	08/07/2014
Title:	COMPOSITE FILTRATION MEMBRANES AND METHODS OF PREPARATION THEREOF

Patent #:	9472455	Issue Dt:	10/18/2016	Application #:	14246197	Filing Dt:	04/07/2014
Publication #:	US20150287604	Pub Dt:	10/08/2015
Title:	METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER

Patent #:	9804231	Issue Dt:	10/31/2017	Application #:	14246376	Filing Dt:	04/07/2014
Publication #:	US20140316725	Pub Dt:	10/23/2014
Title:	POWER NOISE HISTOGRAM OF A COMPUTER SYSTEM

Patent #:	9202751	Issue Dt:	12/01/2015	Application #:	14246476	Filing Dt:	04/07/2014
Publication #:	US20150287636	Pub Dt:	10/08/2015
Title:	TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

Patent #:	9087952	Issue Dt:	07/21/2015	Application #:	14246546	Filing Dt:	04/07/2014
Publication #:	US20140217485	Pub Dt:	08/07/2014
Title:	STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS

Patent #:	9620589	Issue Dt:	04/11/2017	Application #:	14246983	Filing Dt:	04/07/2014
Publication #:	US20150287782	Pub Dt:	10/08/2015
Title:	INTEGRATED CIRCUITS AND METHODS OF FABRICATION THEREOF

Patent #:	9190375	Issue Dt:	11/17/2015	Application #:	14248373	Filing Dt:	04/09/2014
Publication #:	US20150294948	Pub Dt:	10/15/2015
Title:	SOLDER BUMP REFLOW BY INDUCTION HEATING

Patent #:	9679161	Issue Dt:	06/13/2017	Application #:	14248814	Filing Dt:	04/09/2014
Publication #:	US20140325212	Pub Dt:	10/30/2014
Title:	DISTRIBUTION OF ENCRYPTED INFORMATION IN MULTIPLE LOCATIONS

Patent #:	8918494	Issue Dt:	12/23/2014	Application #:	14249615	Filing Dt:	04/10/2014
Publication #:	US20140218398	Pub Dt:	08/07/2014
Title:	SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY

Patent #:	9219665	Issue Dt:	12/22/2015	Application #:	14249619	Filing Dt:	04/10/2014
Publication #:	US20140218399	Pub Dt:	08/07/2014
Title:	SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY

Patent #:	9092591	Issue Dt:	07/28/2015	Application #:	14249765	Filing Dt:	04/10/2014
Publication #:	US20140223397	Pub Dt:	08/07/2014
Title:	Automatic Generation of Wire Tag Lists for a Metal Stack

Patent #:	8929015	Issue Dt:	01/06/2015	Application #:	14249893	Filing Dt:	04/10/2014
Publication #:	US20140313609	Pub Dt:	10/23/2014
Title:	DATA WRITING METHOD AND PROGRAM FOR TAPE DRIVE

Patent #:	9184169	Issue Dt:	11/10/2015	Application #:	14250064	Filing Dt:	04/10/2014
Publication #:	US20150294976	Pub Dt:	10/15/2015
Title:	METHODS OF FORMING FINFET DEVICES IN DIFFERENT REGIONS OF AN INTEGRATED CIRCUIT PRODUCT

Patent #:	9392731	Issue Dt:	07/12/2016	Application #:	14250425	Filing Dt:	04/11/2014
Publication #:	US20150136365	Pub Dt:	05/21/2015
Title:	COOLING APPARATUS WITH DYNAMIC LOAD ADJUSTMENT

Patent #:	9093478	Issue Dt:	07/28/2015	Application #:	14250725	Filing Dt:	04/11/2014
Title:	INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET AND METHODS OF FORMING

Patent #:	9087553	Issue Dt:	07/21/2015	Application #:	14250727	Filing Dt:	04/11/2014
Publication #:	US20140320993	Pub Dt:	10/30/2014
Title:	TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR

Patent #:	9219696	Issue Dt:	12/22/2015	Application #:	14251386	Filing Dt:	04/11/2014
Publication #:	US20150036692	Pub Dt:	02/05/2015
Title:	INCREASED EFFICIENCY OF DATA PAYLOADS TO DATA ARRAYS ACCESSED THROUGH REGISTERS IN A DISTRIBUTED VIRTUAL BRIDGE

Patent #:	9508618	Issue Dt:	11/29/2016	Application #:	14251402	Filing Dt:	04/11/2014
Publication #:	US20150294918	Pub Dt:	10/15/2015
Title:	STAGGERED ELECTRICAL FRAME STRUCTURES FOR FRAME AREA REDUCTION

Patent #:	9368342	Issue Dt:	06/14/2016	Application #:	14252447	Filing Dt:	04/14/2014
Publication #:	US20150295047	Pub Dt:	10/15/2015
Title:	DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH

Patent #:	9389874	Issue Dt:	07/12/2016	Application #:	14253852	Filing Dt:	04/15/2014
Publication #:	US20150106612	Pub Dt:	04/16/2015
Title:	APPARATUS AND METHODS FOR AUTOMATICALLY REFLECTING CHANGES TO A COMPUTING SOLUTION IN AN IMAGE FOR THE COMPUTING SOLUTION

Patent #:	9196475	Issue Dt:	11/24/2015	Application #:	14253906	Filing Dt:	04/16/2014
Publication #:	US20150303057	Pub Dt:	10/22/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION

Patent #:	9196684	Issue Dt:	11/24/2015	Application #:	14254710	Filing Dt:	04/16/2014
Publication #:	US20150303261	Pub Dt:	10/22/2015
Title:	TENSILE NITRIDE PROFILE SHAPER ETCH TO PROVIDE VOID FREE GAPFILL

Patent #:	9299775	Issue Dt:	03/29/2016	Application #:	14254866	Filing Dt:	04/16/2014
Publication #:	US20150303249	Pub Dt:	10/22/2015
Title:	METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES

Patent #:	9564505	Issue Dt:	02/07/2017	Application #:	14254939	Filing Dt:	04/17/2014
Publication #:	US20140225199	Pub Dt:	08/14/2014
Title:	CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION

Patent #:	8999846	Issue Dt:	04/07/2015	Application #:	14255037	Filing Dt:	04/17/2014
Publication #:	US20140227874	Pub Dt:	08/14/2014
Title:	ELONGATED VIA STRUCTURES

Patent #:	8889542	Issue Dt:	11/18/2014	Application #:	14255067	Filing Dt:	04/17/2014
Publication #:	US20140227870	Pub Dt:	08/14/2014
Title:	METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA

Patent #:	9489282	Issue Dt:	11/08/2016	Application #:	14255497	Filing Dt:	04/17/2014
Publication #:	US20140359375	Pub Dt:	12/04/2014
Title:	SELECTIVE PURGING OF A LOG STRUCTURE

Patent #:	9240406	Issue Dt:	01/19/2016	Application #:	14257143	Filing Dt:	04/21/2014
Publication #:	US20150303191	Pub Dt:	10/22/2015
Title:	PRECISION TRENCH CAPACITOR

Patent #:	9461850	Issue Dt:	10/04/2016	Application #:	14257236	Filing Dt:	04/21/2014
Publication #:	US20140321582	Pub Dt:	10/30/2014
Title:	PARALLEL DATA PROCESSING

Patent #:	9337334	Issue Dt:	05/10/2016	Application #:	14257395	Filing Dt:	04/21/2014
Publication #:	US20150303313	Pub Dt:	10/22/2015
Title:	SEMICONDUCTOR MEMORY DEVICE EMPLOYING A FERROMAGNETIC GATE

Patent #:	9466868	Issue Dt:	10/11/2016	Application #:	14257464	Filing Dt:	04/21/2014
Publication #:	US20150303548	Pub Dt:	10/22/2015
Title:	RECONFIGURABLE BRANCH LINE COUPLER

Patent #:	8932949	Issue Dt:	01/13/2015	Application #:	14258063	Filing Dt:	04/22/2014
Publication #:	US20140217504	Pub Dt:	08/07/2014
Title:	FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	14258279	Filing Dt:	04/22/2014
Publication #:	US20150303295	Pub Dt:	10/22/2015
Title:	SELF-ALIGNED CONTACT OPENINGS OVER FINS OF A SEMICONDUCTOR DEVICE

Patent #:	9224842	Issue Dt:	12/29/2015	Application #:	14258488	Filing Dt:	04/22/2014
Publication #:	US20150303273	Pub Dt:	10/22/2015
Title:	PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER

Patent #:	9236269	Issue Dt:	01/12/2016	Application #:	14259179	Filing Dt:	04/23/2014
Publication #:	US20150311085	Pub Dt:	10/29/2015
Title:	FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH A PLANAR BLOCK AREA TO ENABLE VARIALBLE FIN PITCH AND WIDTH

Patent #:	9159567	Issue Dt:	10/13/2015	Application #:	14259497	Filing Dt:	04/23/2014
Publication #:	US20150311083	Pub Dt:	10/29/2015
Title:	REPLACEMENT LOW-K SPACER

Patent #:	9236258	Issue Dt:	01/12/2016	Application #:	14259694	Filing Dt:	04/23/2014
Publication #:	US20150311081	Pub Dt:	10/29/2015
Title:	METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES

Patent #:	9419082	Issue Dt:	08/16/2016	Application #:	14259726	Filing Dt:	04/23/2014
Publication #:	US20150311293	Pub Dt:	10/29/2015
Title:	SOURCE/DRAIN PROFILE ENGINEERING FOR ENHANCED P-MOSFET

Patent #:	9177928	Issue Dt:	11/03/2015	Application #:	14260399	Filing Dt:	04/24/2014
Publication #:	US20150311170	Pub Dt:	10/29/2015
Title:	CONTACT AND SOLDER BALL INTERCONNECT

Patent #:	9196696	Issue Dt:	11/24/2015	Application #:	14260913	Filing Dt:	04/24/2014
Publication #:	US20140231920	Pub Dt:	08/21/2014
Title:	INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME

Patent #:	9530770	Issue Dt:	12/27/2016	Application #:	14261021	Filing Dt:	04/24/2014
Publication #:	US20150311272	Pub Dt:	10/29/2015
Title:	INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM GATE METAL AND METHODS FOR FABRICATING SAME

Patent #:	9263541	Issue Dt:	02/16/2016	Application #:	14261559	Filing Dt:	04/25/2014
Publication #:	US20150311308	Pub Dt:	10/29/2015
Title:	ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS

Patent #:	9311442	Issue Dt:	04/12/2016	Application #:	14261632	Filing Dt:	04/25/2014
Publication #:	US20150310155	Pub Dt:	10/29/2015
Title:	NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC)

Patent #:	9348216	Issue Dt:	05/24/2016	Application #:	14261687	Filing Dt:	04/25/2014
Publication #:	US20140234757	Pub Dt:	08/21/2014
Title:	TEST PAD STRUCTURE FOR REUSE OF INTERCONNECT LEVEL MASKS

Patent #:	9640625	Issue Dt:	05/02/2017	Application #:	14261823	Filing Dt:	04/25/2014
Publication #:	US20150311082	Pub Dt:	10/29/2015
Title:	SELF-ALIGNED GATE CONTACT FORMATION

Patent #:	9735057	Issue Dt:	08/15/2017	Application #:	14262882	Filing Dt:	04/28/2014
Publication #:	US20150311120	Pub Dt:	10/29/2015
Title:	FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS

Patent #:	9059204	Issue Dt:	06/16/2015	Application #:	14263067	Filing Dt:	04/28/2014
Publication #:	US20140234990	Pub Dt:	08/21/2014
Title:	Methodology and Apparatus for Tuning Driving Current of Semiconductor Transistors

Patent #:	9479179	Issue Dt:	10/25/2016	Application #:	14263329	Filing Dt:	04/28/2014
Publication #:	US20150309113	Pub Dt:	10/29/2015
Title:	MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY

Patent #:	9384318	Issue Dt:	07/05/2016	Application #:	14263340	Filing Dt:	04/28/2014
Publication #:	US20150310157	Pub Dt:	10/29/2015
Title:	MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION

Patent #:	8921172	Issue Dt:	12/30/2014	Application #:	14264125	Filing Dt:	04/29/2014
Publication #:	US20140235021	Pub Dt:	08/21/2014
Title:	JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE

Patent #:	9117822	Issue Dt:	08/25/2015	Application #:	14264163	Filing Dt:	04/29/2014
Title:	METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

Patent #:	9087860	Issue Dt:	07/21/2015	Application #:	14264179	Filing Dt:	04/29/2014
Title:	FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR WITH PUNCH-THROUGH STOP REGION

Patent #:	10700170	Issue Dt:	06/30/2020	Application #:	14264240	Filing Dt:	04/29/2014
Publication #:	US20150311199	Pub Dt:	10/29/2015
Title:	MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE

Patent #:	8941179	Issue Dt:	01/27/2015	Application #:	14265401	Filing Dt:	04/30/2014
Publication #:	US20140231918	Pub Dt:	08/21/2014
Title:	FINFETS AND FIN ISOLATION STRUCTURES

Patent #:	9324430	Issue Dt:	04/26/2016	Application #:	14265409	Filing Dt:	04/30/2014
Publication #:	US20150318043	Pub Dt:	11/05/2015
Title:	Method For Defining A Default State of a Charge Trap Based Memory Cell

Patent #:	9136321	Issue Dt:	09/15/2015	Application #:	14265410	Filing Dt:	04/30/2014
Title:	LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION

Patent #:	9385030	Issue Dt:	07/05/2016	Application #:	14265536	Filing Dt:	04/30/2014
Publication #:	US20150318204	Pub Dt:	11/05/2015
Title:	SPACER TO PREVENT SOURCE-DRAIN CONTACT ENCROACHMENT

Patent #:	9575040	Issue Dt:	02/21/2017	Application #:	14265623	Filing Dt:	04/30/2014
Publication #:	US20140230524	Pub Dt:	08/21/2014
Title:	METHODS AND APPARATUS FOR DETECTION OF GASEOUS CORROSIVE CONTAMINANTS

Patent #:	9104316	Issue Dt:	08/11/2015	Application #:	14266455	Filing Dt:	04/30/2014
Publication #:	US20140359380	Pub Dt:	12/04/2014
Title:	RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION

Patent #:	9123627	Issue Dt:	09/01/2015	Application #:	14267010	Filing Dt:	05/01/2014
Title:	METHODS OF FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY FOR A FINFET SEMICONDUCTOR DEVICE

Patent #:	9224605	Issue Dt:	12/29/2015	Application #:	14267154	Filing Dt:	05/01/2014
Publication #:	US20150318176	Pub Dt:	11/05/2015
Title:	FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY BY PERFORMING AN IMPLANTATION/ANNEAL DEFECT GENERATION PROCESS

Patent #:	9312388	Issue Dt:	04/12/2016	Application #:	14267216	Filing Dt:	05/01/2014
Publication #:	US20150318398	Pub Dt:	11/05/2015
Title:	METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL IN TRENCHES LOCATED ABOVE THE SOURCE AND DRAIN REGIONS OF A SEMICONDUCTOR DEVICE

Patent #:	9793358	Issue Dt:	10/17/2017	Application #:	14267541	Filing Dt:	05/01/2014
Publication #:	US20150318351	Pub Dt:	11/05/2015
Title:	Non-Planar Semiconductor Device with Multiple-Head Epitaxial Structure on Fin

Patent #:	9147748	Issue Dt:	09/29/2015	Application #:	14267555	Filing Dt:	05/01/2014
Title:	METHODS OF FORMING REPLACEMENT SPACER STRUCTURES ON SEMICONDUCTOR DEVICES

Patent #:	9275906	Issue Dt:	03/01/2016	Application #:	14267611	Filing Dt:	05/01/2014
Publication #:	US20150318217	Pub Dt:	11/05/2015
Title:	METHOD FOR INCREASING A SURFACE AREA OF EPITAXIAL STRUCTURES IN A MIXED N/P TYPE FIN SEMICONDUCTOR STRUCTURE BY FORMING MULTIPLE EPITAXIAL HEADS

Patent #:	9209038	Issue Dt:	12/08/2015	Application #:	14267959	Filing Dt:	05/02/2014
Publication #:	US20150318181	Pub Dt:	11/05/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING

Patent #:	9460814	Issue Dt:	10/04/2016	Application #:	14268277	Filing Dt:	05/02/2014
Publication #:	US20150318059	Pub Dt:	11/05/2015
Title:	MEMORY TESTER DESIGN FOR SOFT ERROR RATE (SER) FAILURE ANALYSIS

Patent #:	9263340	Issue Dt:	02/16/2016	Application #:	14268415	Filing Dt:	05/02/2014
Publication #:	US20150318215	Pub Dt:	11/05/2015
Title:	METHODS FOR REMOVING SELECTED FINS THAT ARE FORMED FOR FINFET SEMICONDUCTOR DEVICES

Patent #:	9064932	Issue Dt:	06/23/2015	Application #:	14268478	Filing Dt:	05/02/2014
Title:	METHODS OF FORMING GATE STRUCTURES BY A GATE-CUT-LAST PROCESS AND THE RESULTING STRUCTURES

Patent #:	9466491	Issue Dt:	10/11/2016	Application #:	14268579	Filing Dt:	05/02/2014
Publication #:	US20150318178	Pub Dt:	11/05/2015
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A SPACER ETCH BLOCK CAP AND THE RESULTING DEVICE

Patent #:	9087879	Issue Dt:	07/21/2015	Application #:	14268606	Filing Dt:	05/02/2014
Publication #:	US20150011023	Pub Dt:	01/08/2015
Title:	METHOD OF MAKING SEMICONDUCTOR DEVICE WITH DISTINCT MULTIPLE-PATTERNED CONDUCTIVE TRACKS ON A SAME LEVEL

Patent #:	10050118	Issue Dt:	08/14/2018	Application #:	14269566	Filing Dt:	05/05/2014
Publication #:	US20150318345	Pub Dt:	11/05/2015
Title:	SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING

Patent #:	9337310	Issue Dt:	05/10/2016	Application #:	14269599	Filing Dt:	05/05/2014
Publication #:	US20150318378	Pub Dt:	11/05/2015
Title:	LOW LEAKAGE, HIGH FREQUENCY DEVICES

Patent #:	9368395	Issue Dt:	06/14/2016	Application #:	14270660	Filing Dt:	05/06/2014
Title:	SELF-ALIGNED VIA AND AIR GAP

Patent #:	9472465	Issue Dt:	10/18/2016	Application #:	14270824	Filing Dt:	05/06/2014
Publication #:	US20150325681	Pub Dt:	11/12/2015
Title:	METHODS OF FABRICATING INTEGRATED CIRCUITS

Patent #:	9472572	Issue Dt:	10/18/2016	Application #:	14270833	Filing Dt:	05/06/2014
Publication #:	US20150325692	Pub Dt:	11/12/2015
Title:	FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE INCLUDING A SET OF MERGED FINS FORMED ADJACENT A SET OF UNMERGED FINS

Patent #:	9490189	Issue Dt:	11/08/2016	Application #:	14270941	Filing Dt:	05/06/2014
Publication #:	US20140238045	Pub Dt:	08/28/2014
Title:	SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT

Patent #:	9252203	Issue Dt:	02/02/2016	Application #:	14271515	Filing Dt:	05/07/2014
Publication #:	US20150325635	Pub Dt:	11/12/2015
Title:	METAL-INSULATOR-METAL BACK END OF LINE CAPACITOR STRUCTURES

Patent #:	9076645	Issue Dt:	07/07/2015	Application #:	14272554	Filing Dt:	05/08/2014
Title:	METHOD OF FABRICATING AN INTERLAYER STRUCTURE OF INCREASED ELASTICITY MODULUS

Patent #:	9385026	Issue Dt:	07/05/2016	Application #:	14272691	Filing Dt:	05/08/2014
Publication #:	US20150325470	Pub Dt:	11/12/2015
Title:	Sublithographic Kelvin Structure Patterned With DSA

Patent #:	9177858	Issue Dt:	11/03/2015	Application #:	14272787	Filing Dt:	05/08/2014
Publication #:	US20150325467	Pub Dt:	11/12/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES

Patent #:	9299745	Issue Dt:	03/29/2016	Application #:	14272916	Filing Dt:	05/08/2014
Publication #:	US20150325622	Pub Dt:	11/12/2015
Title:	INTEGRATED CIRCUITS HAVING MAGNETIC TUNNEL JUNCTIONS (MTJ) AND METHODS FOR FABRICATING THE SAME

Patent #:	9490129	Issue Dt:	11/08/2016	Application #:	14272952	Filing Dt:	05/08/2014
Publication #:	US20150325482	Pub Dt:	11/12/2015
Title:	INTEGRATED CIRCUITS HAVING IMPROVED GATE STRUCTURES AND METHODS FOR FABRICATING SAME

Patent #:	9097765	Issue Dt:	08/04/2015	Application #:	14273247	Filing Dt:	05/08/2014
Title:	PERFORMANCE SCREEN RING OSCILLATOR FORMED FROM MULTI-DIMENSIONAL PAIRINGS OF SCAN CHAINS

Patent #:	9035465	Issue Dt:	05/19/2015	Application #:	14273975	Filing Dt:	05/09/2014
Publication #:	US20140332929	Pub Dt:	11/13/2014
Title:	FORMING SEMICONDUCTOR CHIP CONNECTIONS

Patent #:	9390884	Issue Dt:	07/12/2016	Application #:	14274042	Filing Dt:	05/09/2014
Publication #:	US20150325406	Pub Dt:	11/12/2015
Title:	METHOD OF INSPECTING A SEMICONDUCTOR SUBSTRATE

Patent #:	9293324	Issue Dt:	03/22/2016	Application #:	14274406	Filing Dt:	05/09/2014
Publication #:	US20150325436	Pub Dt:	11/12/2015
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN

Patent #:	9059177	Issue Dt:	06/16/2015	Application #:	14274962	Filing Dt:	05/12/2014
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Title:	DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING

Patent #:	9224638	Issue Dt:	12/29/2015	Application #:	14275448	Filing Dt:	05/12/2014
Publication #:	US20150325473	Pub Dt:	11/12/2015
Title:	INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS

Patent #:	9005882	Issue Dt:	04/14/2015	Application #:	14275688	Filing Dt:	05/12/2014
Publication #:	US20140247438	Pub Dt:	09/04/2014
Title:	RETICLE DEFECT CORRECTION BY SECOND EXPOSURE

Patent #:	9405468	Issue Dt:	08/02/2016	Application #:	14276025	Filing Dt:	05/13/2014
Publication #:	US20150332736	Pub Dt:	11/19/2015
Title:	Stacked Memory Device Control

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Publication #:	US20140326698	Pub Dt:	11/06/2014
Title:	INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME

Patent #:	9274277	Issue Dt:	03/01/2016	Application #:	14278689	Filing Dt:	05/15/2014
Publication #:	US20150331183	Pub Dt:	11/19/2015
Title:	WAVEGUIDE DEVICES WITH SUPPORTING ANCHORS

Patent #:	9158885	Issue Dt:	10/13/2015	Application #:	14278974	Filing Dt:	05/15/2014
Title:	REDUCING COLOR CONFLICTS IN TRIPLE PATTERNING LITHOGRAPHY

100

Patent #:	9490174	Issue Dt:	11/08/2016	Application #:	14279480	Filing Dt:	05/16/2014
Publication #:	US20150332972	Pub Dt:	11/19/2015
Title:	FABRICATING RAISED FINS USING ANCILLARY FIN STRUCTURES

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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