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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 121 of 146
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Patent #:	9355042	Issue Dt:	05/31/2016	Application #:	14306790	Filing Dt:	06/17/2014
Publication #:	US20140379956	Pub Dt:	12/25/2014
Title:	MANAGING A TRANSLATION LOOKASIDE BUFFER

Patent #:	9142640	Issue Dt:	09/22/2015	Application #:	14306864	Filing Dt:	06/17/2014
Title:	CONTAINMENT STRUCTURE FOR EPITAXIAL GROWTH IN NON-PLANAR SEMICONDUCTOR STRUCTURE

Patent #:	9230822	Issue Dt:	01/05/2016	Application #:	14306920	Filing Dt:	06/17/2014
Publication #:	US20150364336	Pub Dt:	12/17/2015
Title:	UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9660057	Issue Dt:	05/23/2017	Application #:	14307011	Filing Dt:	06/17/2014
Publication #:	US20150364578	Pub Dt:	12/17/2015
Title:	METHOD OF FORMING A REDUCED RESISTANCE FIN STRUCTURE

Patent #:	9530833	Issue Dt:	12/27/2016	Application #:	14307078	Filing Dt:	06/17/2014
Publication #:	US20150364535	Pub Dt:	12/17/2015
Title:	SEMICONDUCTOR STRUCTURE INCLUDING CAPACITORS HAVING DIFFERENT CAPACITOR DIELECTRICS AND METHOD FOR THE FORMATION THEREOF

Patent #:	9508826	Issue Dt:	11/29/2016	Application #:	14307575	Filing Dt:	06/18/2014
Publication #:	US20150372112	Pub Dt:	12/24/2015
Title:	REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY

Patent #:	9484246	Issue Dt:	11/01/2016	Application #:	14307604	Filing Dt:	06/18/2014
Publication #:	US20150371893	Pub Dt:	12/24/2015
Title:	BURIED SIGNAL TRANSMISSION LINE

Patent #:	9472446	Issue Dt:	10/18/2016	Application #:	14307902	Filing Dt:	06/18/2014
Publication #:	US20150371892	Pub Dt:	12/24/2015
Title:	METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH A UNIQUE GATE CONFIGURATION, AND THE RESULTING FINFET DEVICE

Patent #:	9391200	Issue Dt:	07/12/2016	Application #:	14308045	Filing Dt:	06/18/2014
Publication #:	US20150372140	Pub Dt:	12/24/2015
Title:	FINFETS HAVING STRAINED CHANNELS, AND METHODS OF FABRICATING FINFETS HAVING STRAINED CHANNELS

Patent #:	9390017	Issue Dt:	07/12/2016	Application #:	14308100	Filing Dt:	06/18/2014
Publication #:	US20150149716	Pub Dt:	05/28/2015
Title:	WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES

Patent #:	9490340	Issue Dt:	11/08/2016	Application #:	14308138	Filing Dt:	06/18/2014
Publication #:	US20150372115	Pub Dt:	12/24/2015
Title:	METHODS OF FORMING NANOWIRE DEVICES WITH DOPED EXTENSION REGIONS AND THE RESULTING DEVICES

Patent #:	9431512	Issue Dt:	08/30/2016	Application #:	14308257	Filing Dt:	06/18/2014
Publication #:	US20150372111	Pub Dt:	12/24/2015
Title:	METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES

Patent #:	9026981	Issue Dt:	05/05/2015	Application #:	14308835	Filing Dt:	06/19/2014
Publication #:	US20140351785	Pub Dt:	11/27/2014
Title:	DIELECTRIC RELIABILITY ASSESSMENT FOR ADVANCED SEMICONDUCTORS

Patent #:	9941388	Issue Dt:	04/10/2018	Application #:	14309096	Filing Dt:	06/19/2014
Publication #:	US20150372108	Pub Dt:	12/24/2015
Title:	METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH

Patent #:	9018675	Issue Dt:	04/28/2015	Application #:	14309917	Filing Dt:	06/20/2014
Publication #:	US20140299181	Pub Dt:	10/09/2014
Title:	HETEROJUNCTION III-V PHOTOVOLTAIC CELL FABRICATION

Patent #:	9391140	Issue Dt:	07/12/2016	Application #:	14309956	Filing Dt:	06/20/2014
Publication #:	US20150372084	Pub Dt:	12/24/2015
Title:	RAISED FIN STRUCTURES AND METHODS OF FABRICATION

Patent #:	9519307	Issue Dt:	12/13/2016	Application #:	14310097	Filing Dt:	06/20/2014
Publication #:	US20140380084	Pub Dt:	12/25/2014
Title:	Detecting Full-System Idle State In Adaptive-Tick Kernels

Patent #:	9263327	Issue Dt:	02/16/2016	Application #:	14310314	Filing Dt:	06/20/2014
Publication #:	US20150371899	Pub Dt:	12/24/2015
Title:	MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES

Patent #:	9391119	Issue Dt:	07/12/2016	Application #:	14310460	Filing Dt:	06/20/2014
Publication #:	US20150372055	Pub Dt:	12/24/2015
Title:	NON-VOLATILE RANDOM ACCESS MEMORY DEVICES WITH SHARED TRANSISTOR CONFIGURATION AND METHODS OF FORMING THE SAME

Patent #:	9773237	Issue Dt:	09/26/2017	Application #:	14310470	Filing Dt:	06/20/2014
Publication #:	US20150149350	Pub Dt:	05/28/2015
Title:	SYNCHRONOUS SPLIT PAYMENT TRANSACTION MANAGEMENT

Patent #:	9551696	Issue Dt:	01/24/2017	Application #:	14311380	Filing Dt:	06/23/2014
Publication #:	US20150369789	Pub Dt:	12/24/2015
Title:	CLEANABILITY ASSESSMENT OF SUBLIMATE FROM LITHOGRAPHY MATERIALS

Patent #:	9613906	Issue Dt:	04/04/2017	Application #:	14311457	Filing Dt:	06/23/2014
Publication #:	US20150371898	Pub Dt:	12/24/2015
Title:	INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME

Patent #:	10343253	Issue Dt:	07/09/2019	Application #:	14311761	Filing Dt:	06/23/2014
Publication #:	US20150371912	Pub Dt:	12/24/2015
Title:	METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL PLANARIZATION ENDPOINT DETECTION USING AN ALTERNATING CURRENT REFERENCE SIGNAL

Patent #:	9006906	Issue Dt:	04/14/2015	Application #:	14312077	Filing Dt:	06/23/2014
Publication #:	US20140299929	Pub Dt:	10/09/2014
Title:	DRAM CELL BASED ON CONDUCTIVE NANOCHANNEL PLATE

Patent #:	9338001	Issue Dt:	05/10/2016	Application #:	14312085	Filing Dt:	06/23/2014
Publication #:	US20150101061	Pub Dt:	04/09/2015
Title:	PRIVACY ENHANCED SPATIAL ANALYTICS

Patent #:	9502518	Issue Dt:	11/22/2016	Application #:	14312418	Filing Dt:	06/23/2014
Publication #:	US20150372104	Pub Dt:	12/24/2015
Title:	MULTI-CHANNEL GATE-ALL-AROUND FET

Patent #:	9041079	Issue Dt:	05/26/2015	Application #:	14312467	Filing Dt:	06/23/2014
Title:	OPTICAL LATCH AND SYNAPTIC SWITCH

Patent #:	9530864	Issue Dt:	12/27/2016	Application #:	14314404	Filing Dt:	06/25/2014
Publication #:	US20150380514	Pub Dt:	12/31/2015
Title:	JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER

Patent #:	9299584	Issue Dt:	03/29/2016	Application #:	14314595	Filing Dt:	06/25/2014
Publication #:	US20150380269	Pub Dt:	12/31/2015
Title:	METHODS OF FORMING INTEGRATED CIRCUITS WITH A PLANARIZED PERMANET LAYER AND METHODS FOR FORMING FINFET DEVICES WITH A PLANARIZED PERMANENT LAYER

Patent #:	9779987	Issue Dt:	10/03/2017	Application #:	14314670	Filing Dt:	06/25/2014
Publication #:	US20150380304	Pub Dt:	12/31/2015
Title:	TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT

Patent #:	NONE	Issue Dt:		Application #:	14314693	Filing Dt:	06/25/2014
Publication #:	US20150377956	Pub Dt:	12/31/2015
Title:	METHOD AND APPARATUS FOR INLINE DEVICE CHARACTERIZATION AND TEMPERATURE PROFILING

Patent #:	9524986	Issue Dt:	12/20/2016	Application #:	14315362	Filing Dt:	06/26/2014
Publication #:	US20150380438	Pub Dt:	12/31/2015
Title:	TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER

Patent #:	9627480	Issue Dt:	04/18/2017	Application #:	14315385	Filing Dt:	06/26/2014
Publication #:	US20150380488	Pub Dt:	12/31/2015
Title:	JUNCTION BUTTING STRUCTURE USING NONUNIFORM TRENCH SHAPE

Patent #:	9735152	Issue Dt:	08/15/2017	Application #:	14315602	Filing Dt:	06/26/2014
Publication #:	US20150380404	Pub Dt:	12/31/2015
Title:	NON-PLANAR STRUCTURE WITH EXTENDED EXPOSED RAISED STRUCTURES AND SAME-LEVEL GATE AND SPACERS

Patent #:	9305832	Issue Dt:	04/05/2016	Application #:	14315659	Filing Dt:	06/26/2014
Publication #:	US20150380246	Pub Dt:	12/31/2015
Title:	DIMENSION-CONTROLLED VIA FORMATION PROCESSING

Patent #:	9349649	Issue Dt:	05/24/2016	Application #:	14315844	Filing Dt:	06/26/2014
Publication #:	US20150380489	Pub Dt:	12/31/2015
Title:	LOW RESISTANCE AND DEFECT FREE EPITAXIAL SEMICONDUCTOR MATERIAL FOR PROVIDING MERGED FINFETS

Patent #:	9209186	Issue Dt:	12/08/2015	Application #:	14315885	Filing Dt:	06/26/2014
Publication #:	US20150380409	Pub Dt:	12/31/2015
Title:	THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9397012	Issue Dt:	07/19/2016	Application #:	14316915	Filing Dt:	06/27/2014
Publication #:	US20150380320	Pub Dt:	12/31/2015
Title:	TEST PATTERN FOR FEATURE CROSS-SECTIONING

Patent #:	9508562	Issue Dt:	11/29/2016	Application #:	14316988	Filing Dt:	06/27/2014
Publication #:	US20150380252	Pub Dt:	12/31/2015
Title:	SIDEWALL IMAGE TEMPLATES FOR DIRECTED SELF-ASSEMBLY MATERIALS

Patent #:	9058441	Issue Dt:	06/16/2015	Application #:	14317013	Filing Dt:	06/27/2014
Publication #:	US20140310676	Pub Dt:	10/16/2014
Title:	METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION

Patent #:	9286969	Issue Dt:	03/15/2016	Application #:	14317806	Filing Dt:	06/27/2014
Publication #:	US20150380079	Pub Dt:	12/31/2015
Title:	LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY

Patent #:	9496257	Issue Dt:	11/15/2016	Application #:	14318822	Filing Dt:	06/30/2014
Publication #:	US20150380405	Pub Dt:	12/31/2015
Title:	REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS

Patent #:	9305785	Issue Dt:	04/05/2016	Application #:	14318901	Filing Dt:	06/30/2014
Publication #:	US20150380250	Pub Dt:	12/31/2015
Title:	SEMICONDUCTOR CONTACTS AND METHODS OF FABRICATION

Patent #:	9355481	Issue Dt:	05/31/2016	Application #:	14319303	Filing Dt:	06/30/2014
Publication #:	US20150145867	Pub Dt:	05/28/2015
Title:	DYNAMIC VISUALIZATION FOR OPTIMIZATION PROCESSES

Patent #:	9337306	Issue Dt:	05/10/2016	Application #:	14319462	Filing Dt:	06/30/2014
Publication #:	US20150380515	Pub Dt:	12/31/2015
Title:	MULTI-PHASE SOURCE/DRAIN/GATE SPACER-EPI FORMATION

Patent #:	9362176	Issue Dt:	06/07/2016	Application #:	14319640	Filing Dt:	06/30/2014
Publication #:	US20150380316	Pub Dt:	12/31/2015
Title:	UNIFORM EXPOSED RAISED STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9484427	Issue Dt:	11/01/2016	Application #:	14320831	Filing Dt:	07/01/2014
Publication #:	US20160005831	Pub Dt:	01/07/2016
Title:	FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS

Patent #:	9733831	Issue Dt:	08/15/2017	Application #:	14320841	Filing Dt:	07/01/2014
Publication #:	US20150006840	Pub Dt:	01/01/2015
Title:	GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES

Patent #:	NONE	Issue Dt:		Application #:	14320932	Filing Dt:	07/01/2014
Publication #:	US20160005868	Pub Dt:	01/07/2016
Title:	FINFET WITH CONFINED EPITAXY

Patent #:	9324822	Issue Dt:	04/26/2016	Application #:	14321679	Filing Dt:	07/01/2014
Publication #:	US20160005828	Pub Dt:	01/07/2016
Title:	GATE DIELECTRIC PROTECTION FOR TRANSISTORS

Patent #:	9099315	Issue Dt:	08/04/2015	Application #:	14321845	Filing Dt:	07/02/2014
Publication #:	US20150021777	Pub Dt:	01/22/2015
Title:	MOUNTING STRUCTURE AND MOUNTING STRUCTURE MANUFACTURING METHOD

Patent #:	9502232	Issue Dt:	11/22/2016	Application #:	14321866	Filing Dt:	07/02/2014
Publication #:	US20160005598	Pub Dt:	01/07/2016
Title:	INHIBITING DIFFUSION OF ELEMENTS BETWEEN MATERIAL LAYERS OF A LAYERED CIRCUIT STRUCTURE

Patent #:	9263555	Issue Dt:	02/16/2016	Application #:	14322987	Filing Dt:	07/03/2014
Publication #:	US20160005834	Pub Dt:	01/07/2016
Title:	METHODS OF FORMING A CHANNEL REGION FOR A SEMICONDUCTOR DEVICE BY PERFORMING A TRIPLE CLADDING PROCESS

Patent #:	9620384	Issue Dt:	04/11/2017	Application #:	14323036	Filing Dt:	07/03/2014
Publication #:	US20160005620	Pub Dt:	01/07/2016
Title:	CONTROL OF O-INGRESS INTO GATE STACK DIELECTRIC LAYER USING OXYGEN PERMEABLE LAYER

Patent #:	9461090	Issue Dt:	10/04/2016	Application #:	14323164	Filing Dt:	07/03/2014
Publication #:	US20160005775	Pub Dt:	01/07/2016
Title:	PHOTODETECTOR AND METHOD OF FORMING THE PHOTODETECTOR ON STACKED TRENCH ISOLATION REGIONS

Patent #:	9064748	Issue Dt:	06/23/2015	Application #:	14323212	Filing Dt:	07/03/2014
Publication #:	US20140312298	Pub Dt:	10/23/2014
Title:	Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same

Patent #:	9443723	Issue Dt:	09/13/2016	Application #:	14325500	Filing Dt:	07/08/2014
Publication #:	US20160013050	Pub Dt:	01/14/2016
Title:	INTEGRATED CIRCUITS WITH AN INSULTATING LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS

Patent #:	9372392	Issue Dt:	06/21/2016	Application #:	14325515	Filing Dt:	07/08/2014
Publication #:	US20140329173	Pub Dt:	11/06/2014
Title:	RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS

Patent #:	9368493	Issue Dt:	06/14/2016	Application #:	14325668	Filing Dt:	07/08/2014
Publication #:	US20160013184	Pub Dt:	01/14/2016
Title:	METHOD AND STRUCTURE TO SUPPRESS FINFET HEATING

Patent #:	9214463	Issue Dt:	12/15/2015	Application #:	14326623	Filing Dt:	07/09/2014
Publication #:	US20140319617	Pub Dt:	10/30/2014
Title:	METHODS OF FORMING METAL SILICIDE REGIONS ON A SEMICONDUCTOR DEVICE

Patent #:	9466659	Issue Dt:	10/11/2016	Application #:	14326659	Filing Dt:	07/09/2014
Publication #:	US20160013262	Pub Dt:	01/14/2016
Title:	FABRICATION OF MULTILAYER CIRCUIT ELEMENTS

Patent #:	9286459	Issue Dt:	03/15/2016	Application #:	14326761	Filing Dt:	07/09/2014
Publication #:	US20150082409	Pub Dt:	03/19/2015
Title:	AUTHORIZED REMOTE ACCESS TO AN OPERATING SYSTEM HOSTED BY A VIRTUAL MACHINE

Patent #:	9245965	Issue Dt:	01/26/2016	Application #:	14327598	Filing Dt:	07/10/2014
Publication #:	US20140319611	Pub Dt:	10/30/2014
Title:	UNIFORM FINFET GATE HEIGHT

Patent #:	9087880	Issue Dt:	07/21/2015	Application #:	14328760	Filing Dt:	07/11/2014
Publication #:	US20150035153	Pub Dt:	02/05/2015
Title:	REMOVING METAL FILLS IN A WIRING LAYER

Patent #:	9366723	Issue Dt:	06/14/2016	Application #:	14328788	Filing Dt:	07/11/2014
Publication #:	US20140325298	Pub Dt:	10/30/2014
Title:	TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION

Patent #:	9405934	Issue Dt:	08/02/2016	Application #:	14328906	Filing Dt:	07/11/2014
Publication #:	US20150026817	Pub Dt:	01/22/2015
Title:	Hiding Sensitive Data In Plain Text Environment

Patent #:	9240324	Issue Dt:	01/19/2016	Application #:	14328921	Filing Dt:	07/11/2014
Publication #:	US20140322907	Pub Dt:	10/30/2014
Title:	SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR

Patent #:	9171922	Issue Dt:	10/27/2015	Application #:	14329263	Filing Dt:	07/11/2014
Title:	COMBINATION FINFET/ULTRA-THIN BODY TRANSISTOR STRUCTURE AND METHODS OF MAKING SUCH STRUCTURES

Patent #:	9159630	Issue Dt:	10/13/2015	Application #:	14330063	Filing Dt:	07/14/2014
Title:	FIN FIELD-EFFECT TRANSISTOR (FINFET) DEVICE FORMED USING A SINGLE SPACER, DOUBLE HARDMASK SCHEME

Patent #:	9543167	Issue Dt:	01/10/2017	Application #:	14331267	Filing Dt:	07/15/2014
Publication #:	US20160020208	Pub Dt:	01/21/2016
Title:	FINFET SOURCE-DRAIN MERGED BY SILICIDE-BASED MATERIAL

Patent #:	9542354	Issue Dt:	01/10/2017	Application #:	14331276	Filing Dt:	07/15/2014
Publication #:	US20160019182	Pub Dt:	01/21/2016
Title:	GENERATING A PARALLEL DATA SIGNAL BY CONVERTING SERIAL DATA OF A SERIAL DATA SIGNAL TO PARALLEL DATA

Patent #:	NONE	Issue Dt:		Application #:	14332607	Filing Dt:	07/16/2014
Publication #:	US20150032418	Pub Dt:	01/29/2015
Title:	AGGREGATING AND FILTERING DATA FROM MOBILE DEVICES

Patent #:	9304335	Issue Dt:	04/05/2016	Application #:	14332886	Filing Dt:	07/16/2014
Publication #:	US20160018677	Pub Dt:	01/21/2016
Title:	INTEGRATED LDMOS DEVICES FOR SILICON PHOTONICS

Patent #:	9269815	Issue Dt:	02/23/2016	Application #:	14333135	Filing Dt:	07/16/2014
Publication #:	US20140327088	Pub Dt:	11/06/2014
Title:	FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE

Patent #:	9054127	Issue Dt:	06/09/2015	Application #:	14333555	Filing Dt:	07/17/2014
Publication #:	US20140327076	Pub Dt:	11/06/2014
Title:	ROBUST REPLACEMENT GATE INTEGRATION

Patent #:	8946015	Issue Dt:	02/03/2015	Application #:	14333715	Filing Dt:	07/17/2014
Publication #:	US20140363944	Pub Dt:	12/11/2014
Title:	AQUA REGIA AND HYDROGEN PEROXIDE HCL COMBINATION TO REMOVE NI AND NIPT RESIDUES

Patent #:	9240550	Issue Dt:	01/19/2016	Application #:	14333806	Filing Dt:	07/17/2014
Publication #:	US20150036413	Pub Dt:	02/05/2015
Title:	RESISTIVE MEMORY ELEMENT BASED ON OXYGEN-DOPED AMORPHOUS CARBON

Patent #:	9570679	Issue Dt:	02/14/2017	Application #:	14333841	Filing Dt:	07/17/2014
Publication #:	US20150060755	Pub Dt:	03/05/2015
Title:	NANODEVICE ASSEMBLIES

Patent #:	9583380	Issue Dt:	02/28/2017	Application #:	14334385	Filing Dt:	07/17/2014
Publication #:	US20160020140	Pub Dt:	01/21/2016
Title:	ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS

Patent #:	8941940	Issue Dt:	01/27/2015	Application #:	14334603	Filing Dt:	07/17/2014
Title:	UTILIZING STORED WRITE ENVIRONMENT CONDITIONS FOR READ ERROR RECOVERY

Patent #:	9368591	Issue Dt:	06/14/2016	Application #:	14334950	Filing Dt:	07/18/2014
Publication #:	US20160020335	Pub Dt:	01/21/2016
Title:	TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION

Patent #:	9076868	Issue Dt:	07/07/2015	Application #:	14334953	Filing Dt:	07/18/2014
Title:	SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY

Patent #:	9274959	Issue Dt:	03/01/2016	Application #:	14335230	Filing Dt:	07/18/2014
Publication #:	US20150032964	Pub Dt:	01/29/2015
Title:	HANDLING VIRTUAL MEMORY ADDRESS SYNONYMS IN A MULTI-LEVEL CACHE HIERARCHY STRUCTURE

Patent #:	9501850	Issue Dt:	11/22/2016	Application #:	14335486	Filing Dt:	07/18/2014
Publication #:	US20150049089	Pub Dt:	02/19/2015
Title:	DISPLAY TECHNIQUES FOR GRAPHS

Patent #:	9058987	Issue Dt:	06/16/2015	Application #:	14336407	Filing Dt:	07/21/2014
Publication #:	US20150037939	Pub Dt:	02/05/2015
Title:	RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN

Patent #:	9372226	Issue Dt:	06/21/2016	Application #:	14337290	Filing Dt:	07/22/2014
Publication #:	US20160025805	Pub Dt:	01/28/2016
Title:	WAFER TEST STRUCTURES AND METHODS OF PROVIDING WAFER TEST STRUCTURES

Patent #:	9105643	Issue Dt:	08/11/2015	Application #:	14337596	Filing Dt:	07/22/2014
Publication #:	US20140332967	Pub Dt:	11/13/2014
Title:	BIT CELL WITH DOUBLE PATTERENED METAL LAYER STRUCTURES

Patent #:	9059253	Issue Dt:	06/16/2015	Application #:	14337774	Filing Dt:	07/22/2014
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Title:	VERTICAL ELECTRONIC FUSE

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Title:	Message Reconciliation During Disaster Recovery

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100

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Title:	TECHNIQUES FOR MEDICAL IMAGE RETREIVAL

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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