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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 126 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
9425103
Issue Dt:
08/23/2016
Application #:
14560102
Filing Dt:
12/04/2014
Publication #:
US20160163601
Pub Dt:
06/09/2016
Title:
METHODS OF USING A METAL PROTECTION LAYER TO FORM REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
2
Patent #:
9660083
Issue Dt:
05/23/2017
Application #:
14560255
Filing Dt:
12/04/2014
Publication #:
US20160163850
Pub Dt:
06/09/2016
Title:
LDMOS FINFET DEVICE AND METHOD OF MANUFACTURE USING A TRENCH CONFINED EPITAXIAL GROWTH PROCESS
3
Patent #:
9362405
Issue Dt:
06/07/2016
Application #:
14560361
Filing Dt:
12/04/2014
Publication #:
US20160163863
Pub Dt:
06/09/2016
Title:
CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON A FINFET DEVICE
4
Patent #:
9645486
Issue Dt:
05/09/2017
Application #:
14560388
Filing Dt:
12/04/2014
Publication #:
US20160161840
Pub Dt:
06/09/2016
Title:
MULTIPLE THRESHOLD CONVERGENT OPC MODEL
5
Patent #:
9419139
Issue Dt:
08/16/2016
Application #:
14560428
Filing Dt:
12/04/2014
Publication #:
US20160163859
Pub Dt:
06/09/2016
Title:
NITRIDE LAYER PROTECTION BETWEEN PFET SOURCE/DRAIN REGIONS AND DUMMY GATE DURING SOURCE/DRAIN ETCH
6
Patent #:
9082852
Issue Dt:
07/14/2015
Application #:
14560472
Filing Dt:
12/04/2014
Title:
LDMOS FINFET DEVICE USING A LONG CHANNEL REGION AND METHOD OF MANUFACTURE
7
Patent #:
9482519
Issue Dt:
11/01/2016
Application #:
14560518
Filing Dt:
12/04/2014
Publication #:
US20160161248
Pub Dt:
06/09/2016
Title:
MEASURING SEMICONDUCTOR DEVICE FEATURES USING STEPWISE OPTICAL METROLOGY
8
Patent #:
9269628
Issue Dt:
02/23/2016
Application #:
14560557
Filing Dt:
12/04/2014
Title:
METHODS OF REMOVING PORTIONS OF AT LEAST ONE FIN STRUCTURE SO AS TO FORM ISOLATION REGIONS WHEN FORMING FINFET SEMICONDUCTOR DEVICES
9
Patent #:
9547232
Issue Dt:
01/17/2017
Application #:
14560688
Filing Dt:
12/04/2014
Publication #:
US20160161857
Pub Dt:
06/09/2016
Title:
PELLICLE WITH AEROGEL SUPPORT FRAME
10
Patent #:
9087528
Issue Dt:
07/21/2015
Application #:
14561134
Filing Dt:
12/04/2014
Publication #:
US20150092302
Pub Dt:
04/02/2015
Title:
METHODS FOR BIASING ELECTRICALLY BIASABLE STRUCTURES
11
Patent #:
9406616
Issue Dt:
08/02/2016
Application #:
14561359
Filing Dt:
12/05/2014
Publication #:
US20160163644
Pub Dt:
06/09/2016
Title:
MERGED SOURCE/DRAIN AND GATE CONTACTS IN SRAM BITCELL
12
Patent #:
9287264
Issue Dt:
03/15/2016
Application #:
14561395
Filing Dt:
12/05/2014
Title:
EPITAXIALLY GROWN SILICON GERMANIUM CHANNEL FINFET WITH SILICON UNDERLAYER
13
Patent #:
9595524
Issue Dt:
03/14/2017
Application #:
14561632
Filing Dt:
12/05/2014
Publication #:
US20160020209
Pub Dt:
01/21/2016
Title:
FINFET SOURCE-DRAIN MERGED BY SILICIDE-BASED MATERIAL
14
Patent #:
9383404
Issue Dt:
07/05/2016
Application #:
14561830
Filing Dt:
12/05/2014
Publication #:
US20160161545
Pub Dt:
06/09/2016
Title:
HIGH RESISTIVITY SUBSTRATE FINAL RESISTANCE TEST STRUCTURE
15
Patent #:
9443857
Issue Dt:
09/13/2016
Application #:
14561999
Filing Dt:
12/05/2014
Publication #:
US20160163712
Pub Dt:
06/09/2016
Title:
VERTICAL FIN EDRAM
16
Patent #:
9392679
Issue Dt:
07/12/2016
Application #:
14562570
Filing Dt:
12/05/2014
Publication #:
US20160165710
Pub Dt:
06/09/2016
Title:
METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER PROCESSING
17
Patent #:
9449887
Issue Dt:
09/20/2016
Application #:
14563009
Filing Dt:
12/08/2014
Publication #:
US20160163814
Pub Dt:
06/09/2016
Title:
METHOD OF FORMING REPLACEMENT GATE PFET HAVING TIALCO LAYER FOR IMPROVED NBTI PERFORMANCE
18
Patent #:
9496250
Issue Dt:
11/15/2016
Application #:
14563097
Filing Dt:
12/08/2014
Publication #:
US20160163685
Pub Dt:
06/09/2016
Title:
TUNABLE SCALING OF CURRENT GAIN IN BIPOLAR JUNCTION TRANSISTORS
19
Patent #:
9455926
Issue Dt:
09/27/2016
Application #:
14563152
Filing Dt:
12/08/2014
Publication #:
US20150092546
Pub Dt:
04/02/2015
Title:
QUEUE CREDIT MANAGEMENT
20
Patent #:
9141494
Issue Dt:
09/22/2015
Application #:
14563245
Filing Dt:
12/08/2014
Publication #:
US20150095700
Pub Dt:
04/02/2015
Title:
ISOLATING A PCI HOST BRIDGE IN RESPONSE TO AN ERROR EVENT
21
Patent #:
9378323
Issue Dt:
06/28/2016
Application #:
14563475
Filing Dt:
12/08/2014
Publication #:
US20160162621
Pub Dt:
06/09/2016
Title:
METHODS FOR RETARGETING VIAS AND FOR FABRICATING SEMICONDUCTOR DEVICES WITH RETARGETED VIAS
22
Patent #:
9472470
Issue Dt:
10/18/2016
Application #:
14564323
Filing Dt:
12/09/2014
Publication #:
US20160163826
Pub Dt:
06/09/2016
Title:
METHODS OF FORMING FINFET WITH WIDE UNMERGED SOURCE DRAIN EPI
23
Patent #:
9263344
Issue Dt:
02/16/2016
Application #:
14564603
Filing Dt:
12/09/2014
Publication #:
US20150147876
Pub Dt:
05/28/2015
Title:
LOW THRESHOLD VOLTAGE CMOS DEVICE
24
Patent #:
9490223
Issue Dt:
11/08/2016
Application #:
14566773
Filing Dt:
12/11/2014
Publication #:
US20160172314
Pub Dt:
06/16/2016
Title:
STRUCTURE TO PREVENT DEEP TRENCH MOAT CHARGING AND MOAT ISOLATION FAILS
25
Patent #:
9412759
Issue Dt:
08/09/2016
Application #:
14566779
Filing Dt:
12/11/2014
Publication #:
US20160172378
Pub Dt:
06/16/2016
Title:
CMOS GATE CONTACT RESISTANCE REDUCTION
26
Patent #:
10126395
Issue Dt:
11/13/2018
Application #:
14566939
Filing Dt:
12/11/2014
Publication #:
US20150168521
Pub Dt:
06/18/2015
Title:
MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGING METHOD
27
Patent #:
9293439
Issue Dt:
03/22/2016
Application #:
14567052
Filing Dt:
12/11/2014
Publication #:
US20150093859
Pub Dt:
04/02/2015
Title:
ELECTRONIC MODULE ASSEMBLY WITH PATTERNED ADHESIVE ARRAY
28
Patent #:
9917016
Issue Dt:
03/13/2018
Application #:
14567544
Filing Dt:
12/11/2014
Publication #:
US20160172251
Pub Dt:
06/16/2016
Title:
INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH EFFECTIVE DUMMY GATE CAP REMOVAL
29
Patent #:
9685342
Issue Dt:
06/20/2017
Application #:
14567598
Filing Dt:
12/11/2014
Publication #:
US20160172255
Pub Dt:
06/16/2016
Title:
WAFER PROCESSING APPARATUSES AND METHODS OF OPERATING THE SAME
30
Patent #:
9110014
Issue Dt:
08/18/2015
Application #:
14568382
Filing Dt:
12/12/2014
Publication #:
US20150137191
Pub Dt:
05/21/2015
Title:
FIELD EFFECT TRANSISTOR-BASED BIO-SENSOR
31
Patent #:
9640228
Issue Dt:
05/02/2017
Application #:
14568966
Filing Dt:
12/12/2014
Publication #:
US20160172011
Pub Dt:
06/16/2016
Title:
CMOS DEVICE WITH READING CIRCUIT
32
Patent #:
9640988
Issue Dt:
05/02/2017
Application #:
14569005
Filing Dt:
12/12/2014
Publication #:
US20160172850
Pub Dt:
06/16/2016
Title:
COMPARATIVE ESD POWER CLAMP
33
Patent #:
9714985
Issue Dt:
07/25/2017
Application #:
14569350
Filing Dt:
12/12/2014
Publication #:
US20150097576
Pub Dt:
04/09/2015
Title:
CALIBRATION ASSEMBLY FOR AIDE IN DETECTION OF ANALYTES WITH ELECTROMAGNETIC READ-WRITE HEADS
34
Patent #:
9411022
Issue Dt:
08/09/2016
Application #:
14569376
Filing Dt:
12/12/2014
Publication #:
US20150097552
Pub Dt:
04/09/2015
Title:
CALIBRATION CORRELATION FOR CALIBRATION ASSEMBLY HAVING ELECTROMAGNETIC READ HEAD
35
Patent #:
9153496
Issue Dt:
10/06/2015
Application #:
14570049
Filing Dt:
12/15/2014
Publication #:
US20150099336
Pub Dt:
04/09/2015
Title:
METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS
36
Patent #:
NONE
Issue Dt:
Application #:
14570292
Filing Dt:
12/15/2014
Publication #:
US20150137270
Pub Dt:
05/21/2015
Title:
SUPERIOR INTEGRITY OF A HIGH-K GATE STACK BY FORMING A CONTROLLED UNDERCUT ON THE BASIS OF A WET CHEMISTRY
37
Patent #:
9305878
Issue Dt:
04/05/2016
Application #:
14570617
Filing Dt:
12/15/2014
Publication #:
US20150097291
Pub Dt:
04/09/2015
Title:
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS
38
Patent #:
9391075
Issue Dt:
07/12/2016
Application #:
14571460
Filing Dt:
12/16/2014
Publication #:
US20150097246
Pub Dt:
04/09/2015
Title:
INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
39
Patent #:
9281045
Issue Dt:
03/08/2016
Application #:
14571496
Filing Dt:
12/16/2014
Title:
REFRESH HIDDEN EDRAM MEMORY
40
Patent #:
9337289
Issue Dt:
05/10/2016
Application #:
14571628
Filing Dt:
12/16/2014
Publication #:
US20150137269
Pub Dt:
05/21/2015
Title:
REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
41
Patent #:
9390925
Issue Dt:
07/12/2016
Application #:
14572975
Filing Dt:
12/17/2014
Publication #:
US20160181105
Pub Dt:
06/23/2016
Title:
SILICON-GERMANIUM (SiGe) FIN FORMATION
42
Patent #:
9099353
Issue Dt:
08/04/2015
Application #:
14573050
Filing Dt:
12/17/2014
Publication #:
US20150140695
Pub Dt:
05/21/2015
Title:
METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES
43
Patent #:
9479160
Issue Dt:
10/25/2016
Application #:
14573238
Filing Dt:
12/17/2014
Publication #:
US20160182037
Pub Dt:
06/23/2016
Title:
RESONANT RADIO FREQUENCY SWITCH
44
Patent #:
9385025
Issue Dt:
07/05/2016
Application #:
14573268
Filing Dt:
12/17/2014
Publication #:
US20150099356
Pub Dt:
04/09/2015
Title:
E-FUSES CONTAINING AT LEAST ONE UNDERLYING TUNGSTEN CONTACT FOR PROGRAMMING
45
Patent #:
9536842
Issue Dt:
01/03/2017
Application #:
14574430
Filing Dt:
12/18/2014
Publication #:
US20160181208
Pub Dt:
06/23/2016
Title:
STRUCTURE WITH AIR GAP CRACK STOP
46
Patent #:
9490257
Issue Dt:
11/08/2016
Application #:
14574460
Filing Dt:
12/18/2014
Publication #:
US20160181252
Pub Dt:
06/23/2016
Title:
DEEP TRENCH POLYSILICON FIN FIRST
47
Patent #:
9536882
Issue Dt:
01/03/2017
Application #:
14574504
Filing Dt:
12/18/2014
Publication #:
US20160181247
Pub Dt:
06/23/2016
Title:
FIELD-ISOLATED BULK FINFET
48
Patent #:
9455141
Issue Dt:
09/27/2016
Application #:
14574533
Filing Dt:
12/18/2014
Publication #:
US20160181095
Pub Dt:
06/23/2016
Title:
SILICON-GERMANIUM FIN OF HEIGHT ABOVE CRITICAL THICKNESS
49
Patent #:
10060974
Issue Dt:
08/28/2018
Application #:
14574746
Filing Dt:
12/18/2014
Publication #:
US20160178694
Pub Dt:
06/23/2016
Title:
ELECTRICAL CIRCUIT ODOMETER SENSOR ARRAY
50
Patent #:
9685370
Issue Dt:
06/20/2017
Application #:
14574889
Filing Dt:
12/18/2014
Publication #:
US20160181151
Pub Dt:
06/23/2016
Title:
TITANIUM TUNGSTEN LINER USED WITH COPPER INTERCONNECTS
51
Patent #:
9399753
Issue Dt:
07/26/2016
Application #:
14574995
Filing Dt:
12/18/2014
Publication #:
US20150105308
Pub Dt:
04/16/2015
Title:
AQUA REGIA AND HYDROGEN PEROXIDE HCL COMBINATION TO REMOVE NI AND NIPT RESIDUES
52
Patent #:
9385245
Issue Dt:
07/05/2016
Application #:
14575311
Filing Dt:
12/18/2014
Publication #:
US20150102289
Pub Dt:
04/16/2015
Title:
GATE TUNABLE TUNNEL DIODE
53
Patent #:
9230886
Issue Dt:
01/05/2016
Application #:
14575639
Filing Dt:
12/18/2014
Publication #:
US20150137359
Pub Dt:
05/21/2015
Title:
METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION
54
Patent #:
9087733
Issue Dt:
07/21/2015
Application #:
14575677
Filing Dt:
12/18/2014
Publication #:
US20150102417
Pub Dt:
04/16/2015
Title:
DOUBLE TRENCH WELL FORMATION IN SRAM CELLS
55
Patent #:
9525069
Issue Dt:
12/20/2016
Application #:
14576611
Filing Dt:
12/19/2014
Publication #:
US20150303272
Pub Dt:
10/22/2015
Title:
STRUCTURE AND METHOD TO FORM A FINFET DEVICE
56
Patent #:
9251890
Issue Dt:
02/02/2016
Application #:
14577113
Filing Dt:
12/19/2014
Title:
BIAS TEMPERATURE INSTABILITY STATE DETECTION AND CORRECTION
57
Patent #:
9755031
Issue Dt:
09/05/2017
Application #:
14577431
Filing Dt:
12/19/2014
Publication #:
US20160181381
Pub Dt:
06/23/2016
Title:
TRENCH EPITAXIAL GROWTH FOR A FINFET DEVICE HAVING REDUCED CAPACITANCE
58
Patent #:
9601565
Issue Dt:
03/21/2017
Application #:
14578523
Filing Dt:
12/22/2014
Publication #:
US20160181359
Pub Dt:
06/23/2016
Title:
ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE
59
Patent #:
9613177
Issue Dt:
04/04/2017
Application #:
14578717
Filing Dt:
12/22/2014
Publication #:
US20150113484
Pub Dt:
04/23/2015
Title:
METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES
60
Patent #:
9530860
Issue Dt:
12/27/2016
Application #:
14578768
Filing Dt:
12/22/2014
Publication #:
US20160181394
Pub Dt:
06/23/2016
Title:
III-V MOSFETS With Halo-Doped Bottom Barrier Layer
61
Patent #:
9178053
Issue Dt:
11/03/2015
Application #:
14579122
Filing Dt:
12/22/2014
Publication #:
US20150108586
Pub Dt:
04/23/2015
Title:
TRANSISTOR DEVICE WITH IMPROVED SOURCE/DRAIN JUNCTION ARCHITECTURE AND METHODS OF MAKING SUCH A DEVICE
62
Patent #:
9165840
Issue Dt:
10/20/2015
Application #:
14579255
Filing Dt:
12/22/2014
Publication #:
US20150111349
Pub Dt:
04/23/2015
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF
63
Patent #:
9231051
Issue Dt:
01/05/2016
Application #:
14579428
Filing Dt:
12/22/2014
Publication #:
US20150145071
Pub Dt:
05/28/2015
Title:
METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES
64
Patent #:
9431485
Issue Dt:
08/30/2016
Application #:
14580274
Filing Dt:
12/23/2014
Publication #:
US20160181367
Pub Dt:
06/23/2016
Title:
FORMATION OF FINFET JUNCTION
65
Patent #:
9425144
Issue Dt:
08/23/2016
Application #:
14580539
Filing Dt:
12/23/2014
Publication #:
US20150137312
Pub Dt:
05/21/2015
Title:
METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY
66
Patent #:
9384792
Issue Dt:
07/05/2016
Application #:
14580589
Filing Dt:
12/23/2014
Publication #:
US20150294706
Pub Dt:
10/15/2015
Title:
OFFSET-CANCELLING SELF-REFERENCE STT-MRAM SENSE AMPLIFIER
67
Patent #:
9087706
Issue Dt:
07/21/2015
Application #:
14580834
Filing Dt:
12/23/2014
Publication #:
US20150108580
Pub Dt:
04/23/2015
Title:
METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES
68
Patent #:
9251826
Issue Dt:
02/02/2016
Application #:
14581207
Filing Dt:
12/23/2014
Publication #:
US20160019927
Pub Dt:
01/21/2016
Title:
UTILIZING STORED WRITE ENVIRONMENT CONDITIONS FOR READ ERROR RECOVERY
69
Patent #:
9564501
Issue Dt:
02/07/2017
Application #:
14581741
Filing Dt:
12/23/2014
Publication #:
US20160181384
Pub Dt:
06/23/2016
Title:
REDUCED TRENCH PROFILE FOR A GATE
70
Patent #:
10062762
Issue Dt:
08/28/2018
Application #:
14581857
Filing Dt:
12/23/2014
Publication #:
US20160181390
Pub Dt:
06/23/2016
Title:
SEMICONDUCTOR DEVICES HAVING LOW CONTACT RESISTANCE AND LOW CURRENT LEAKAGE
71
Patent #:
9960168
Issue Dt:
05/01/2018
Application #:
14582655
Filing Dt:
12/24/2014
Publication #:
US20160190140
Pub Dt:
06/30/2016
Title:
CAPACITOR STRAP CONNECTION STRUCTURE AND FABRICATION METHOD
72
Patent #:
9343372
Issue Dt:
05/17/2016
Application #:
14583835
Filing Dt:
12/29/2014
Title:
METAL STACK FOR REDUCED GATE RESISTANCE
73
Patent #:
9887196
Issue Dt:
02/06/2018
Application #:
14583842
Filing Dt:
12/29/2014
Publication #:
US20150287648
Pub Dt:
10/08/2015
Title:
FINFET INCLUDING TUNABLE FIN HEIGHT AND TUNABLE FIN WIDTH RATIO
74
Patent #:
9614023
Issue Dt:
04/04/2017
Application #:
14584068
Filing Dt:
12/29/2014
Publication #:
US20160190229
Pub Dt:
06/30/2016
Title:
SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE
75
Patent #:
9685555
Issue Dt:
06/20/2017
Application #:
14584161
Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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