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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 128 of 146
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Patent #:	9275898	Issue Dt:	03/01/2016	Application #:	14637442	Filing Dt:	03/04/2015
Title:	METHOD TO IMPROVE SELECTIVITY COBALT CAP PROCESS

Patent #:	9541839	Issue Dt:	01/10/2017	Application #:	14637459	Filing Dt:	03/04/2015
Publication #:	US20160259251	Pub Dt:	09/08/2016
Title:	METHOD AND DEVICE FOR SPLITTING A HIGH-POWER LIGHT BEAM TO PROVIDE SIMULTANEOUS SUB-BEAMS TO PHOTOLITHOGRAPHY SCANNERS

Patent #:	9379104	Issue Dt:	06/28/2016	Application #:	14639159	Filing Dt:	03/05/2015
Title:	METHOD TO MAKE GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING

Patent #:	9342466	Issue Dt:	05/17/2016	Application #:	14640047	Filing Dt:	03/06/2015
Publication #:	US20150178225	Pub Dt:	06/25/2015
Title:	MULTIPLE VOLUME ENCRYPTION OF STORAGE DEVICES USING SELF ENCRYPTING DRIVE (SED)

Patent #:	9449972	Issue Dt:	09/20/2016	Application #:	14640151	Filing Dt:	03/06/2015
Publication #:	US20160260714	Pub Dt:	09/08/2016
Title:	FERROELECTRIC FINFET

Patent #:	9196700	Issue Dt:	11/24/2015	Application #:	14640698	Filing Dt:	03/06/2015
Publication #:	US20150187901	Pub Dt:	07/02/2015
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	9252232	Issue Dt:	02/02/2016	Application #:	14640735	Filing Dt:	03/06/2015
Publication #:	US20150179459	Pub Dt:	06/25/2015
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	9276118	Issue Dt:	03/01/2016	Application #:	14640851	Filing Dt:	03/06/2015
Publication #:	US20150179789	Pub Dt:	06/25/2015
Title:	FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME

Patent #:	9401373	Issue Dt:	07/26/2016	Application #:	14641462	Filing Dt:	03/09/2015
Publication #:	US20150187815	Pub Dt:	07/02/2015
Title:	MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES

Patent #:	9324656	Issue Dt:	04/26/2016	Application #:	14641551	Filing Dt:	03/09/2015
Title:	METHODS OF FORMING CONTACTS ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9412695	Issue Dt:	08/09/2016	Application #:	14641699	Filing Dt:	03/09/2015
Title:	INTERCONNECT STRUCTURES AND METHODS OF FABRICATION

Patent #:	9419137	Issue Dt:	08/16/2016	Application #:	14641809	Filing Dt:	03/09/2015
Title:	STRESS MEMORIZATION FILM AND OXIDE ISOLATION IN FINS

Patent #:	9577099	Issue Dt:	02/21/2017	Application #:	14641917	Filing Dt:	03/09/2015
Publication #:	US20160268413	Pub Dt:	09/15/2016
Title:	DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER

Patent #:	9379116	Issue Dt:	06/28/2016	Application #:	14642909	Filing Dt:	03/10/2015
Title:	FABRICATION OF A DEEP TRENCH MEMORY CELL

Patent #:	NONE	Issue Dt:		Application #:	14643323	Filing Dt:	03/10/2015
Publication #:	US20160266332	Pub Dt:	09/15/2016
Title:	OPTICAL DIE PACKAGING

Patent #:	9583616	Issue Dt:	02/28/2017	Application #:	14643326	Filing Dt:	03/10/2015
Publication #:	US20160268424	Pub Dt:	09/15/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING BACKGATE REGIONS AND METHOD FOR THE FORMATION THEREOF

Patent #:	9530869	Issue Dt:	12/27/2016	Application #:	14643409	Filing Dt:	03/10/2015
Publication #:	US20160268399	Pub Dt:	09/15/2016
Title:	METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES

Patent #:	9865514	Issue Dt:	01/09/2018	Application #:	14643436	Filing Dt:	03/10/2015
Publication #:	US20150187667	Pub Dt:	07/02/2015
Title:	INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH

Patent #:	9899268	Issue Dt:	02/20/2018	Application #:	14644269	Filing Dt:	03/11/2015
Publication #:	US20160268171	Pub Dt:	09/15/2016
Title:	CAP LAYER FOR SPACER-CONSTRAINED EPITAXIALLY GROWN MATERIAL ON FINS OF A FINFET DEVICE

Patent #:	9543441	Issue Dt:	01/10/2017	Application #:	14645121	Filing Dt:	03/11/2015
Publication #:	US20160268435	Pub Dt:	09/15/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR FABRICATING HIGH PERFORMANCE FINFET DEVICE

Patent #:	9251825	Issue Dt:	02/02/2016	Application #:	14645350	Filing Dt:	03/11/2015
Publication #:	US20150187379	Pub Dt:	07/02/2015
Title:	BACKWARD COMPATIBLE HEAD FOR QUASI-STATIC TILTED READING AND/OR RECORDING

Patent #:	10032870	Issue Dt:	07/24/2018	Application #:	14645449	Filing Dt:	03/12/2015
Publication #:	US20160268123	Pub Dt:	09/15/2016
Title:	LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON

Patent #:	9696376	Issue Dt:	07/04/2017	Application #:	14645541	Filing Dt:	03/12/2015
Publication #:	US20160266200	Pub Dt:	09/15/2016
Title:	LEAKAGE TESTING OF INTEGRATED CIRCUITS USING A LOGARITHMIC TRANSDUCER AND A VOLTMETER

Patent #:	9142513	Issue Dt:	09/22/2015	Application #:	14645598	Filing Dt:	03/12/2015
Publication #:	US20150187702	Pub Dt:	07/02/2015
Title:	MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES

Patent #:	9844124	Issue Dt:	12/12/2017	Application #:	14645871	Filing Dt:	03/12/2015
Publication #:	US20160270200	Pub Dt:	09/15/2016
Title:	METHOD, APPARATUS AND SYSTEM FOR USING FREE-ELECTRON LASER COMPATIBLE EUV BEAM FOR SEMICONDUCTOR WAFER METROLOGY

Patent #:	9640533	Issue Dt:	05/02/2017	Application #:	14656412	Filing Dt:	03/12/2015
Publication #:	US20160268257	Pub Dt:	09/15/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LAYER WITH LATERAL OVER-GROWTH SUPPRESSION

Patent #:	9337340	Issue Dt:	05/10/2016	Application #:	14656649	Filing Dt:	03/12/2015
Publication #:	US20150187947	Pub Dt:	07/02/2015
Title:	FINFET WITH ACTIVE REGION SHAPED STRUCTURES AND CHANNEL SEPARATION

Patent #:	9960257	Issue Dt:	05/01/2018	Application #:	14656671	Filing Dt:	03/12/2015
Publication #:	US20160268400	Pub Dt:	09/15/2016
Title:	COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS

Patent #:	9419015	Issue Dt:	08/16/2016	Application #:	14656758	Filing Dt:	03/13/2015
Title:	METHOD FOR INTEGRATING THIN-FILM TRANSISTORS ON AN ISOLATION REGION IN AN INTEGRATED CIRCUIT AND RESULTING DEVICE

Patent #:	9484297	Issue Dt:	11/01/2016	Application #:	14656770	Filing Dt:	03/13/2015
Publication #:	US20160268195	Pub Dt:	09/15/2016
Title:	SEMICONDUCTOR DEVICE HAVING NON-MAGNETIC SINGLE CORE INDUCTOR AND METHOD OF PRODUCING THE SAME

Patent #:	9581644	Issue Dt:	02/28/2017	Application #:	14656790	Filing Dt:	03/13/2015
Publication #:	US20150276872	Pub Dt:	10/01/2015
Title:	DIGITAL IC SIMULATION

Patent #:	9170338	Issue Dt:	10/27/2015	Application #:	14657864	Filing Dt:	03/13/2015
Publication #:	US20150253438	Pub Dt:	09/10/2015
Title:	CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS

Patent #:	9324713	Issue Dt:	04/26/2016	Application #:	14658279	Filing Dt:	03/16/2015
Title:	ELIMINATING FIELD OXIDE LOSS PRIOR TO FINFET SOURCE/DRAIN EPITAXIAL GROWTH

Patent #:	9250890	Issue Dt:	02/02/2016	Application #:	14658587	Filing Dt:	03/16/2015
Publication #:	US20150186130	Pub Dt:	07/02/2015
Title:	OPTIMIZING PERFORMANCE OF A COMPUTER SYSTEM IN RESPONSE TO A SOFTWARE CHANGE

Patent #:	9559284	Issue Dt:	01/31/2017	Application #:	14659749	Filing Dt:	03/17/2015
Publication #:	US20160276570	Pub Dt:	09/22/2016
Title:	SILICIDED NANOWIRES FOR NANOBRIDGE WEAK LINKS

Patent #:	9772371	Issue Dt:	09/26/2017	Application #:	14659793	Filing Dt:	03/17/2015
Publication #:	US20150185277	Pub Dt:	07/02/2015
Title:	VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR

Patent #:	10068895	Issue Dt:	09/04/2018	Application #:	14661202	Filing Dt:	03/18/2015
Publication #:	US20160276336	Pub Dt:	09/22/2016
Title:	TRANSISTORS PATTERNED WITH ELECTROSTATIC DISCHARGE PROTECTION AND METHODS OF FABRICATION

Patent #:	9418745	Issue Dt:	08/16/2016	Application #:	14661383	Filing Dt:	03/18/2015
Title:	REBALANCING IN TWIN CELL MEMORY SCHEMES TO ENABLE MULTIPLE WRITES

Patent #:	9397158	Issue Dt:	07/19/2016	Application #:	14662468	Filing Dt:	03/19/2015
Publication #:	US20150194484	Pub Dt:	07/09/2015
Title:	Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion

Patent #:	9865603	Issue Dt:	01/09/2018	Application #:	14662734	Filing Dt:	03/19/2015
Publication #:	US20160276350	Pub Dt:	09/22/2016
Title:	TRANSISTOR STRUCTURE HAVING N-TYPE AND P-TYPE ELONGATED REGIONS INTERSECTING UNDER COMMON GATE

Patent #:	9484402	Issue Dt:	11/01/2016	Application #:	14662743	Filing Dt:	03/19/2015
Publication #:	US20150194334	Pub Dt:	07/09/2015
Title:	Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion

Patent #:	9295166	Issue Dt:	03/22/2016	Application #:	14663754	Filing Dt:	03/20/2015
Publication #:	US20150194408	Pub Dt:	07/09/2015
Title:	DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING

Patent #:	9095081	Issue Dt:	07/28/2015	Application #:	14663806	Filing Dt:	03/20/2015
Publication #:	US20150195920	Pub Dt:	07/09/2015
Title:	DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING

Patent #:	9343407	Issue Dt:	05/17/2016	Application #:	14664036	Filing Dt:	03/20/2015
Publication #:	US20150194385	Pub Dt:	07/09/2015
Title:	METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED THEREBY

Patent #:	9337264	Issue Dt:	05/10/2016	Application #:	14664435	Filing Dt:	03/20/2015
Publication #:	US20150194487	Pub Dt:	07/09/2015
Title:	Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric

Patent #:	9548136	Issue Dt:	01/17/2017	Application #:	14664959	Filing Dt:	03/23/2015
Publication #:	US20160284421	Pub Dt:	09/29/2016
Title:	METHOD TO IDENTIFY EXTRINSIC SRAM BITS FOR FAILURE ANALYSIS BASED ON FAIL COUNT VOLTAGE RESPONSE

Patent #:	9397073	Issue Dt:	07/19/2016	Application #:	14664970	Filing Dt:	03/23/2015
Title:	METHOD OF USING A BACK-END-OF-LINE CONNECTION STRUCTURE TO DISTRIBUTE CURRENT EVENLY AMONG MULTIPLE TSVS IN A SERIES FOR DELIVERY TO A TOP DIE

Patent #:	9754067	Issue Dt:	09/05/2017	Application #:	14665242	Filing Dt:	03/23/2015
Publication #:	US20150347667	Pub Dt:	12/03/2015
Title:	METHOD OF CHECKING THE LAYOUT INTEGRITY

Patent #:	9343550	Issue Dt:	05/17/2016	Application #:	14666469	Filing Dt:	03/24/2015
Publication #:	US20150194507	Pub Dt:	07/09/2015
Title:	SILICON-ON-NOTHING FINFETS

Patent #:	9673039	Issue Dt:	06/06/2017	Application #:	14666787	Filing Dt:	03/24/2015
Publication #:	US20160284540	Pub Dt:	09/29/2016
Title:	DEVICES COMPRISING HIGH-K DIELECTRIC LAYER AND METHODS OF FORMING SAME

Patent #:	9391860	Issue Dt:	07/12/2016	Application #:	14667174	Filing Dt:	03/24/2015
Publication #:	US20150195168	Pub Dt:	07/09/2015
Title:	SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY

Patent #:	9735012	Issue Dt:	08/15/2017	Application #:	14667778	Filing Dt:	03/25/2015
Publication #:	US20160284549	Pub Dt:	09/29/2016
Title:	SHORT-CHANNEL NFET DEVICE

Patent #:	9913405	Issue Dt:	03/06/2018	Application #:	14668017	Filing Dt:	03/25/2015
Publication #:	US20160286686	Pub Dt:	09/29/2016
Title:	GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES

Patent #:	9269589	Issue Dt:	02/23/2016	Application #:	14668018	Filing Dt:	03/25/2015
Publication #:	US20150200107	Pub Dt:	07/16/2015
Title:	DENSE FINFET SRAM

Patent #:	9585257	Issue Dt:	02/28/2017	Application #:	14668031	Filing Dt:	03/25/2015
Publication #:	US20160286660	Pub Dt:	09/29/2016
Title:	METHOD OF FORMING A GLASS INTERPOSER WITH THERMAL VIAS

Patent #:	9633911	Issue Dt:	04/25/2017	Application #:	14668482	Filing Dt:	03/25/2015
Publication #:	US20150200205	Pub Dt:	07/16/2015
Title:	SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS

Patent #:	9236116	Issue Dt:	01/12/2016	Application #:	14669043	Filing Dt:	03/26/2015
Title:	MEMORY CELLS WITH READ ACCESS SCHEMES

Patent #:	9460969	Issue Dt:	10/04/2016	Application #:	14669055	Filing Dt:	03/26/2015
Publication #:	US20160284602	Pub Dt:	09/29/2016
Title:	MACRO TO MONITOR N-P BUMP

Patent #:	9401315	Issue Dt:	07/26/2016	Application #:	14669775	Filing Dt:	03/26/2015
Title:	THERMAL HOT SPOT COOLING FOR SEMICONDUCTOR DEVICES

Patent #:	9496185	Issue Dt:	11/15/2016	Application #:	14670800	Filing Dt:	03/27/2015
Publication #:	US20160284607	Pub Dt:	09/29/2016
Title:	DUAL CHANNEL FINFET WITH RELAXED PFET REGION

Patent #:	9111999	Issue Dt:	08/18/2015	Application #:	14671027	Filing Dt:	03/27/2015
Publication #:	US20150200131	Pub Dt:	07/16/2015
Title:	TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP

Patent #:	10103070	Issue Dt:	10/16/2018	Application #:	14671265	Filing Dt:	03/27/2015
Publication #:	US20160284609	Pub Dt:	09/29/2016
Title:	DYNAMIC INTEGRATED CIRCUIT FABRICATION METHODS

Patent #:	9324350	Issue Dt:	04/26/2016	Application #:	14671819	Filing Dt:	03/27/2015
Publication #:	US20150206546	Pub Dt:	07/23/2015
Title:	HIGH DENSITY TIMING BASED SERVO FORMAT FOR USE WITH TILTED TRANSDUCER ARRAYS

Patent #:	9378948	Issue Dt:	06/28/2016	Application #:	14672157	Filing Dt:	03/28/2015
Publication #:	US20150206744	Pub Dt:	07/23/2015
Title:	FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS

Patent #:	9349732	Issue Dt:	05/24/2016	Application #:	14672865	Filing Dt:	03/30/2015
Publication #:	US20150206880	Pub Dt:	07/23/2015
Title:	HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION

Patent #:	9851398	Issue Dt:	12/26/2017	Application #:	14673185	Filing Dt:	03/30/2015
Publication #:	US20160291084	Pub Dt:	10/06/2016
Title:	VIA LEAKAGE AND BREAKDOWN TESTING

Patent #:	9348706	Issue Dt:	05/24/2016	Application #:	14673926	Filing Dt:	03/31/2015
Publication #:	US20150205683	Pub Dt:	07/23/2015
Title:	MAINTAINING A CLUSTER OF VIRTUAL MACHINES

Patent #:	9224843	Issue Dt:	12/29/2015	Application #:	14673958	Filing Dt:	03/31/2015
Publication #:	US20150206959	Pub Dt:	07/23/2015
Title:	FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION

Patent #:	9425106	Issue Dt:	08/23/2016	Application #:	14674108	Filing Dt:	03/31/2015
Title:	METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR TAPER FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9535319	Issue Dt:	01/03/2017	Application #:	14674157	Filing Dt:	03/31/2015
Publication #:	US20160291457	Pub Dt:	10/06/2016
Title:	RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR THE FORMATION THEREOF

Patent #:	9502286	Issue Dt:	11/22/2016	Application #:	14674460	Filing Dt:	03/31/2015
Publication #:	US20160163585	Pub Dt:	06/09/2016
Title:	METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9337101	Issue Dt:	05/10/2016	Application #:	14674549	Filing Dt:	03/31/2015
Title:	METHODS FOR SELECTIVELY REMOVING A FIN WHEN FORMING FINFET DEVICES

Patent #:	9471743	Issue Dt:	10/18/2016	Application #:	14674571	Filing Dt:	03/31/2015
Publication #:	US20160292342	Pub Dt:	10/06/2016
Title:	PREDICTING PROCESS FAIL LIMITS

Patent #:	9245885	Issue Dt:	01/26/2016	Application #:	14674656	Filing Dt:	03/31/2015
Title:	METHODS OF FORMING LATERAL AND VERTICAL FINFET DEVICES AND THE RESULTING PRODUCT

Patent #:	9437481	Issue Dt:	09/06/2016	Application #:	14674792	Filing Dt:	03/31/2015
Publication #:	US20160163584	Pub Dt:	06/09/2016
Title:	SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR TWO DIMENSIONAL PATTERNS

Patent #:	9615248	Issue Dt:	04/04/2017	Application #:	14674859	Filing Dt:	03/31/2015
Publication #:	US20160295401	Pub Dt:	10/06/2016
Title:	ANONYMOUS VEHICLE COMMUNICATION PROTOCOL IN VEHICLE-TO-VEHICLE NETWORKS

Patent #:	9362181	Issue Dt:	06/07/2016	Application #:	14674924	Filing Dt:	03/31/2015
Publication #:	US20160163604	Pub Dt:	06/09/2016
Title:	METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS

Patent #:	9337050	Issue Dt:	05/10/2016	Application #:	14675045	Filing Dt:	03/31/2015
Title:	METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS

Patent #:	9579608	Issue Dt:	02/28/2017	Application #:	14675316	Filing Dt:	03/31/2015
Publication #:	US20150202575	Pub Dt:	07/23/2015
Title:	COMPOSITE MEMBRANES AND METHODS OF PREPARATION THEREOF

Patent #:	9443956	Issue Dt:	09/13/2016	Application #:	14675880	Filing Dt:	04/01/2015
Publication #:	US20160163816	Pub Dt:	06/09/2016
Title:	METHOD FOR FORMING AIR GAP STRUCTURE USING CARBON-CONTAINING SPACER

Patent #:	9455198	Issue Dt:	09/27/2016	Application #:	14676034	Filing Dt:	04/01/2015
Title:	METHODS OF REMOVING FINS SO AS TO FORM ISOLATION STRUCTURES ON PRODUCTS THAT INCLUDE FINFET SEMICONDUCTOR DEVICES

Patent #:	9449835	Issue Dt:	09/20/2016	Application #:	14676097	Filing Dt:	04/01/2015
Publication #:	US20160163555	Pub Dt:	06/09/2016
Title:	METHODS OF FORMING FEATURES HAVING DIFFERING PITCH SPACING AND CRITICAL DIMENSIONS

Patent #:	9406676	Issue Dt:	08/02/2016	Application #:	14676165	Filing Dt:	04/01/2015
Publication #:	US20160190130	Pub Dt:	06/30/2016
Title:	METHOD FOR FORMING SINGLE DIFFUSION BREAKS BETWEEN FINFET DEVICES AND THE RESULTING DEVICES

Patent #:	9406803	Issue Dt:	08/02/2016	Application #:	14676239	Filing Dt:	04/01/2015
Publication #:	US20160190323	Pub Dt:	06/30/2016
Title:	FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN

Patent #:	9287130	Issue Dt:	03/15/2016	Application #:	14676345	Filing Dt:	04/01/2015
Title:	METHOD FOR SINGLE FIN CUTS USING SELECTIVE ION IMPLANTS

Patent #:	9401408	Issue Dt:	07/26/2016	Application #:	14676608	Filing Dt:	04/01/2015
Publication #:	US20160190262	Pub Dt:	06/30/2016
Title:	CONFINED EARLY EPITAXY WITH LOCAL INTERCONNECT CAPABILITY

Patent #:	9581411	Issue Dt:	02/28/2017	Application #:	14676663	Filing Dt:	04/01/2015
Publication #:	US20150276343	Pub Dt:	10/01/2015
Title:	STOCK AND DETACHABLE ACCESSORY HOUSING FOR A SMALL ARMS WEAPON

Patent #:	9634123	Issue Dt:	04/25/2017	Application #:	14676909	Filing Dt:	04/02/2015
Publication #:	US20160163831	Pub Dt:	06/09/2016
Title:	FINFET DEVICE INCLUDING A DIELECTRICALLY ISOLATED SILICON ALLOY FIN

Patent #:	9406752	Issue Dt:	08/02/2016	Application #:	14676912	Filing Dt:	04/02/2015
Publication #:	US20160190251	Pub Dt:	06/30/2016
Title:	FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE

Patent #:	9231087	Issue Dt:	01/05/2016	Application #:	14677303	Filing Dt:	04/02/2015
Publication #:	US20150214344	Pub Dt:	07/30/2015
Title:	BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS

Patent #:	9397203	Issue Dt:	07/19/2016	Application #:	14677460	Filing Dt:	04/02/2015
Publication #:	US20150214346	Pub Dt:	07/30/2015
Title:	LATERAL SILICON-ON-INSULATOR BIPOLAR JUNCTION TRANSISTOR PROCESS AND STRUCTURE

Patent #:	9690187	Issue Dt:	06/27/2017	Application #:	14678008	Filing Dt:	04/03/2015
Publication #:	US20160161841	Pub Dt:	06/09/2016
Title:	SAMPLING FOR OPC MODEL BUILDING

Patent #:	NONE	Issue Dt:		Application #:	14678016	Filing Dt:	04/03/2015
Publication #:	US20160293579	Pub Dt:	10/06/2016
Title:	INTEGRATION STRUCTURES FOR HIGH CURRENT APPLICATIONS

Patent #:	9589848	Issue Dt:	03/07/2017	Application #:	14678024	Filing Dt:	04/03/2015
Publication #:	US20150214117	Pub Dt:	07/30/2015
Title:	FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS

Patent #:	9536778	Issue Dt:	01/03/2017	Application #:	14679060	Filing Dt:	04/06/2015
Publication #:	US20160293478	Pub Dt:	10/06/2016
Title:	SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR METAL ROUTING

Patent #:	9397162	Issue Dt:	07/19/2016	Application #:	14679074	Filing Dt:	04/06/2015
Publication #:	US20160190252	Pub Dt:	06/30/2016
Title:	FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE

Patent #:	9466717	Issue Dt:	10/11/2016	Application #:	14680172	Filing Dt:	04/07/2015
Publication #:	US20160300947	Pub Dt:	10/13/2016
Title:	COMPLEX SEMICONDUCTOR DEVICES OF THE SOI TYPE

Patent #:	9460806	Issue Dt:	10/04/2016	Application #:	14680228	Filing Dt:	04/07/2015
Publication #:	US20160163398	Pub Dt:	06/09/2016
Title:	METHOD FOR CREATING AN OTPROM ARRAY POSSESSING MULTI-BIT CAPACITY WITH TDDB STRESS RELIABILITY MECHANISM

Patent #:	9443940	Issue Dt:	09/13/2016	Application #:	14680328	Filing Dt:	04/07/2015
Title:	DEFECT REDUCTION WITH ROTATED DOUBLE ASPECT RATIO TRAPPING

100

Patent #:	9755841	Issue Dt:	09/05/2017	Application #:	14680961	Filing Dt:	04/07/2015
Publication #:	US20160301534	Pub Dt:	10/13/2016
Title:	METHOD, APPARATUS AND SYSTEM FOR SECURITY APPLICATION FOR INTEGRATED CIRCUIT DEVICES

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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