USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 13 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146

Patent #:	6713791	Issue Dt:	03/30/2004	Application #:	09770788	Filing Dt:	01/26/2001
Publication #:	US20020100918	Pub Dt:	08/01/2002
Title:	T-RAM ARRAY HAVING A PLANAR CELL STRUCTURE AND METHOD FOR FABRICATING THE SAME

Patent #:	6509134	Issue Dt:	01/21/2003	Application #:	09771149	Filing Dt:	01/26/2001
Publication #:	US20020146638	Pub Dt:	10/10/2002
Title:	NORBORNENE FLUOROACRYLATE COPOLYMERS AND PROCESS FOR USE THEREOF

Patent #:	6593035	Issue Dt:	07/15/2003	Application #:	09771236	Filing Dt:	01/26/2001
Title:	PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE USING A SILICON LAYER

Patent #:	6730452	Issue Dt:	05/04/2004	Application #:	09771261	Filing Dt:	01/26/2001
Publication #:	US20020146639	Pub Dt:	10/10/2002
Title:	LITHOGRAPHIC PHOTORESIST COMPOSITION AND PROCESS FOR ITS USE

Patent #:	6548219	Issue Dt:	04/15/2003	Application #:	09771262	Filing Dt:	01/26/2001
Publication #:	US20020102490	Pub Dt:	08/01/2002
Title:	SUBSTITUTED NORBORNENE FLUOROACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS

Patent #:	6589713	Issue Dt:	07/08/2003	Application #:	09771820	Filing Dt:	01/29/2001
Title:	PROCESS FOR REDUCING THE PITCH OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS

Patent #:	6500751	Issue Dt:	12/31/2002	Application #:	09772205	Filing Dt:	01/29/2001
Publication #:	US20020146900	Pub Dt:	10/10/2002
Title:	METHOD OF FORMING RECESSED THIN FILM LANDING PAD STRUCTURE

Patent #:	6580136	Issue Dt:	06/17/2003	Application #:	09772345	Filing Dt:	01/30/2001
Publication #:	US20020100945	Pub Dt:	08/01/2002
Title:	METHOD FOR DELINEATION OF EDRAM SUPPORT DEVICE NOTCHED GATE

Patent #:	6534224	Issue Dt:	03/18/2003	Application #:	09772577	Filing Dt:	01/30/2001
Publication #:	US20020102471	Pub Dt:	08/01/2002
Title:	PHASE SHIFT MASK AND SYSTEM AND METHOD FOR MAKING THE SAME

Patent #:	6566680	Issue Dt:	05/20/2003	Application #:	09772610	Filing Dt:	01/30/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR

Patent #:	6444534	Issue Dt:	09/03/2002	Application #:	09772649	Filing Dt:	01/30/2001
Title:	SOI SEMICONDUCTOR DEVICE OPENING IMPLANTATION GETTERING METHOD

Patent #:	6538307	Issue Dt:	03/25/2003	Application #:	09772889	Filing Dt:	01/31/2001
Title:	PACKAGING SUBSTRATE COMPRISING STAGGERED VIAS

Patent #:	6510120	Issue Dt:	01/21/2003	Application #:	09773323	Filing Dt:	01/31/2001
Publication #:	US20020101795	Pub Dt:	08/01/2002
Title:	METHOD FOR WRITING AND/OR ERASING HIGH DENSITY DATA ON A MEDIA

Patent #:	6468363	Issue Dt:	10/22/2002	Application #:	09773488	Filing Dt:	02/02/2001
Publication #:	US20010025673	Pub Dt:	10/04/2001
Title:	COMPOSITION FOR INCREASING ACTIVITY OF A NO-CLEAN FLUX

Patent #:	7214593	Issue Dt:	05/08/2007	Application #:	09773798	Filing Dt:	02/01/2001
Publication #:	US20020102787	Pub Dt:	08/01/2002
Title:	PASSIVATION FOR IMPROVED BIPOLAR YIELD

Patent #:	6599839	Issue Dt:	07/29/2003	Application #:	09773906	Filing Dt:	02/02/2001
Title:	PLASMA ETCH PROCESS FOR NONHOMOGENOUS FILM

Patent #:	6501555	Issue Dt:	12/31/2002	Application #:	09773954	Filing Dt:	02/01/2001
Title:	OPTICAL TECHNIQUE TO DETECT ETCH PROCESS TERMINATION

Patent #:	6426265	Issue Dt:	07/30/2002	Application #:	09774126	Filing Dt:	01/30/2001
Publication #:	US20020100917	Pub Dt:	08/01/2002
Title:	INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY

Patent #:	6380589	Issue Dt:	04/30/2002	Application #:	09774138	Filing Dt:	01/30/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR SRAM CELL

Patent #:	6501171	Issue Dt:	12/31/2002	Application #:	09774152	Filing Dt:	01/30/2001
Publication #:	US20020100969	Pub Dt:	08/01/2002
Title:	FLIP CHIP PACKAGE WITH IMPROVED CAP DESIGN AND PROCESS FOR MAKING THEREOF

Patent #:	6738535	Issue Dt:	05/18/2004	Application #:	09774489	Filing Dt:	01/31/2001
Publication #:	US20020138249	Pub Dt:	09/26/2002
Title:	HEAD-MOUNTED DISPLAY CONTENT TRANSFORMER

Patent #:	6475929	Issue Dt:	11/05/2002	Application #:	09774708	Filing Dt:	02/01/2001
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TREATMENT TO SACRIFICIAL STOP LAYER PRODUCING DIFFUSION TO AN ADJACENT LOW-K DIELECTRIC LAYER LOWERING THE CONSTANT

Patent #:	6365466	Issue Dt:	04/02/2002	Application #:	09774939	Filing Dt:	01/31/2001
Title:	Dual gate process using self-assembled molecular layer

Patent #:	6920088	Issue Dt:	07/19/2005	Application #:	09774943	Filing Dt:	01/31/2001
Publication #:	US20020101673	Pub Dt:	08/01/2002
Title:	ASSEMBLY FOR WRITING AND / OR ERASING HIGH DENSITY DATA ON A MEDIA

Patent #:	6920289	Issue Dt:	07/19/2005	Application #:	09775374	Filing Dt:	02/01/2001
Publication #:	US20020101638	Pub Dt:	08/01/2002
Title:	SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES

Patent #:	6738522	Issue Dt:	05/18/2004	Application #:	09776077	Filing Dt:	02/01/2001
Title:	EFFICIENT SIMD QUANTIZATION METHOD

Patent #:	6701406	Issue Dt:	03/02/2004	Application #:	09776339	Filing Dt:	02/02/2001
Title:	PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE

Patent #:	6372635	Issue Dt:	04/16/2002	Application #:	09776736	Filing Dt:	02/06/2001
Title:	METHOD FOR MAKING A SLOT VIA FILLED DUAL DAMASCENE LOW K INTERCONNECT STRUCTURE WITHOUT MIDDLE STOP LAYER

Patent #:	6525391	Issue Dt:	02/25/2003	Application #:	09776748	Filing Dt:	02/06/2001
Title:	NICKEL SILICIDE PROCESS USING STARVED SILICON DIFFUSION BARRIER

Patent #:	6478665	Issue Dt:	11/12/2002	Application #:	09777539	Filing Dt:	02/06/2001
Publication #:	US20010005669	Pub Dt:	06/28/2001
Title:	MULTI-WAFER POLISHING TOOL

Patent #:	6579149	Issue Dt:	06/17/2003	Application #:	09777548	Filing Dt:	02/06/2001
Publication #:	US20020106972	Pub Dt:	08/08/2002
Title:	SUPPORT AND ALIGNMENT DEVICE FOR ENABLING CHEMICAL MECHANICAL POLISHING RINSE AND FILM MEASUREMENTS

Patent #:	6495402	Issue Dt:	12/17/2002	Application #:	09777637	Filing Dt:	02/06/2001
Title:	SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS AND METHOD OF MANUFACTURE

Patent #:	6656830	Issue Dt:	12/02/2003	Application #:	09777695	Filing Dt:	02/07/2001
Title:	DUAL DAMASCENE WITH SILICON CARBIDE MIDDLE ETCH STOP LAYER/ARC

Patent #:	6465889	Issue Dt:	10/15/2002	Application #:	09778109	Filing Dt:	02/07/2001
Title:	SILICON CARBIDE BARC IN DUAL DAMASCENE PROCESSING

Patent #:	6686630	Issue Dt:	02/03/2004	Application #:	09778335	Filing Dt:	02/07/2001
Publication #:	US20020105039	Pub Dt:	08/08/2002
Title:	DAMASCENE DOUBLE-GATE MOSFET STRUCTURE AND ITS FABRICATION METHOD

Patent #:	6397239	Issue Dt:	05/28/2002	Application #:	09778352	Filing Dt:	02/06/2001
Publication #:	US20010051969	Pub Dt:	12/13/2001
Title:	FLOATING POINT ADDITION PIPELINE INCLUDING EXTREME VALUE, COMPARISON AND ACCUMULATE FUNCTIONS

Patent #:	6581023	Issue Dt:	06/17/2003	Application #:	09778529	Filing Dt:	02/07/2001
Title:	ACCURATE CONTACT CRITICAL DIMENSION MEASUREMENT USING VARIABLE THRESHOLD METHOD

Patent #:	6576376	Issue Dt:	06/10/2003	Application #:	09778586	Filing Dt:	02/07/2001
Title:	TRI-TONE MASK PROCESS FOR DENSE AND ISOLATED PATTERNS

Patent #:	6583070	Issue Dt:	06/24/2003	Application #:	09778777	Filing Dt:	02/08/2001
Title:	SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL

Patent #:	6551885	Issue Dt:	04/22/2003	Application #:	09779986	Filing Dt:	02/09/2001
Title:	LOW TEMPERATURE PROCESS FOR A THIN FILM TRANSISTOR

Patent #:	6403434	Issue Dt:	06/11/2002	Application #:	09779987	Filing Dt:	02/09/2001
Title:	PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS AND A HIGH-K GATE DIELECTRIC

Patent #:	6673524	Issue Dt:	01/06/2004	Application #:	09780275	Filing Dt:	02/09/2001
Publication #:	US20020146648	Pub Dt:	10/10/2002
Title:	ATTENUATING EXTREME ULTRAVIOLET (EUV) PHASE-SHIFTING MASK FABRICATION METHOD

Patent #:	6458679	Issue Dt:	10/01/2002	Application #:	09780454	Filing Dt:	02/12/2001
Title:	METHOD OF MAKING A SILICIDE STOP LAYER IN A DAMASCENE SEMICONDUCTOR STRUCTURE

Patent #:	6795951	Issue Dt:	09/21/2004	Application #:	09780558	Filing Dt:	02/09/2001
Publication #:	US20020112195	Pub Dt:	08/15/2002
Title:	METHOD AND SYSTEM FOR FAULT-TOLERANT STATIC TIMING ANALYSIS

Patent #:	6534843	Issue Dt:	03/18/2003	Application #:	09781014	Filing Dt:	02/10/2001
Publication #:	US20020109204	Pub Dt:	08/15/2002
Title:	HIGH Q INDUCTOR WITH FARADAY SHIELD AND DIELECTRIC WELL BURIED IN SUBSTRATE

Patent #:	6495437	Issue Dt:	12/17/2002	Application #:	09781039	Filing Dt:	02/09/2001
Title:	LOW TEMPERATURE PROCESS TO LOCALLY FORM HIGH-K GATE DIELECTRICS

Patent #:	6534863	Issue Dt:	03/18/2003	Application #:	09781121	Filing Dt:	02/09/2001
Publication #:	US20020111010	Pub Dt:	08/15/2002
Title:	COMMON BALL-LIMITING METALLURGY FOR I/O SITES

Patent #:	6380057	Issue Dt:	04/30/2002	Application #:	09781225	Filing Dt:	02/13/2001
Title:	ENHANCEMENT OF NICKEL SILICIDE FORMATION BY USE OF NICKEL PRE-AMORPHIZING IMPLANT

Patent #:	6372673	Issue Dt:	04/16/2002	Application #:	09781256	Filing Dt:	02/13/2001
Title:	SILICON-STARVED NITRIDE SPACER DEPOSITION

Patent #:	6380043	Issue Dt:	04/30/2002	Application #:	09781357	Filing Dt:	02/12/2001
Title:	LOW TEMPERATURE PROCESS TO FORM ELEVATED DRAIN AND SOURCE OF A FIELD EFFECT TRANSISTOR HAVING HIGH-K GATE DIELECTRIC

Patent #:	6406951	Issue Dt:	06/18/2002	Application #:	09781364	Filing Dt:	02/12/2001
Title:	FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN IN SOI TECHNOLOGY

Patent #:	6534160	Issue Dt:	03/18/2003	Application #:	09781637	Filing Dt:	02/12/2001
Publication #:	US20010005548	Pub Dt:	06/28/2001
Title:	SEMICONDUCTOR DEVICE HAVING A THERMOSET-CONTAINING DIELECTRIC MATERIAL AND METHODS FOR FABRICATING THE SAME

Patent #:	6395589	Issue Dt:	05/28/2002	Application #:	09781783	Filing Dt:	02/12/2001
Title:	FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH HIGH-K GATE DIELECTRIC IN SOI TECHNOLOGY

Patent #:	6641747	Issue Dt:	11/04/2003	Application #:	09783204	Filing Dt:	02/15/2001
Title:	METHOD AND APPARATUS FOR DETERMINING AN ETCH ENDPOINT

Patent #:	6727558	Issue Dt:	04/27/2004	Application #:	09784790	Filing Dt:	02/15/2001
Title:	CHANNEL ISOLATION USING DIELECTRIC ISOLATION STRUCTURES

Patent #:	6368965	Issue Dt:	04/09/2002	Application #:	09784842	Filing Dt:	02/15/2001
Title:	METHOD FOR LOW STRESS PLATING OF SEMICONDUCTOR VIAS AND CHANNELS

Patent #:	6440826	Issue Dt:	08/27/2002	Application #:	09785176	Filing Dt:	02/20/2001
Title:	NISI CONTACTING EXTENSIONS OF ACTIVE REGIONS

Patent #:	6498372	Issue Dt:	12/24/2002	Application #:	09785432	Filing Dt:	02/16/2001
Publication #:	US20020113267	Pub Dt:	08/22/2002
Title:	CONDUCTIVE COUPLING OF ELECTRICAL STRUCTURES TO A SEMICONDUCTOR DEVICE LOCATED UNDER A BURIED OXIDE LAYER

Patent #:	6465361	Issue Dt:	10/15/2002	Application #:	09785444	Filing Dt:	02/20/2001
Title:	METHOD FOR PREVENTING DAMAGE OF LOW-K DIELECTRICS DURING PATTERNING

Patent #:	6653045	Issue Dt:	11/25/2003	Application #:	09785609	Filing Dt:	02/16/2001
Publication #:	US20020115017	Pub Dt:	08/22/2002
Title:	RADIATION SENSITIVE SILICON-CONTAINING NEGATIVE RESISTS AND USE THEREOF

Patent #:	6397326	Issue Dt:	05/28/2002	Application #:	09788027	Filing Dt:	02/16/2001
Title:	METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS

Patent #:	6393546	Issue Dt:	05/21/2002	Application #:	09788067	Filing Dt:	02/16/2001
Title:	PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER, CONDITION CODE, AND MULTIMEDIA VALUES

Patent #:	6627926	Issue Dt:	09/30/2003	Application #:	09788631	Filing Dt:	02/16/2001
Publication #:	US20010005052	Pub Dt:	06/28/2001
Title:	METHOD OF DESIGNING AND STRUCTURE FOR VISUAL AND ELECTRICAL TEST OF SEMICONDUCTOR DEVICES

Patent #:	6727922	Issue Dt:	04/27/2004	Application #:	09788635	Filing Dt:	02/21/2001
Publication #:	US20020145630	Pub Dt:	10/10/2002
Title:	GUI FOR REPRESENTING ENTITY MATCHES UTILIZING GRAPHICAL TRANSITIONS PERFORMED DIRECTLY ON THE MATCHING OBJECT

Patent #:	6745373	Issue Dt:	06/01/2004	Application #:	09788925	Filing Dt:	02/20/2001
Publication #:	US20020116690	Pub Dt:	08/22/2002
Title:	METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED CIRCUIT LOGIC DESIGNS

Patent #:	6551114	Issue Dt:	04/22/2003	Application #:	09789141	Filing Dt:	02/20/2001
Publication #:	US20020115325	Pub Dt:	08/22/2002
Title:	SEMICONDUCTOR DEVICE HAVING SIGNAL CONTACTS AND HIGH CURRENT POWER CONTACTS

Patent #:	6372644	Issue Dt:	04/16/2002	Application #:	09789765	Filing Dt:	02/22/2001
Title:	HYDROGEN PASSIVATED SILICON NITRIDE SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING

Patent #:	6615098	Issue Dt:	09/02/2003	Application #:	09789871	Filing Dt:	02/21/2001
Title:	METHOD AND APPARATUS FOR CONTROLLING A TOOL USING A BASELINE CONTROL SCRIPT

Patent #:	6475890	Issue Dt:	11/05/2002	Application #:	09789939	Filing Dt:	02/12/2001
Title:	FABRICATION OF A FIELD EFFECT TRANSISTOR WITH AN UPSIDE DOWN T-SHAPED SEMICONDUCTOR PILLAR IN SOI TECHNOLOGY

Patent #:	6489068	Issue Dt:	12/03/2002	Application #:	09790135	Filing Dt:	02/21/2001
Title:	PROCESS FOR OBSERVING OVERLAY ERRORS ON LITHOGRAPHIC MASKS

Patent #:	6754864	Issue Dt:	06/22/2004	Application #:	09791003	Filing Dt:	02/22/2001
Publication #:	US20020116676	Pub Dt:	08/22/2002
Title:	SYSTEM AND METHOD TO PREDETERMINE A BITMAP OF A SELF-TESTED EMBEDDED ARRAY

Patent #:	6444578	Issue Dt:	09/03/2002	Application #:	09791024	Filing Dt:	02/21/2001
Publication #:	US20020115262	Pub Dt:	08/22/2002
Title:	SELF-ALIGNED SILICIDE PROCESS FOR REDUCTION OF SI CONSUMPTION IN SHALLOW JUNCTION AND THIN SOI ELECTRONIC DEVICES

Patent #:	6785586	Issue Dt:	08/31/2004	Application #:	09791981	Filing Dt:	02/23/2001
Title:	METHOD AND APPARATUS FOR ADAPTIVELY SCHEDULING TOOL MAINTENANCE

Patent #:	6380590	Issue Dt:	04/30/2002	Application #:	09792139	Filing Dt:	02/22/2001
Title:	SOI CHIP HAVING MULTIPLE THRESHOLD VOLTAGE MOSFETS BY USING MULTIPLE CHANNEL MATERIALS AND METHOD OF FABRICATING SAME

Patent #:	6462381	Issue Dt:	10/08/2002	Application #:	09792146	Filing Dt:	02/22/2001
Title:	SILICON-ON-INSULATOR (SOI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE WITH BACKSIDE CONTACT OPENING

Patent #:	6376350	Issue Dt:	04/23/2002	Application #:	09792766	Filing Dt:	02/23/2001
Title:	Method of forming low resistance gate electrode

Patent #:	6475869	Issue Dt:	11/05/2002	Application #:	09793055	Filing Dt:	02/26/2001
Title:	METHOD OF FORMING A DOUBLE GATE TRANSISTOR HAVING AN EPITAXIAL SILICON/GERMANIUM CHANNEL REGION

Patent #:	6610456	Issue Dt:	08/26/2003	Application #:	09794466	Filing Dt:	02/26/2001
Publication #:	US20020164538	Pub Dt:	11/07/2002
Title:	FLUORINE-CONTAINING STYRENE ACRYLATE COPOLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS

Patent #:	6410371	Issue Dt:	06/25/2002	Application #:	09794884	Filing Dt:	02/26/2001
Title:	METHOD OF FABRICATION OF SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER

Patent #:	6445016	Issue Dt:	09/03/2002	Application #:	09795159	Filing Dt:	02/28/2001
Title:	SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION

Patent #:	6677680	Issue Dt:	01/13/2004	Application #:	09795429	Filing Dt:	02/28/2001
Publication #:	US20020117754	Pub Dt:	08/29/2002
Title:	HYBRID LOW-K INTERCONNECT STRUCTURE COMPRISED OF 2 SPIN-ON DIELECTRIC MATERIALS

Patent #:	6710450	Issue Dt:	03/23/2004	Application #:	09795430	Filing Dt:	02/28/2001
Publication #:	US20020117737	Pub Dt:	08/29/2002
Title:	INTERCONNECT STRUCTURE WITH PRECISE CONDUCTOR RESISTANCE AND METHOD TO FORM SAME

Patent #:	6531410	Issue Dt:	03/11/2003	Application #:	09795610	Filing Dt:	02/27/2001
Publication #:	US20020119637	Pub Dt:	08/29/2002
Title:	INTRINSIC DUAL GATE OXIDE MOSFET USING A DAMASCENE GATE PROCESS

Patent #:	6452116	Issue Dt:	09/17/2002	Application #:	09796389	Filing Dt:	02/28/2001
Publication #:	US20010010628	Pub Dt:	08/02/2001
Title:	USE OF BLIND VIAS FOR SOLDERED INTERCONNECTIONS BETWEEN SUBSTRATES AND PRINTED WIRING BOARDS

Patent #:	6617086	Issue Dt:	09/09/2003	Application #:	09796445	Filing Dt:	03/02/2001
Publication #:	US20020123010	Pub Dt:	09/05/2002
Title:	FORMING A PATTERN OF A NEGATIVE PHOTORESIST

Patent #:	6512295	Issue Dt:	01/28/2003	Application #:	09797078	Filing Dt:	03/01/2001
Publication #:	US20020121694	Pub Dt:	09/05/2002
Title:	COUPLED-CAP FLIP CHIP BGA PACKAGE WITH IMPROVED CAP DESIGN FOR REDUCED INTERFACIAL STRESSES

Patent #:	6577515	Issue Dt:	06/10/2003	Application #:	09798550	Filing Dt:	03/02/2001
Publication #:	US20030031036	Pub Dt:	02/13/2003
Title:	ASYMMETRIC POWER SUPPLY INCLUDING A FAST RESPONSE CONVERTER

Patent #:	6573480	Issue Dt:	06/03/2003	Application #:	09800166	Filing Dt:	03/06/2001
Title:	USE OF THERMAL FLOW TO REMOVE SIDE LOBES

Patent #:	6602794	Issue Dt:	08/05/2003	Application #:	09802437	Filing Dt:	03/09/2001
Title:	SILYLATION PROCESS FOR FORMING CONTACTS

Patent #:	6514829	Issue Dt:	02/04/2003	Application #:	09803831	Filing Dt:	03/12/2001
Title:	METHOD OF FABRICATING ABRUPT SOURCE/DRAIN JUNCTIONS

Patent #:	6645679	Issue Dt:	11/11/2003	Application #:	09803853	Filing Dt:	03/12/2001
Title:	ATTENUATED PHASE SHIFT MASK FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A MASK

Patent #:	6429390	Issue Dt:	08/06/2002	Application #:	09804535	Filing Dt:	03/12/2001
Title:	STRUCTURE AND METHOD FOR FORMING THE SAME OF A PRINTED WIRING BOARD HAVING BUILT-IN INSPECTION AIDS

Patent #:	6381689	Issue Dt:	04/30/2002	Application #:	09804768	Filing Dt:	03/13/2001
Publication #:	US20020007450	Pub Dt:	01/17/2002
Title:	LINE-ORIENTED REORDER BUFFER CONFIGURED TO SELECTIVELY STORE A MEMORY OPERATION RESULT IN ONE OF THE PLURALITY OF REORDER BUFFER STORAGE LOCATIONS CORRESPONDING TO THE EXECUTED INSTRUCTION

Patent #:	7087997	Issue Dt:	08/08/2006	Application #:	09805027	Filing Dt:	03/12/2001
Publication #:	US20020127846	Pub Dt:	09/12/2002
Title:	COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER

Patent #:	6434082	Issue Dt:	08/13/2002	Application #:	09805420	Filing Dt:	03/13/2001
Title:	CLOCKED MEMORY DEVICE THAT INCLUDES A PROGRAMMING MECHANISM FOR SETTING WRITE RECOVERY TIME AS A FUNCTION OF THE INPUT CLOCK

Patent #:	6403466	Issue Dt:	06/11/2002	Application #:	09805651	Filing Dt:	03/13/2001
Title:	POST-CMP-CU DEPOSITION AND CMP TO ELIMINATE SURFACE VOIDS

Patent #:	6492708	Issue Dt:	12/10/2002	Application #:	09808381	Filing Dt:	03/14/2001
Publication #:	US20020130386	Pub Dt:	09/19/2002
Title:	INTEGRATED COIL INDUCTORS FOR IC DEVICES

Patent #:	6685983	Issue Dt:	02/03/2004	Application #:	09808724	Filing Dt:	03/14/2001
Publication #:	US20020131246	Pub Dt:	09/19/2002
Title:	DEFECT-FREE DIELECTRIC COATINGS AND PREPARATION THEREOF USING POLYMERIC NITROGENOUS POROGENS

Patent #:	6670285	Issue Dt:	12/30/2003	Application #:	09808726	Filing Dt:	03/14/2001
Publication #:	US20020130396	Pub Dt:	09/19/2002
Title:	NITROGEN-CONTAINING POLYMERS AS POROGENS IN THE PREPARATION OF HIGHLY POROUS, LOW DIELECTRIC CONSTANT MATERIALS

100

Patent #:	6744101	Issue Dt:	06/01/2004	Application #:	09808896	Filing Dt:	03/15/2001
Publication #:	US20010017390	Pub Dt:	08/30/2001
Title:	NON-UNIFORM GATE/DIELECTRIC FIELD EFFECT TRANSISTOR

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

Search Results as of: 05/15/2024 03:35 PM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6