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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 130 of 146
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Patent #:	9343616	Issue Dt:	05/17/2016	Application #:	14711462	Filing Dt:	05/13/2015
Publication #:	US20150249188	Pub Dt:	09/03/2015
Title:	HETEROJUNCTION LIGHT EMITTING DIODE

Patent #:	9263393	Issue Dt:	02/16/2016	Application #:	14711872	Filing Dt:	05/14/2015
Publication #:	US20150243602	Pub Dt:	08/27/2015
Title:	SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS

Patent #:	9786835	Issue Dt:	10/10/2017	Application #:	14712092	Filing Dt:	05/14/2015
Publication #:	US20150243879	Pub Dt:	08/27/2015
Title:	BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE

Patent #:	9490317	Issue Dt:	11/08/2016	Application #:	14712388	Filing Dt:	05/14/2015
Publication #:	US20160336399	Pub Dt:	11/17/2016
Title:	GATE CONTACT STRUCTURE HAVING GATE CONTACT LAYER

Patent #:	9595579	Issue Dt:	03/14/2017	Application #:	14712397	Filing Dt:	05/14/2015
Publication #:	US20150255539	Pub Dt:	09/10/2015
Title:	DUAL SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR FIELD EFFECT TRANSISTOR (FET)

Patent #:	9385023	Issue Dt:	07/05/2016	Application #:	14712462	Filing Dt:	05/14/2015
Title:	METHOD AND STRUCTURE TO MAKE FINS WITH DIFFERENT FIN HEIGHTS AND NO TOPOGRAPHY

Patent #:	9727685	Issue Dt:	08/08/2017	Application #:	14712830	Filing Dt:	05/14/2015
Publication #:	US20160335389	Pub Dt:	11/17/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR IMPROVED STANDARD CELL DESIGN AND ROUTING FOR IMPROVING STANDARD CELL ROUTABILITY

Patent #:	9172025	Issue Dt:	10/27/2015	Application #:	14713327	Filing Dt:	05/15/2015
Publication #:	US20150249200	Pub Dt:	09/03/2015
Title:	INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE

Patent #:	9599664	Issue Dt:	03/21/2017	Application #:	14713626	Filing Dt:	05/15/2015
Publication #:	US20150247896	Pub Dt:	09/03/2015
Title:	CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES

Patent #:	9548356	Issue Dt:	01/17/2017	Application #:	14714779	Filing Dt:	05/18/2015
Publication #:	US20150255538	Pub Dt:	09/10/2015
Title:	SHALLOW TRENCH ISOLATION STRUCTURES

Patent #:	9324617	Issue Dt:	04/26/2016	Application #:	14715050	Filing Dt:	05/18/2015
Title:	METHODS OF FORMING ELASTICALLY RELAXED SiGe VIRTUAL SUBSTRATES ON BULK SILICON

Patent #:	9362361	Issue Dt:	06/07/2016	Application #:	14715109	Filing Dt:	05/18/2015
Title:	METHODS OF FORMING ELASTICALLY RELAXED SIGE VIRTUAL SUBSTRATES ON BULK SILICON

Patent #:	9530711	Issue Dt:	12/27/2016	Application #:	14715693	Filing Dt:	05/19/2015
Publication #:	US20150255363	Pub Dt:	09/10/2015
Title:	SILICON-ON-INSULATOR HEAT SINK

Patent #:	9362357	Issue Dt:	06/07/2016	Application #:	14716045	Filing Dt:	05/19/2015
Publication #:	US20150249129	Pub Dt:	09/03/2015
Title:	BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS

Patent #:	9190303	Issue Dt:	11/17/2015	Application #:	14716236	Filing Dt:	05/19/2015
Publication #:	US20150279709	Pub Dt:	10/01/2015
Title:	REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING

Patent #:	9620481	Issue Dt:	04/11/2017	Application #:	14716300	Filing Dt:	05/19/2015
Publication #:	US20150262976	Pub Dt:	09/17/2015
Title:	SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES

Patent #:	9639650	Issue Dt:	05/02/2017	Application #:	14716565	Filing Dt:	05/19/2015
Publication #:	US20160342726	Pub Dt:	11/24/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL DESIGN

Patent #:	9548357	Issue Dt:	01/17/2017	Application #:	14716696	Filing Dt:	05/19/2015
Publication #:	US20160020275	Pub Dt:	01/21/2016
Title:	SHALLOW TRENCH ISOLATION STRUCTURE WITH SIGMA CAVITY

Patent #:	10020383	Issue Dt:	07/10/2018	Application #:	14716938	Filing Dt:	05/20/2015
Publication #:	US20160343607	Pub Dt:	11/24/2016
Title:	PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH

Patent #:	9472607	Issue Dt:	10/18/2016	Application #:	14717344	Filing Dt:	05/20/2015
Publication #:	US20150270326	Pub Dt:	09/24/2015
Title:	ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR

Patent #:	9236298	Issue Dt:	01/12/2016	Application #:	14717387	Filing Dt:	05/20/2015
Publication #:	US20150255337	Pub Dt:	09/10/2015
Title:	METHODS FOR FABRICATION INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND ELECTRICAL CONDUCTIVE CONTACT STRUCTURES ON A SAME LEVEL

Patent #:	9478658	Issue Dt:	10/25/2016	Application #:	14717551	Filing Dt:	05/20/2015
Publication #:	US20150255603	Pub Dt:	09/10/2015
Title:	DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER

Patent #:	9281236	Issue Dt:	03/08/2016	Application #:	14718128	Filing Dt:	05/21/2015
Publication #:	US20150255326	Pub Dt:	09/10/2015
Title:	EMBEDDED ON-CHIP SECURITY

Patent #:	9786574	Issue Dt:	10/10/2017	Application #:	14718314	Filing Dt:	05/21/2015
Publication #:	US20160343633	Pub Dt:	11/24/2016
Title:	THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM

Patent #:	9306956	Issue Dt:	04/05/2016	Application #:	14718331	Filing Dt:	05/21/2015
Publication #:	US20150256548	Pub Dt:	09/10/2015
Title:	FILE SYSTEM LEVEL DATA PROTECTION DURING POTENTIAL SECURITY BREACH

Patent #:	NONE	Issue Dt:		Application #:	14718402	Filing Dt:	05/21/2015
Publication #:	US20160343806	Pub Dt:	11/24/2016
Title:	INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING

Patent #:	9484301	Issue Dt:	11/01/2016	Application #:	14718466	Filing Dt:	05/21/2015
Publication #:	US20150255395	Pub Dt:	09/10/2015
Title:	CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING

Patent #:	9553046	Issue Dt:	01/24/2017	Application #:	14718502	Filing Dt:	05/21/2015
Publication #:	US20160343659	Pub Dt:	11/24/2016
Title:	E-FUSE IN SOI CONFIGURATION

Patent #:	9490007	Issue Dt:	11/08/2016	Application #:	14718574	Filing Dt:	05/21/2015
Publication #:	US20160343428	Pub Dt:	11/24/2016
Title:	DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF

Patent #:	10134577	Issue Dt:	11/20/2018	Application #:	14718747	Filing Dt:	05/21/2015
Publication #:	US20160343564	Pub Dt:	11/24/2016
Title:	EDGE TRIM PROCESSES AND RESULTANT STRUCTURES

Patent #:	9514995	Issue Dt:	12/06/2016	Application #:	14718760	Filing Dt:	05/21/2015
Publication #:	US20160343623	Pub Dt:	11/24/2016
Title:	IMPLANT-FREE PUNCH THROUGH DOPING LAYER FORMATION FOR BULK FINFET STRUCTURES

Patent #:	9613181	Issue Dt:	04/04/2017	Application #:	14719424	Filing Dt:	05/22/2015
Publication #:	US20150349120	Pub Dt:	12/03/2015
Title:	SEMICONDUCTOR DEVICE STRUCTURE INCLUDING ACTIVE REGION HAVING AN EXTENSION PORTION

Patent #:	9484430	Issue Dt:	11/01/2016	Application #:	14720328	Filing Dt:	05/22/2015
Publication #:	US20150255574	Pub Dt:	09/10/2015
Title:	BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS

Patent #:	10062618	Issue Dt:	08/28/2018	Application #:	14721402	Filing Dt:	05/26/2015
Publication #:	US20160351453	Pub Dt:	12/01/2016
Title:	METHOD AND STRUCTURE FOR FORMATION OF REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS

Patent #:	9791849	Issue Dt:	10/17/2017	Application #:	14722074	Filing Dt:	05/26/2015
Publication #:	US20160349735	Pub Dt:	12/01/2016
Title:	DEFECT DETECTION PROCESS IN A SEMICONDUCTOR MANUFACTURING ENVIRONMENT

Patent #:	9362230	Issue Dt:	06/07/2016	Application #:	14722302	Filing Dt:	05/27/2015
Title:	METHODS TO FORM CONDUCTIVE THIN FILM STRUCTURES

Patent #:	9397003	Issue Dt:	07/19/2016	Application #:	14722818	Filing Dt:	05/27/2015
Title:	METHOD FOR FORMING SOURCE/DRAIN CONTACTS DURING CMOS INTEGRATION USING CONFINED EPITAXIAL GROWTH TECHNIQUES

Patent #:	9379135	Issue Dt:	06/28/2016	Application #:	14723681	Filing Dt:	05/28/2015
Publication #:	US20150263046	Pub Dt:	09/17/2015
Title:	FINFET SEMICONDUCTOR DEVICE HAVING INCREASED GATE HEIGHT CONTROL

Patent #:	9847213	Issue Dt:	12/19/2017	Application #:	14723703	Filing Dt:	05/28/2015
Publication #:	US20150262795	Pub Dt:	09/17/2015
Title:	VACUUM TRAP

Patent #:	9406717	Issue Dt:	08/02/2016	Application #:	14725151	Filing Dt:	05/29/2015
Publication #:	US20150263064	Pub Dt:	09/17/2015
Title:	PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR

Patent #:	9431507	Issue Dt:	08/30/2016	Application #:	14725392	Filing Dt:	05/29/2015
Publication #:	US20150263120	Pub Dt:	09/17/2015
Title:	REPLACEMENT GATE STRUCTURE WITH LOW-K SIDEWALL SPACER FOR SEMICONDUCTOR DEVICES

Patent #:	9343371	Issue Dt:	05/17/2016	Application #:	14725552	Filing Dt:	05/29/2015
Title:	FABRICATING FIN STRUCTURES WITH DOPED MIDDLE PORTIONS

Patent #:	9391144	Issue Dt:	07/12/2016	Application #:	14725581	Filing Dt:	05/29/2015
Publication #:	US20150287790	Pub Dt:	10/08/2015
Title:	SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON

Patent #:	9318388	Issue Dt:	04/19/2016	Application #:	14725663	Filing Dt:	05/29/2015
Publication #:	US20150294912	Pub Dt:	10/15/2015
Title:	METHODS OF FORMING SUBSTANTIALLY SELF-ALIGNED ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9391180	Issue Dt:	07/12/2016	Application #:	14725755	Filing Dt:	05/29/2015
Publication #:	US20150263129	Pub Dt:	09/17/2015
Title:	HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS

Patent #:	9779960	Issue Dt:	10/03/2017	Application #:	14726712	Filing Dt:	06/01/2015
Publication #:	US20160351411	Pub Dt:	12/01/2016
Title:	HYBRID FIN CUTTING PROCESSES FOR FINFET SEMICONDUCTOR DEVICES

Patent #:	9602271	Issue Dt:	03/21/2017	Application #:	14726945	Filing Dt:	06/01/2015
Publication #:	US20160352500	Pub Dt:	12/01/2016
Title:	SUB-NANOSECOND DISTRIBUTED CLOCK SYNCHRONIZATION USING ALIGNMENT MARKER IN ETHERNET IEEE 1588 PROTOCOL

Patent #:	9455204	Issue Dt:	09/27/2016	Application #:	14727143	Filing Dt:	06/01/2015
Title:	10 NM ALTERNATIVE N/P DOPED FIN FOR SSRW SCHEME

Patent #:	9437496	Issue Dt:	09/06/2016	Application #:	14727219	Filing Dt:	06/01/2015
Title:	MERGED SOURCE DRAIN EPITAXY

Patent #:	9324618	Issue Dt:	04/26/2016	Application #:	14727364	Filing Dt:	06/01/2015
Title:	METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE

Patent #:	9536990	Issue Dt:	01/03/2017	Application #:	14727458	Filing Dt:	06/01/2015
Publication #:	US20160351681	Pub Dt:	12/01/2016
Title:	METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TARGETED THICKNESS FOR THE PATTERNED FIN ETCH MASK

Patent #:	9928335	Issue Dt:	03/27/2018	Application #:	14728100	Filing Dt:	06/02/2015
Publication #:	US20160357898	Pub Dt:	12/08/2016
Title:	DESIGN OF TEMPERATURE-COMPLIANT INTEGRATED CIRCUITS

Patent #:	9576894	Issue Dt:	02/21/2017	Application #:	14729188	Filing Dt:	06/03/2015
Publication #:	US20160358851	Pub Dt:	12/08/2016
Title:	INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME

Patent #:	9865546	Issue Dt:	01/09/2018	Application #:	14729298	Filing Dt:	06/03/2015
Publication #:	US20160358860	Pub Dt:	12/08/2016
Title:	CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME

Patent #:	9553017	Issue Dt:	01/24/2017	Application #:	14729342	Filing Dt:	06/03/2015
Publication #:	US20160218034	Pub Dt:	07/28/2016
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BACK-END-OF-THE-LINE INTERCONNECT STRUCTURES

Patent #:	9443776	Issue Dt:	09/13/2016	Application #:	14729446	Filing Dt:	06/03/2015
Publication #:	US20150262899	Pub Dt:	09/17/2015
Title:	METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY

Patent #:	9754941	Issue Dt:	09/05/2017	Application #:	14729845	Filing Dt:	06/03/2015
Publication #:	US20160358922	Pub Dt:	12/08/2016
Title:	METHOD AND STRUCTURE TO FORM TENSILE STRAINED SIGE FINS AND COMPRESSIVE STRAINED SIGE FINS ON A SAME SUBSTRATE

Patent #:	9768325	Issue Dt:	09/19/2017	Application #:	14730294	Filing Dt:	06/04/2015
Publication #:	US20160359056	Pub Dt:	12/08/2016
Title:	DIODES AND FABRICATION METHODS THEREOF

Patent #:	9496341	Issue Dt:	11/15/2016	Application #:	14730320	Filing Dt:	06/04/2015
Publication #:	US20160359001	Pub Dt:	12/08/2016
Title:	SILICON GERMANIUM FIN

Patent #:	9483782	Issue Dt:	11/01/2016	Application #:	14730375	Filing Dt:	06/04/2015
Publication #:	US20150269640	Pub Dt:	09/24/2015
Title:	Automating Capacity Upgrade on Demand

Patent #:	10058388	Issue Dt:	08/28/2018	Application #:	14730503	Filing Dt:	06/04/2015
Publication #:	US20150265351	Pub Dt:	09/24/2015
Title:	Laser Surgical Apparatus and Methods of its Use Minimizing Damage During the Ablation of Tissue Using a Focused Ultrashort Pulsed Laser Beam Wherein the Slope of Fluence Breakdown is a Function of the Pulse Width

Patent #:	9502301	Issue Dt:	11/22/2016	Application #:	14730614	Filing Dt:	06/04/2015
Publication #:	US20160190014	Pub Dt:	06/30/2016
Title:	FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES

Patent #:	9391174	Issue Dt:	07/12/2016	Application #:	14730735	Filing Dt:	06/04/2015
Title:	METHOD OF UNIFORM FIN RECESSING USING ISOTROPIC ETCH

Patent #:	9349814	Issue Dt:	05/24/2016	Application #:	14730887	Filing Dt:	06/04/2015
Publication #:	US20150270364	Pub Dt:	09/24/2015
Title:	GATE HEIGHT UNIFORMITY IN SEMICONDUCTOR DEVICES

Patent #:	9543216	Issue Dt:	01/10/2017	Application #:	14731480	Filing Dt:	06/05/2015
Publication #:	US20160358826	Pub Dt:	12/08/2016
Title:	INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS

Patent #:	9711503	Issue Dt:	07/18/2017	Application #:	14731569	Filing Dt:	06/05/2015
Publication #:	US20150270262	Pub Dt:	09/24/2015
Title:	GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH

Patent #:	9331202	Issue Dt:	05/03/2016	Application #:	14731876	Filing Dt:	06/05/2015
Publication #:	US20150364595	Pub Dt:	12/17/2015
Title:	REPLACEMENT GATE STRUCTURE ON FINFET DEVICES WITH REDUCED SIZE FIN IN THE CHANNEL REGION

Patent #:	9780178	Issue Dt:	10/03/2017	Application #:	14731960	Filing Dt:	06/05/2015
Publication #:	US20160359009	Pub Dt:	12/08/2016
Title:	METHODS OF FORMING A GATE CONTACT ABOVE AN ACTIVE REGION OF A SEMICONDUCTOR DEVICE

Patent #:	10546854	Issue Dt:	01/28/2020	Application #:	14732038	Filing Dt:	06/05/2015
Publication #:	US20160358908	Pub Dt:	12/08/2016
Title:	METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES BY FORMING A PROTECTION LAYER WITH A NON-UNIFORM THICKNESS

Patent #:	9412660	Issue Dt:	08/09/2016	Application #:	14732078	Filing Dt:	06/05/2015
Title:	METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES THAT INCLUDES RECESSING A CONTACT STRUCTURE

Patent #:	9478651	Issue Dt:	10/25/2016	Application #:	14732680	Filing Dt:	06/06/2015
Publication #:	US20150270380	Pub Dt:	09/24/2015
Title:	BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME

Patent #:	9368420	Issue Dt:	06/14/2016	Application #:	14732689	Filing Dt:	06/06/2015
Publication #:	US20150270187	Pub Dt:	09/24/2015
Title:	FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES

Patent #:	9590001	Issue Dt:	03/07/2017	Application #:	14732835	Filing Dt:	06/08/2015
Publication #:	US20150303229	Pub Dt:	10/22/2015
Title:	CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING

Patent #:	9708508	Issue Dt:	07/18/2017	Application #:	14733235	Filing Dt:	06/08/2015
Publication #:	US20150267084	Pub Dt:	09/24/2015
Title:	SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF

Patent #:	9716036	Issue Dt:	07/25/2017	Application #:	14733398	Filing Dt:	06/08/2015
Publication #:	US20160358852	Pub Dt:	12/08/2016
Title:	ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH

Patent #:	9812359	Issue Dt:	11/07/2017	Application #:	14733445	Filing Dt:	06/08/2015
Publication #:	US20160358821	Pub Dt:	12/08/2016
Title:	THRU-SILICON-VIA STRUCTURES

Patent #:	9977002	Issue Dt:	05/22/2018	Application #:	14734018	Filing Dt:	06/09/2015
Publication #:	US20150268206	Pub Dt:	09/24/2015
Title:	NANOPOROUS STRUCTURES BY REACTIVE ION ETCHING

Patent #:	9276002	Issue Dt:	03/01/2016	Application #:	14734310	Filing Dt:	06/09/2015
Publication #:	US20150294973	Pub Dt:	10/15/2015
Title:	INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET

Patent #:	9501607	Issue Dt:	11/22/2016	Application #:	14734411	Filing Dt:	06/09/2015
Publication #:	US20160364516	Pub Dt:	12/15/2016
Title:	COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS

Patent #:	9601200	Issue Dt:	03/21/2017	Application #:	14734504	Filing Dt:	06/09/2015
Publication #:	US20160365146	Pub Dt:	12/15/2016
Title:	TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE

Patent #:	9570155	Issue Dt:	02/14/2017	Application #:	14734525	Filing Dt:	06/09/2015
Publication #:	US20160365139	Pub Dt:	12/15/2016
Title:	CIRCUIT TO IMPROVE SRAM STABILITY

Patent #:	9466547	Issue Dt:	10/11/2016	Application #:	14734600	Filing Dt:	06/09/2015
Title:	PASSIVATION LAYER TOPOGRAPHY

Patent #:	9240448	Issue Dt:	01/19/2016	Application #:	14734713	Filing Dt:	06/09/2015
Publication #:	US20150311283	Pub Dt:	10/29/2015
Title:	BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE

Patent #:	9853128	Issue Dt:	12/26/2017	Application #:	14735283	Filing Dt:	06/10/2015
Publication #:	US20160365451	Pub Dt:	12/15/2016
Title:	DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE

Patent #:	9406545	Issue Dt:	08/02/2016	Application #:	14735466	Filing Dt:	06/10/2015
Publication #:	US20150279723	Pub Dt:	10/01/2015
Title:	BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES

Patent #:	9613958	Issue Dt:	04/04/2017	Application #:	14735984	Filing Dt:	06/10/2015
Publication #:	US20160365346	Pub Dt:	12/15/2016
Title:	SPACER CHAMFERING GATE STACK SCHEME

Patent #:	9257433	Issue Dt:	02/09/2016	Application #:	14736695	Filing Dt:	06/11/2015
Publication #:	US20150279843	Pub Dt:	10/01/2015
Title:	STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM

Patent #:	9401312	Issue Dt:	07/26/2016	Application #:	14736769	Filing Dt:	06/11/2015
Title:	TSV REDUNDANCY SCHEME AND ARCHITECTURE USING DECODER/ENCODER

Patent #:	9337436	Issue Dt:	05/10/2016	Application #:	14736942	Filing Dt:	06/11/2015
Publication #:	US20150280157	Pub Dt:	10/01/2015
Title:	TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE

Patent #:	9595478	Issue Dt:	03/14/2017	Application #:	14737551	Filing Dt:	06/12/2015
Publication #:	US20160365288	Pub Dt:	12/15/2016
Title:	DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Patent #:	9676075	Issue Dt:	06/13/2017	Application #:	14737915	Filing Dt:	06/12/2015
Publication #:	US20160361791	Pub Dt:	12/15/2016
Title:	METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS

Patent #:	9361921	Issue Dt:	06/07/2016	Application #:	14738025	Filing Dt:	06/12/2015
Publication #:	US20150279397	Pub Dt:	10/01/2015
Title:	TAPE SERVO TRACK WRITE COMPENSATION

Patent #:	9553092	Issue Dt:	01/24/2017	Application #:	14738288	Filing Dt:	06/12/2015
Publication #:	US20160365347	Pub Dt:	12/15/2016
Title:	ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs

Patent #:	9530843	Issue Dt:	12/27/2016	Application #:	14738336	Filing Dt:	06/12/2015
Publication #:	US20150279936	Pub Dt:	10/01/2015
Title:	FINFET HAVING AN EPITAXIALLY GROWN SEMICONDUCTOR ON THE FIN IN THE CHANNEL REGION

Patent #:	9953117	Issue Dt:	04/24/2018	Application #:	14738355	Filing Dt:	06/12/2015
Publication #:	US20150278412	Pub Dt:	10/01/2015
Title:	PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY

Patent #:	9431494	Issue Dt:	08/30/2016	Application #:	14739137	Filing Dt:	06/15/2015
Publication #:	US20150311302	Pub Dt:	10/29/2015
Title:	LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR

Patent #:	10134840	Issue Dt:	11/20/2018	Application #:	14739543	Filing Dt:	06/15/2015
Publication #:	US20160365411	Pub Dt:	12/15/2016
Title:	SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS

Patent #:	9653571	Issue Dt:	05/16/2017	Application #:	14739662	Filing Dt:	06/15/2015
Publication #:	US20160365425	Pub Dt:	12/15/2016
Title:	FREESTANDING SPACER HAVING SUB-LITHOGRAPHIC LATERAL DIMENSION AND METHOD OF FORMING SAME

Patent #:	9332628	Issue Dt:	05/03/2016	Application #:	14739703	Filing Dt:	06/15/2015
Publication #:	US20150289361	Pub Dt:	10/08/2015
Title:	MICROELECTRONIC STRUCTURE INCLUDING AIR GAP

100

Patent #:	9741610	Issue Dt:	08/22/2017	Application #:	14740035	Filing Dt:	06/15/2015
Publication #:	US20160365277	Pub Dt:	12/15/2016
Title:	SACRIFICIAL AMORPHOUS SILICON HARD MASK FOR BEOL

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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