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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 131 of 146
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Patent #:	9728615	Issue Dt:	08/08/2017	Application #:	14740872	Filing Dt:	06/16/2015
Publication #:	US20160372559	Pub Dt:	12/22/2016
Title:	FIN SHAPE CONTACTS AND METHODS FOR FORMING FIN SHAPE CONTACTS

Patent #:	9564372	Issue Dt:	02/07/2017	Application #:	14740987	Filing Dt:	06/16/2015
Publication #:	US20160372380	Pub Dt:	12/22/2016
Title:	DUAL LINER SILICIDE

Patent #:	9299847	Issue Dt:	03/29/2016	Application #:	14741169	Filing Dt:	06/16/2015
Publication #:	US20150280006	Pub Dt:	10/01/2015
Title:	PRINTED TRANSISTOR AND FABRICATION METHOD

Patent #:	9368506	Issue Dt:	06/14/2016	Application #:	14741528	Filing Dt:	06/17/2015
Publication #:	US20150333080	Pub Dt:	11/19/2015
Title:	INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY

Patent #:	9431289	Issue Dt:	08/30/2016	Application #:	14741618	Filing Dt:	06/17/2015
Publication #:	US20150287629	Pub Dt:	10/08/2015
Title:	Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion

Patent #:	9508680	Issue Dt:	11/29/2016	Application #:	14741757	Filing Dt:	06/17/2015
Publication #:	US20160372444	Pub Dt:	12/22/2016
Title:	INDUCTION HEATING FOR UNDERFILL REMOVAL AND CHIP REWORK

Patent #:	9496234	Issue Dt:	11/15/2016	Application #:	14741802	Filing Dt:	06/17/2015
Title:	WAFER-LEVEL CHIP-SCALE PACKAGE STRUCTURE UTILIZING CONDUCTIVE POLYMER

Patent #:	9337022	Issue Dt:	05/10/2016	Application #:	14742471	Filing Dt:	06/17/2015
Title:	VIRTUAL RELAXED SUBSTRATE ON EDGE-RELAXED COMPOSITE SEMICONDUCTOR PILLARS

Patent #:	9385126	Issue Dt:	07/05/2016	Application #:	14742537	Filing Dt:	06/17/2015
Publication #:	US20150287727	Pub Dt:	10/08/2015
Title:	SILICON-ON-INSULATOR FINFET WITH BULK SOURCE AND DRAIN

Patent #:	9639645	Issue Dt:	05/02/2017	Application #:	14742801	Filing Dt:	06/18/2015
Publication #:	US20160371413	Pub Dt:	12/22/2016
Title:	INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING

Patent #:	10103060	Issue Dt:	10/16/2018	Application #:	14742895	Filing Dt:	06/18/2015
Publication #:	US20160372389	Pub Dt:	12/22/2016
Title:	TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS

Patent #:	9941179	Issue Dt:	04/10/2018	Application #:	14742917	Filing Dt:	06/18/2015
Publication #:	US20160370311	Pub Dt:	12/22/2016
Title:	CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES

Patent #:	9437588	Issue Dt:	09/06/2016	Application #:	14742935	Filing Dt:	06/18/2015
Title:	MIDDLE-OF-LINE ARCHITECTURE FOR DENSE LIBRARY LAYOUT USING M0 HAND-SHAKE

Patent #:	9299590	Issue Dt:	03/29/2016	Application #:	14743030	Filing Dt:	06/18/2015
Title:	INTEGRATED MICRO-PELTIER COOLING COMPONENTS IN SILICON-ON-INSULATOR (SOI) LAYERS

Patent #:	10103068	Issue Dt:	10/16/2018	Application #:	14743208	Filing Dt:	06/18/2015
Publication #:	US20160370421	Pub Dt:	12/22/2016
Title:	DETECTING A VOID BETWEEN A VIA AND A WIRING LINE

Patent #:	9508560	Issue Dt:	11/29/2016	Application #:	14743511	Filing Dt:	06/18/2015
Publication #:	US20160372334	Pub Dt:	12/22/2016
Title:	SiARC REMOVAL WITH PLASMA ETCH AND FLUORINATED WET CHEMICAL SOLUTION COMBINATION

Patent #:	9892979	Issue Dt:	02/13/2018	Application #:	14744198	Filing Dt:	06/19/2015
Publication #:	US20160372385	Pub Dt:	12/22/2016
Title:	NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD

Patent #:	9779783	Issue Dt:	10/03/2017	Application #:	14744800	Filing Dt:	06/19/2015
Publication #:	US20160372164	Pub Dt:	12/22/2016
Title:	LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

Patent #:	9685553	Issue Dt:	06/20/2017	Application #:	14745547	Filing Dt:	06/22/2015
Publication #:	US20160372598	Pub Dt:	12/22/2016
Title:	GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL

Patent #:	10446644	Issue Dt:	10/15/2019	Application #:	14745704	Filing Dt:	06/22/2015
Publication #:	US20160372582	Pub Dt:	12/22/2016
Title:	DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER

Patent #:	9728603	Issue Dt:	08/08/2017	Application #:	14745764	Filing Dt:	06/22/2015
Publication #:	US20160372548	Pub Dt:	12/22/2016
Title:	BIPOLAR JUNCTION TRANSISTORS WITH DOUBLE-TAPERED EMITTER FINGERS

Patent #:	NONE	Issue Dt:		Application #:	14745800	Filing Dt:	06/22/2015
Publication #:	US20160372396	Pub Dt:	12/22/2016
Title:	CHIP PACKAGE WITH REDUCED TEMPERATURE VARIATION HAVING EMITTER FINGERS FORMATION ACCORDING TO THEIR PROXIMITY TO THE THERMAL PATHWAY STRUCTURE AND A METHOD FOR FORMING A SAME

Patent #:	9461042	Issue Dt:	10/04/2016	Application #:	14746017	Filing Dt:	06/22/2015
Publication #:	US20150287721	Pub Dt:	10/08/2015
Title:	SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY

Patent #:	9576899	Issue Dt:	02/21/2017	Application #:	14746891	Filing Dt:	06/23/2015
Publication #:	US20160379930	Pub Dt:	12/29/2016
Title:	ELECTRICAL FUSE WITH HIGH OFF RESISTANCE

Patent #:	9496377	Issue Dt:	11/15/2016	Application #:	14747525	Filing Dt:	06/23/2015
Publication #:	US20150311324	Pub Dt:	10/29/2015
Title:	SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE

Patent #:	9425269	Issue Dt:	08/23/2016	Application #:	14747604	Filing Dt:	06/23/2015
Title:	REPLACEMENT EMITTER FOR REDUCED CONTACT RESISTANCE

Patent #:	9722057	Issue Dt:	08/01/2017	Application #:	14747668	Filing Dt:	06/23/2015
Publication #:	US20160380088	Pub Dt:	12/29/2016
Title:	BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION

Patent #:	9530798	Issue Dt:	12/27/2016	Application #:	14748355	Filing Dt:	06/24/2015
Publication #:	US20160379999	Pub Dt:	12/29/2016
Title:	HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE

Patent #:	9582621	Issue Dt:	02/28/2017	Application #:	14748595	Filing Dt:	06/24/2015
Publication #:	US20160378897	Pub Dt:	12/29/2016
Title:	MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY

Patent #:	9691971	Issue Dt:	06/27/2017	Application #:	14749165	Filing Dt:	06/24/2015
Publication #:	US20160190207	Pub Dt:	06/30/2016
Title:	INTEGRATED CIRCUITS INCLUDING MAGNETIC TUNNEL JUNCTIONS FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME

Patent #:	9287180	Issue Dt:	03/15/2016	Application #:	14749245	Filing Dt:	06/24/2015
Publication #:	US20150294915	Pub Dt:	10/15/2015
Title:	INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME

Patent #:	9368608	Issue Dt:	06/14/2016	Application #:	14749809	Filing Dt:	06/25/2015
Title:	HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED PERFORMANCE AND BREAKDOWN VOLTAGE

Patent #:	9673091	Issue Dt:	06/06/2017	Application #:	14749817	Filing Dt:	06/25/2015
Publication #:	US20160379878	Pub Dt:	12/29/2016
Title:	STRUCTURE FOR BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION

Patent #:	9536784	Issue Dt:	01/03/2017	Application #:	14749843	Filing Dt:	06/25/2015
Publication #:	US20160379883	Pub Dt:	12/29/2016
Title:	INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC

Patent #:	9606291	Issue Dt:	03/28/2017	Application #:	14749907	Filing Dt:	06/25/2015
Publication #:	US20160377806	Pub Dt:	12/29/2016
Title:	MULTILEVEL WAVEGUIDE STRUCTURE

Patent #:	9690898	Issue Dt:	06/27/2017	Application #:	14749909	Filing Dt:	06/25/2015
Publication #:	US20160378902	Pub Dt:	12/29/2016
Title:	GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS

Patent #:	9748270	Issue Dt:	08/29/2017	Application #:	14750236	Filing Dt:	06/25/2015
Publication #:	US20160379993	Pub Dt:	12/29/2016
Title:	TUNABLE CAPACITOR FOR FDSOI APPLICATIONS

Patent #:	9558995	Issue Dt:	01/31/2017	Application #:	14750741	Filing Dt:	06/25/2015
Publication #:	US20160379873	Pub Dt:	12/29/2016
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	9519747	Issue Dt:	12/13/2016	Application #:	14751222	Filing Dt:	06/26/2015
Publication #:	US20160378903	Pub Dt:	12/29/2016
Title:	DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE

Patent #:	9576852	Issue Dt:	02/21/2017	Application #:	14751380	Filing Dt:	06/26/2015
Publication #:	US20160379881	Pub Dt:	12/29/2016
Title:	INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACTS AND METHODS OF MANUFACTURING THE SAME

Patent #:	9324795	Issue Dt:	04/26/2016	Application #:	14751493	Filing Dt:	06/26/2015
Publication #:	US20150303257	Pub Dt:	10/22/2015
Title:	GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION

Patent #:	9293532	Issue Dt:	03/22/2016	Application #:	14751542	Filing Dt:	06/26/2015
Publication #:	US20150325664	Pub Dt:	11/12/2015
Title:	GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION

Patent #:	9805990	Issue Dt:	10/31/2017	Application #:	14751557	Filing Dt:	06/26/2015
Publication #:	US20160380100	Pub Dt:	12/29/2016
Title:	FDSOI VOLTAGE REFERENCE

Patent #:	9324796	Issue Dt:	04/26/2016	Application #:	14751646	Filing Dt:	06/26/2015
Publication #:	US20150295037	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9299777	Issue Dt:	03/29/2016	Application #:	14751706	Filing Dt:	06/26/2015
Publication #:	US20150295038	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9466723	Issue Dt:	10/11/2016	Application #:	14751718	Filing Dt:	06/26/2015
Title:	LINER AND CAP LAYER FOR PLACEHOLDER SOURCE/DRAIN CONTACT STRUCTURE PLANARIZATION AND REPLACEMENT

Patent #:	9324797	Issue Dt:	04/26/2016	Application #:	14751761	Filing Dt:	06/26/2015
Publication #:	US20150295039	Pub Dt:	10/15/2015
Title:	Gate-All-Around Nanowire MOSFET and Method of Formation

Patent #:	9570344	Issue Dt:	02/14/2017	Application #:	14752210	Filing Dt:	06/26/2015
Publication #:	US20160379872	Pub Dt:	12/29/2016
Title:	METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS

Patent #:	9653367	Issue Dt:	05/16/2017	Application #:	14753198	Filing Dt:	06/29/2015
Publication #:	US20160379900	Pub Dt:	12/29/2016
Title:	METHODS INCLUDING A PROCESSING OF WAFERS AND SPIN COATING TOOL

Patent #:	9583442	Issue Dt:	02/28/2017	Application #:	14753407	Filing Dt:	06/29/2015
Publication #:	US20160379932	Pub Dt:	12/29/2016
Title:	INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER

Patent #:	9391065	Issue Dt:	07/12/2016	Application #:	14753628	Filing Dt:	06/29/2015
Title:	ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE

Patent #:	9761539	Issue Dt:	09/12/2017	Application #:	14753768	Filing Dt:	06/29/2015
Publication #:	US20160379934	Pub Dt:	12/29/2016
Title:	WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE

Patent #:	9287185	Issue Dt:	03/15/2016	Application #:	14753771	Filing Dt:	06/29/2015
Title:	DETERMINING APPROPRIATENESS OF SAMPLING INTEGRATED CIRCUIT TEST DATA IN THE PRESENCE OF MANUFACTURING VARIATIONS

Patent #:	9311217	Issue Dt:	04/12/2016	Application #:	14754013	Filing Dt:	06/29/2015
Publication #:	US20150301922	Pub Dt:	10/22/2015
Title:	ANALYZING COMPUTER PROGRAMS TO IDENTIFY ERRORS

Patent #:	9245791	Issue Dt:	01/26/2016	Application #:	14754190	Filing Dt:	06/29/2015
Publication #:	US20150318208	Pub Dt:	11/05/2015
Title:	METHOD FOR FABRICATING A CONTACT

Patent #:	9659131	Issue Dt:	05/23/2017	Application #:	14754585	Filing Dt:	06/29/2015
Publication #:	US20150317423	Pub Dt:	11/05/2015
Title:	Copper Feature Design for Warpage Control of Substrates

Patent #:	9659941	Issue Dt:	05/23/2017	Application #:	14754958	Filing Dt:	06/30/2015
Publication #:	US20170005101	Pub Dt:	01/05/2017
Title:	INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME

Patent #:	9991202	Issue Dt:	06/05/2018	Application #:	14755440	Filing Dt:	06/30/2015
Publication #:	US20170005037	Pub Dt:	01/05/2017
Title:	METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM

Patent #:	9843303	Issue Dt:	12/12/2017	Application #:	14755522	Filing Dt:	06/30/2015
Publication #:	US20150318839	Pub Dt:	11/05/2015
Title:	SWITCHABLE FILTERS AND DESIGN STRUCTURES

Patent #:	9820248	Issue Dt:	11/14/2017	Application #:	14755621	Filing Dt:	06/30/2015
Publication #:	US20170006567	Pub Dt:	01/05/2017
Title:	NETWORK CLOCK SYNCHRONIZATION

Patent #:	10288645	Issue Dt:	05/14/2019	Application #:	14755733	Filing Dt:	06/30/2015
Publication #:	US20170003318	Pub Dt:	01/05/2017
Title:	ORGANIC PROBE SUBSTRATE

Patent #:	9269787	Issue Dt:	02/23/2016	Application #:	14755862	Filing Dt:	06/30/2015
Publication #:	US20150303275	Pub Dt:	10/22/2015
Title:	BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS

Patent #:	9601379	Issue Dt:	03/21/2017	Application #:	14757996	Filing Dt:	12/23/2015
Title:	METHODS OF FORMING METAL SOURCE/DRAIN CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES WITH GATE ALL AROUND CHANNEL STRUCTURES

Patent #:	9910348	Issue Dt:	03/06/2018	Application #:	14788296	Filing Dt:	06/30/2015
Publication #:	US20170004233	Pub Dt:	01/05/2017
Title:	METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW

Patent #:	9425129	Issue Dt:	08/23/2016	Application #:	14789160	Filing Dt:	07/01/2015
Title:	METHODS FOR FABRICATING CONDUCTIVE VIAS OF CIRCUIT STRUCTURES

Patent #:	10396000	Issue Dt:	08/27/2019	Application #:	14789476	Filing Dt:	07/01/2015
Publication #:	US20170005014	Pub Dt:	01/05/2017
Title:	TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS

Patent #:	9646850	Issue Dt:	05/09/2017	Application #:	14791784	Filing Dt:	07/06/2015
Publication #:	US20170011932	Pub Dt:	01/12/2017
Title:	HIGH-PRESSURE ANNEAL

Patent #:	9362283	Issue Dt:	06/07/2016	Application #:	14793005	Filing Dt:	07/07/2015
Publication #:	US20150311206	Pub Dt:	10/29/2015
Title:	GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND PRODUCTS

Patent #:	9680020	Issue Dt:	06/13/2017	Application #:	14794997	Filing Dt:	07/09/2015
Publication #:	US20170012129	Pub Dt:	01/12/2017
Title:	INCREASED CONTACT AREA FOR FINFETS

Patent #:	9356149	Issue Dt:	05/31/2016	Application #:	14795716	Filing Dt:	07/09/2015
Publication #:	US20160005867	Pub Dt:	01/07/2016
Title:	SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES

Patent #:	9583584	Issue Dt:	02/28/2017	Application #:	14795984	Filing Dt:	07/10/2015
Publication #:	US20170012107	Pub Dt:	01/12/2017
Title:	METHODS FOR PRODUCING INTEGRATED CIRCUITS USING LONG AND SHORT REGIONS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS

Patent #:	9298625	Issue Dt:	03/29/2016	Application #:	14796401	Filing Dt:	07/10/2015
Publication #:	US20150317250	Pub Dt:	11/05/2015
Title:	Read and Write Requests to Partially Cached Files

Patent #:	9455331	Issue Dt:	09/27/2016	Application #:	14796646	Filing Dt:	07/10/2015
Title:	METHOD AND STRUCTURE OF FORMING CONTROLLABLE UNMERGED EPITAXIAL MATERIAL

Patent #:	9831098	Issue Dt:	11/28/2017	Application #:	14797337	Filing Dt:	07/13/2015
Publication #:	US20170018452	Pub Dt:	01/19/2017
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING FLOWABLE CHEMICAL VAPOR DEPOSITION TECHNIQUES WITH LOW-TEMPERATURE THERMAL ANNEALING

Patent #:	9558943	Issue Dt:	01/31/2017	Application #:	14797531	Filing Dt:	07/13/2015
Publication #:	US20170018421	Pub Dt:	01/19/2017
Title:	STRESS RELAXED BUFFER LAYER ON TEXTURED SILICON SURFACE

Patent #:	9324722	Issue Dt:	04/26/2016	Application #:	14797757	Filing Dt:	07/13/2015
Title:	UTILIZATION OF BLOCK-MASK AND CUT-MASK FOR FORMING METAL ROUTING IN AN IC DEVICE

Patent #:	9406651	Issue Dt:	08/02/2016	Application #:	14797804	Filing Dt:	07/13/2015
Publication #:	US20150318269	Pub Dt:	11/05/2015
Title:	Chip Stack with Oleic Acid-Aligned Nanotubes in Thermal Interface Material

Patent #:	9647063	Issue Dt:	05/09/2017	Application #:	14797945	Filing Dt:	07/13/2015
Publication #:	US20150318352	Pub Dt:	11/05/2015
Title:	NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS

Patent #:	9293554	Issue Dt:	03/22/2016	Application #:	14797982	Filing Dt:	07/13/2015
Publication #:	US20150318371	Pub Dt:	11/05/2015
Title:	SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS

Patent #:	9646758	Issue Dt:	05/09/2017	Application #:	14798604	Filing Dt:	07/14/2015
Publication #:	US20170018348	Pub Dt:	01/19/2017
Title:	A METHOD OF FABRICATING INTEGRATED CIRCUIT (IC) DEVICES

Patent #:	9570291	Issue Dt:	02/14/2017	Application #:	14798796	Filing Dt:	07/14/2015
Publication #:	US20170018426	Pub Dt:	01/19/2017
Title:	SEMICONDUCTOR SUBSTRATES AND METHODS FOR PROCESSING SEMICONDUCTOR SUBSTRATES

Patent #:	9318440	Issue Dt:	04/19/2016	Application #:	14799116	Filing Dt:	07/14/2015
Publication #:	US20150357285	Pub Dt:	12/10/2015
Title:	FORMATION OF CARBON-RICH CONTACT LINER MATERIAL

Patent #:	9659786	Issue Dt:	05/23/2017	Application #:	14799297	Filing Dt:	07/14/2015
Publication #:	US20170018437	Pub Dt:	01/19/2017
Title:	GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER

Patent #:	9588044	Issue Dt:	03/07/2017	Application #:	14800940	Filing Dt:	07/16/2015
Publication #:	US20170016822	Pub Dt:	01/19/2017
Title:	INLINE BURIED METAL VOID DETECTION BY SURFACE PLASMON RESONANCE (SPR)

Patent #:	9589851	Issue Dt:	03/07/2017	Application #:	14800970	Filing Dt:	07/16/2015
Publication #:	US20170018463	Pub Dt:	01/19/2017
Title:	Dipole-Based Contact Structure to Reduce Metal-Semiconductor Contact Resistance in MOSFETs

Patent #:	9601512	Issue Dt:	03/21/2017	Application #:	14801519	Filing Dt:	07/16/2015
Publication #:	US20170018573	Pub Dt:	01/19/2017
Title:	SOI-BASED SEMICONDUCTOR DEVICE WITH DYNAMIC THRESHOLD VOLTAGE

Patent #:	9806067	Issue Dt:	10/31/2017	Application #:	14803466	Filing Dt:	07/20/2015
Publication #:	US20170025398	Pub Dt:	01/26/2017
Title:	DIE-DIE STACKING

Patent #:	9337281	Issue Dt:	05/10/2016	Application #:	14803910	Filing Dt:	07/20/2015
Publication #:	US20150325682	Pub Dt:	11/12/2015
Title:	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL

Patent #:	9293363	Issue Dt:	03/22/2016	Application #:	14805443	Filing Dt:	07/21/2015
Publication #:	US20150332959	Pub Dt:	11/19/2015
Title:	METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

Patent #:	9570318	Issue Dt:	02/14/2017	Application #:	14805527	Filing Dt:	07/22/2015
Publication #:	US20170025285	Pub Dt:	01/26/2017
Title:	HIGH-K AND P-TYPE WORK FUNCTION METAL FIRST FABRICATION PROCESS HAVING IMPROVED ANNEALING PROCESS FLOWS

Patent #:	9685457	Issue Dt:	06/20/2017	Application #:	14805827	Filing Dt:	07/22/2015
Publication #:	US20170025442	Pub Dt:	01/26/2017
Title:	METHOD INCLUDING A FORMATION OF A TRANSISTOR AND SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR

Patent #:	9484417	Issue Dt:	11/01/2016	Application #:	14805907	Filing Dt:	07/22/2015
Title:	METHODS OF FORMING DOPED TRANSITION REGIONS OF TRANSISTOR STRUCTURES

Patent #:	9711346	Issue Dt:	07/18/2017	Application #:	14807289	Filing Dt:	07/23/2015
Publication #:	US20170025270	Pub Dt:	01/26/2017
Title:	METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL)

Patent #:	9224639	Issue Dt:	12/29/2015	Application #:	14807480	Filing Dt:	07/23/2015
Publication #:	US20150348833	Pub Dt:	12/03/2015
Title:	Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution

Patent #:	9245981	Issue Dt:	01/26/2016	Application #:	14808914	Filing Dt:	07/24/2015
Publication #:	US20150333156	Pub Dt:	11/19/2015
Title:	DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL

Patent #:	9536035	Issue Dt:	01/03/2017	Application #:	14809698	Filing Dt:	07/27/2015
Publication #:	US20150331988	Pub Dt:	11/19/2015
Title:	WIDE PIN FOR IMPROVED CIRCUIT ROUTING

Patent #:	9431520	Issue Dt:	08/30/2016	Application #:	14810017	Filing Dt:	07/27/2015
Publication #:	US20150333157	Pub Dt:	11/19/2015
Title:	GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES

Patent #:	9601366	Issue Dt:	03/21/2017	Application #:	14810143	Filing Dt:	07/27/2015
Publication #:	US20170033000	Pub Dt:	02/02/2017
Title:	TRENCH FORMATION FOR DIELECTRIC FILLED CUT REGION

Patent #:	9385192	Issue Dt:	07/05/2016	Application #:	14810167	Filing Dt:	07/27/2015
Publication #:	US20150333121	Pub Dt:	11/19/2015
Title:	SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY

100

Patent #:	9385027	Issue Dt:	07/05/2016	Application #:	14811236	Filing Dt:	07/28/2015
Publication #:	US20150332958	Pub Dt:	11/19/2015
Title:	Sublithographic Kelvin Structure Patterned With DSA

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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