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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 133 of 146
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Patent #:	9553080	Issue Dt:	01/24/2017	Application #:	14858373	Filing Dt:	09/18/2015
Title:	METHOD AND PROCESS FOR INTEGRATION OF TSV-MIDDLE IN 3D IC STACKS

Patent #:	9524911	Issue Dt:	12/20/2016	Application #:	14858412	Filing Dt:	09/18/2015
Title:	METHOD FOR CREATING SELF-ALIGNED SDB FOR MINIMUM GATE-JUNCTION PITCH AND EPITAXY FORMATION IN A FIN-TYPE IC DEVICE

Patent #:	9564350	Issue Dt:	02/07/2017	Application #:	14858475	Filing Dt:	09/18/2015
Title:	METHOD AND APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR WAFERS IN A VACUUM POD

Patent #:	9704881	Issue Dt:	07/11/2017	Application #:	14859914	Filing Dt:	09/21/2015
Publication #:	US20170084629	Pub Dt:	03/23/2017
Title:	SEMICONDUCTOR DEVICE WITH REDUCED POLY SPACING EFFECT

Patent #:	9614058	Issue Dt:	04/04/2017	Application #:	14860276	Filing Dt:	09/21/2015
Publication #:	US20160013296	Pub Dt:	01/14/2016
Title:	METHODS OF FORMING LOW DEFECT REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES

Patent #:	9437501	Issue Dt:	09/06/2016	Application #:	14861326	Filing Dt:	09/22/2015
Title:	STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)

Patent #:	9576954	Issue Dt:	02/21/2017	Application #:	14862258	Filing Dt:	09/23/2015
Title:	NEW POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9435852	Issue Dt:	09/06/2016	Application #:	14862587	Filing Dt:	09/23/2015
Title:	INTEGRATED CIRCUIT (IC) TEST STRUCTURE WITH MONITOR CHAIN AND TEST WIRES

Patent #:	9619609	Issue Dt:	04/11/2017	Application #:	14862652	Filing Dt:	09/23/2015
Publication #:	US20170083661	Pub Dt:	03/23/2017
Title:	INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS

Patent #:	9735111	Issue Dt:	08/15/2017	Application #:	14862894	Filing Dt:	09/23/2015
Publication #:	US20170084537	Pub Dt:	03/23/2017
Title:	DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD

Patent #:	9601428	Issue Dt:	03/21/2017	Application #:	14865589	Filing Dt:	09/25/2015
Publication #:	US20160284643	Pub Dt:	09/29/2016
Title:	SEMICONDUCTOR FUSES WITH NANOWIRE FUSE LINKS AND FABRICATION METHODS THEREOF

Patent #:	9268491	Issue Dt:	02/23/2016	Application #:	14866531	Filing Dt:	09/25/2015
Publication #:	US20160019001	Pub Dt:	01/21/2016
Title:	THICK AND THIN DATA VOLUME MANAGEMENT

Patent #:	9691897	Issue Dt:	06/27/2017	Application #:	14867193	Filing Dt:	09/28/2015
Publication #:	US20170092764	Pub Dt:	03/30/2017
Title:	THREE-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH GATE CONTACT IN ACTIVE REGION

Patent #:	9691497	Issue Dt:	06/27/2017	Application #:	14867331	Filing Dt:	09/28/2015
Publication #:	US20170092373	Pub Dt:	03/30/2017
Title:	PROGRAMMABLE DEVICES WITH CURRENT-FACILITATED MIGRATION AND FABRICATION METHODS

Patent #:	9812393	Issue Dt:	11/07/2017	Application #:	14867341	Filing Dt:	09/28/2015
Publication #:	US20170092583	Pub Dt:	03/30/2017
Title:	PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF

Patent #:	10262905	Issue Dt:	04/16/2019	Application #:	14867797	Filing Dt:	09/28/2015
Publication #:	US20160020154	Pub Dt:	01/21/2016
Title:	SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS

Patent #:	9397200	Issue Dt:	07/19/2016	Application #:	14867800	Filing Dt:	09/28/2015
Publication #:	US20160118472	Pub Dt:	04/28/2016
Title:	METHODS OF FORMING 3D DEVICES WITH DIELECTRIC ISOLATION AND A STRAINED CHANNEL REGION

Patent #:	9536981	Issue Dt:	01/03/2017	Application #:	14868414	Filing Dt:	09/29/2015
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9543297	Issue Dt:	01/10/2017	Application #:	14869397	Filing Dt:	09/29/2015
Title:	FIN-FET REPLACEMENT METAL GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Patent #:	9536750	Issue Dt:	01/03/2017	Application #:	14870932	Filing Dt:	09/30/2015
Title:	METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME

Patent #:	9620587	Issue Dt:	04/11/2017	Application #:	14871181	Filing Dt:	09/30/2015
Publication #:	US20160020204	Pub Dt:	01/21/2016
Title:	THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Patent #:	9455316	Issue Dt:	09/27/2016	Application #:	14871289	Filing Dt:	09/30/2015
Publication #:	US20160020277	Pub Dt:	01/21/2016
Title:	THREE-DIMENSIONAL ELECTROSTATIC DISCHARGE SEMICONDUCTOR DEVICE

Patent #:	9431424	Issue Dt:	08/30/2016	Application #:	14872294	Filing Dt:	10/01/2015
Title:	METHOD FOR CREATING METAL GATE RESISTOR IN FDSOL AND RESULTING DEVICE

Patent #:	9972550	Issue Dt:	05/15/2018	Application #:	14873677	Filing Dt:	10/02/2015
Publication #:	US20170098585	Pub Dt:	04/06/2017
Title:	SOURCE/DRAIN EPITAXIAL ELECTRICAL MONITOR

Patent #:	9608096	Issue Dt:	03/28/2017	Application #:	14874039	Filing Dt:	10/02/2015
Publication #:	US20170098699	Pub Dt:	04/06/2017
Title:	IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR

Patent #:	10128114	Issue Dt:	11/13/2018	Application #:	14874623	Filing Dt:	10/05/2015
Publication #:	US20170098544	Pub Dt:	04/06/2017
Title:	AMORPHIZATION INDUCED METAL-SILICON CONTACT FORMATION

Patent #:	9754911	Issue Dt:	09/05/2017	Application #:	14875032	Filing Dt:	10/05/2015
Publication #:	US20170098623	Pub Dt:	04/06/2017
Title:	IC STRUCTURE WITH ANGLED INTERCONNECT ELEMENTS

Patent #:	9337144	Issue Dt:	05/10/2016	Application #:	14876011	Filing Dt:	10/06/2015
Publication #:	US20160027734	Pub Dt:	01/28/2016
Title:	E-FUSE STRUCTURE WITH METHODS OF FUSING THE SAME AND MONITORING MATERIAL LEAKAGE

Patent #:	9373543	Issue Dt:	06/21/2016	Application #:	14876023	Filing Dt:	10/06/2015
Title:	FORMING INTERCONNECT FEATURES WITH REDUCED SIDEWALL TAPERING

Patent #:	9559009	Issue Dt:	01/31/2017	Application #:	14876212	Filing Dt:	10/06/2015
Publication #:	US20160027700	Pub Dt:	01/28/2016
Title:	GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

Patent #:	9397054	Issue Dt:	07/19/2016	Application #:	14876889	Filing Dt:	10/07/2015
Publication #:	US20160027744	Pub Dt:	01/28/2016
Title:	A SEMICONDUCTOR STRUCTURE WITH AN INTERCONNECT LEVEL HAVING A CONDUCTIVE PAD AND METALLIC STRUCTURE SUCH AS A BASE OF A CRACKSTOP

Patent #:	9691787	Issue Dt:	06/27/2017	Application #:	14878332	Filing Dt:	10/08/2015
Publication #:	US20170104011	Pub Dt:	04/13/2017
Title:	CO-FABRICATED BULK DEVICES AND SEMICONDUCTOR-ON-INSULATOR DEVICES

Patent #:	9478625	Issue Dt:	10/25/2016	Application #:	14878440	Filing Dt:	10/08/2015
Title:	METAL RESISTOR USING FINFET-BASED REPLACEMENT GATE PROCESS

Patent #:	9818873	Issue Dt:	11/14/2017	Application #:	14879220	Filing Dt:	10/09/2015
Publication #:	US20170104100	Pub Dt:	04/13/2017
Title:	FORMING STRESSED EPITAXIAL LAYERS BETWEEN GATES SEPARATED BY DIFFERENT PITCHES

Patent #:	9470712	Issue Dt:	10/18/2016	Application #:	14879645	Filing Dt:	10/09/2015
Title:	APPARATUS AND METHOD FOR ATOMIC FORCE PROBING/SEM NANO-PROBING/SCANNING PROBE MICROSCOPY AND COLLIMATED ION MILLING

Patent #:	10622457	Issue Dt:	04/14/2020	Application #:	14879968	Filing Dt:	10/09/2015
Publication #:	US20170104082	Pub Dt:	04/13/2017
Title:	FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS

Patent #:	9397175	Issue Dt:	07/19/2016	Application #:	14881766	Filing Dt:	10/13/2015
Publication #:	US20160035841	Pub Dt:	02/04/2016
Title:	MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS

Patent #:	9852954	Issue Dt:	12/26/2017	Application #:	14882640	Filing Dt:	10/14/2015
Publication #:	US20160035630	Pub Dt:	02/04/2016
Title:	METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14882869	Filing Dt:	10/14/2015
Publication #:	US20170110376	Pub Dt:	04/20/2017
Title:	STRUCTURES WITH THINNED DIELECTRIC MATERIAL

Patent #:	9570588	Issue Dt:	02/14/2017	Application #:	14883045	Filing Dt:	10/14/2015
Publication #:	US20160190289	Pub Dt:	06/30/2016
Title:	METHODS OF FORMING TRANSISTOR STRUCTURES INCLUDING FORMING CHANNEL MATERIAL AFTER FORMATION PROCESSES TO PREVENT DAMAGE TO THE CHANNEL MATERIAL

Patent #:	9349840	Issue Dt:	05/24/2016	Application #:	14883049	Filing Dt:	10/14/2015
Publication #:	US20160035863	Pub Dt:	02/04/2016
Title:	METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

Patent #:	9331037	Issue Dt:	05/03/2016	Application #:	14886177	Filing Dt:	10/19/2015
Publication #:	US20160043048	Pub Dt:	02/11/2016
Title:	PREVENTING MISSHAPED SOLDER BALLS

Patent #:	9589806	Issue Dt:	03/07/2017	Application #:	14886424	Filing Dt:	10/19/2015
Title:	INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME

Patent #:	10436837	Issue Dt:	10/08/2019	Application #:	14886739	Filing Dt:	10/19/2015
Publication #:	US20170108549	Pub Dt:	04/20/2017
Title:	AUTO TEST GROUPING/CLOCK SEQUENCING FOR AT-SPEED TEST

Patent #:	9660027	Issue Dt:	05/23/2017	Application #:	14887572	Filing Dt:	10/20/2015
Publication #:	US20170110539	Pub Dt:	04/20/2017
Title:	EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR

Patent #:	9735242	Issue Dt:	08/15/2017	Application #:	14887927	Filing Dt:	10/20/2015
Publication #:	US20170110549	Pub Dt:	04/20/2017
Title:	SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

Patent #:	9633948	Issue Dt:	04/25/2017	Application #:	14887984	Filing Dt:	10/20/2015
Publication #:	US20160111374	Pub Dt:	04/21/2016
Title:	LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER

Patent #:	9735154	Issue Dt:	08/15/2017	Application #:	14918012	Filing Dt:	10/20/2015
Publication #:	US20160043081	Pub Dt:	02/11/2016
Title:	SEMICONDUCTOR STRUCTURE HAVING GAP FILL DIELECTRIC LAYER DISPOSED BETWEEN FINS

Patent #:	9711513	Issue Dt:	07/18/2017	Application #:	14918048	Filing Dt:	10/20/2015
Publication #:	US20170047336	Pub Dt:	02/16/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF

Patent #:	9761329	Issue Dt:	09/12/2017	Application #:	14918149	Filing Dt:	10/20/2015
Publication #:	US20170110205	Pub Dt:	04/20/2017
Title:	BUILT-IN SELF-TEST (BIST) CIRCUIT AND ASSOCIATED BIST METHOD FOR EMBEDDED MEMORIES

Patent #:	9614003	Issue Dt:	04/04/2017	Application #:	14918736	Filing Dt:	10/21/2015
Publication #:	US20170117322	Pub Dt:	04/27/2017
Title:	METHOD OF FORMING A MEMORY DEVICE STRUCTURE AND MEMORY DEVICE STRUCTURE

Patent #:	10049570	Issue Dt:	08/14/2018	Application #:	14918776	Filing Dt:	10/21/2015
Publication #:	US20170116849	Pub Dt:	04/27/2017
Title:	CONTROLLING RIGHT-OF-WAY FOR PRIORITY VEHICLES

Patent #:	9875905	Issue Dt:	01/23/2018	Application #:	14920179	Filing Dt:	10/22/2015
Publication #:	US20170117156	Pub Dt:	04/27/2017
Title:	FINFET DEVICES HAVING FINS WITH A TAPERED CONFIGURATION AND METHODS OF FABRICATING THE SAME

Patent #:	10032884	Issue Dt:	07/24/2018	Application #:	14920354	Filing Dt:	10/22/2015
Publication #:	US20170117274	Pub Dt:	04/27/2017
Title:	UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

Patent #:	10228685	Issue Dt:	03/12/2019	Application #:	14920376	Filing Dt:	10/22/2015
Publication #:	US20170115658	Pub Dt:	04/27/2017
Title:	Use of Multivariate Models to Control Manufacturing Operations

Patent #:	9722045	Issue Dt:	08/01/2017	Application #:	14921434	Filing Dt:	10/23/2015
Publication #:	US20170117387	Pub Dt:	04/27/2017
Title:	BUFFER LAYER FOR MODULATING Vt ACROSS DEVICES

Patent #:	9740815	Issue Dt:	08/22/2017	Application #:	14922256	Filing Dt:	10/26/2015
Publication #:	US20170116367	Pub Dt:	04/27/2017
Title:	ELECTROMIGRATION-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS

Patent #:	9397191	Issue Dt:	07/19/2016	Application #:	14922308	Filing Dt:	10/26/2015
Publication #:	US20160056265	Pub Dt:	02/25/2016
Title:	METHODS OF MAKING A SELF-ALIGNED CHANNEL DRIFT DEVICE

Patent #:	9390769	Issue Dt:	07/12/2016	Application #:	14922323	Filing Dt:	10/26/2015
Title:	SENSE AMPLIFIERS AND MULTIPLEXED LATCHES

Patent #:	10078107	Issue Dt:	09/18/2018	Application #:	14924439	Filing Dt:	10/27/2015
Publication #:	US20170115337	Pub Dt:	04/27/2017
Title:	WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR ETCH BIAS

Patent #:	9362284	Issue Dt:	06/07/2016	Application #:	14924486	Filing Dt:	10/27/2015
Publication #:	US20160049400	Pub Dt:	02/18/2016
Title:	THRESHOLD VOLTAGE CONTROL FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9570615	Issue Dt:	02/14/2017	Application #:	14924925	Filing Dt:	10/28/2015
Publication #:	US20160049514	Pub Dt:	02/18/2016
Title:	GATE STACK AND CONTACT STRUCTURE

Patent #:	9947774	Issue Dt:	04/17/2018	Application #:	14925630	Filing Dt:	10/28/2015
Publication #:	US20170125551	Pub Dt:	05/04/2017
Title:	FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING

Patent #:	9660040	Issue Dt:	05/23/2017	Application #:	14926657	Filing Dt:	10/29/2015
Publication #:	US20160049481	Pub Dt:	02/18/2016
Title:	TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS

Patent #:	9754903	Issue Dt:	09/05/2017	Application #:	14926880	Filing Dt:	10/29/2015
Publication #:	US20170125361	Pub Dt:	05/04/2017
Title:	SEMICONDUCTOR STRUCTURE WITH ANTI-EFUSE DEVICE

Patent #:	9741853	Issue Dt:	08/22/2017	Application #:	14926897	Filing Dt:	10/29/2015
Publication #:	US20170125587	Pub Dt:	05/04/2017
Title:	STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES

Patent #:	9570555	Issue Dt:	02/14/2017	Application #:	14926936	Filing Dt:	10/29/2015
Title:	SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

Patent #:	9853110	Issue Dt:	12/26/2017	Application #:	14927765	Filing Dt:	10/30/2015
Publication #:	US20170125530	Pub Dt:	05/04/2017
Title:	METHOD OF FORMING A GATE CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE

Patent #:	9601392	Issue Dt:	03/21/2017	Application #:	14927943	Filing Dt:	10/30/2015
Title:	DEVICE CHARACTERIZATION BY TIME DEPENDENT CHARGING DYNAMICS

Patent #:	10115719	Issue Dt:	10/30/2018	Application #:	14928272	Filing Dt:	10/30/2015
Publication #:	US20160126239	Pub Dt:	05/05/2016
Title:	INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME

Patent #:	9960284	Issue Dt:	05/01/2018	Application #:	14928595	Filing Dt:	10/30/2015
Publication #:	US20170125610	Pub Dt:	05/04/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR

Patent #:	9551674	Issue Dt:	01/24/2017	Application #:	14928605	Filing Dt:	10/30/2015
Title:	METHOD OF PRODUCING AN UN-DISTORTED DARK FIELD STRAIN MAP AT HIGH SPATIAL RESOLUTION THROUGH DARK FIELD ELECTRON HOLOGRAPHY

Patent #:	10199479	Issue Dt:	02/05/2019	Application #:	14928681	Filing Dt:	10/30/2015
Publication #:	US20160056263	Pub Dt:	02/25/2016
Title:	METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE

Patent #:	9923078	Issue Dt:	03/20/2018	Application #:	14928719	Filing Dt:	10/30/2015
Publication #:	US20170125543	Pub Dt:	05/04/2017
Title:	TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS

Patent #:	9530553	Issue Dt:	12/27/2016	Application #:	14929869	Filing Dt:	11/02/2015
Title:	HIGH PERFORMANCE INDUCTOR/TRANSFORMER AND METHODS OF MAKING SUCH INDUCTOR/TRANSFORMER STRUCTURES

Patent #:	9536982	Issue Dt:	01/03/2017	Application #:	14930895	Filing Dt:	11/03/2015
Title:	ETCH STOP FOR AIRGAP PROTECTION

Patent #:	9484255	Issue Dt:	11/01/2016	Application #:	14930933	Filing Dt:	11/03/2015
Title:	HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

Patent #:	9576097	Issue Dt:	02/21/2017	Application #:	14930949	Filing Dt:	11/03/2015
Title:	METHODS FOR CIRCUIT PATTERN LAYOUT DECOMPOSITION

Patent #:	9443976	Issue Dt:	09/13/2016	Application #:	14931409	Filing Dt:	11/03/2015
Publication #:	US20160293757	Pub Dt:	10/06/2016
Title:	INTEGRATED CIRCUIT PRODUCT COMPRISING LATERAL AND VERTICAL FINFET DEVICES

Patent #:	10161915	Issue Dt:	12/25/2018	Application #:	14932372	Filing Dt:	11/04/2015
Publication #:	US20170122913	Pub Dt:	05/04/2017
Title:	IN-SITU CONTACTLESS MONITORING OF PHOTOMASK PELLICLE DEGRADATION

Patent #:	9419101	Issue Dt:	08/16/2016	Application #:	14932394	Filing Dt:	11/04/2015
Title:	MULTI-LAYER SPACER USED IN FINFET

Patent #:	NONE	Issue Dt:		Application #:	14932409	Filing Dt:	11/04/2015
Publication #:	US20160056106	Pub Dt:	02/25/2016
Title:	STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME

Patent #:	10263065	Issue Dt:	04/16/2019	Application #:	14932441	Filing Dt:	11/04/2015
Publication #:	US20170125509	Pub Dt:	05/04/2017
Title:	METAL RESISTOR FORMING METHOD USING ION IMPLANTATION

Patent #:	9673115	Issue Dt:	06/06/2017	Application #:	14933107	Filing Dt:	11/05/2015
Publication #:	US20170133287	Pub Dt:	05/11/2017
Title:	TEST STRUCTURES AND METHOD OF FORMING AN ACCORDING TEST STRUCTURE

Patent #:	9537006	Issue Dt:	01/03/2017	Application #:	14933557	Filing Dt:	11/05/2015
Publication #:	US20160056288	Pub Dt:	02/25/2016
Title:	CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS

Patent #:	9905460	Issue Dt:	02/27/2018	Application #:	14933650	Filing Dt:	11/05/2015
Publication #:	US20170133325	Pub Dt:	05/11/2017
Title:	METHODS OF SELF-FORMING BARRIER FORMATION IN METAL INTERCONNECTION APPLICATIONS

Patent #:	9798088	Issue Dt:	10/24/2017	Application #:	14933668	Filing Dt:	11/05/2015
Publication #:	US20170131476	Pub Dt:	05/11/2017
Title:	BARRIER STRUCTURES FOR UNDERFILL BLOCKOUT REGIONS

Patent #:	NONE	Issue Dt:		Application #:	14934042	Filing Dt:	11/05/2015
Publication #:	US20170133406	Pub Dt:	05/11/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR STACKED CMOS LOGIC CIRCUITS ON FINS

Patent #:	9368513	Issue Dt:	06/14/2016	Application #:	14934369	Filing Dt:	11/06/2015
Publication #:	US20160071886	Pub Dt:	03/10/2016
Title:	HIGHLY CONFORMAL EXTENSION DOPING IN ADVANCED MULTI-GATE DEVICES

Patent #:	9906213	Issue Dt:	02/27/2018	Application #:	14934793	Filing Dt:	11/06/2015
Publication #:	US20170133923	Pub Dt:	05/11/2017
Title:	REDUCING THERMAL RUNAWAY IN INVERTER DEVICES

Patent #:	9443771	Issue Dt:	09/13/2016	Application #:	14935676	Filing Dt:	11/09/2015
Title:	METHODS TO THIN DOWN RMG SIDEWALL LAYERS FOR SCALABILITY OF GATE-LAST PLANAR CMOS AND FINFET TECHNOLOGY

Patent #:	9466505	Issue Dt:	10/11/2016	Application #:	14935767	Filing Dt:	11/09/2015
Publication #:	US20160064236	Pub Dt:	03/03/2016
Title:	METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS

Patent #:	9659862	Issue Dt:	05/23/2017	Application #:	14936582	Filing Dt:	11/09/2015
Publication #:	US20170133319	Pub Dt:	05/11/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES

Patent #:	9548318	Issue Dt:	01/17/2017	Application #:	14936848	Filing Dt:	11/10/2015
Title:	CONNECTING TO BACK-PLATE CONTACTS OR DIODE JUNCTIONS THROUGH A RMG ELECTRODE AND RESULTING DEVICES

Patent #:	9673296	Issue Dt:	06/06/2017	Application #:	14937029	Filing Dt:	11/10/2015
Publication #:	US20160064523	Pub Dt:	03/03/2016
Title:	SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS

Patent #:	9548312	Issue Dt:	01/17/2017	Application #:	14937041	Filing Dt:	11/10/2015
Title:	METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL

Patent #:	9704807	Issue Dt:	07/11/2017	Application #:	14939251	Filing Dt:	11/12/2015
Publication #:	US20170141035	Pub Dt:	05/18/2017
Title:	PATTERN PLACEMENT ERROR COMPENSATION LAYER

Patent #:	9748176	Issue Dt:	08/29/2017	Application #:	14939319	Filing Dt:	11/12/2015
Publication #:	US20170141036	Pub Dt:	05/18/2017
Title:	PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING

Patent #:	9633942	Issue Dt:	04/25/2017	Application #:	14939365	Filing Dt:	11/12/2015
Publication #:	US20170141027	Pub Dt:	05/18/2017
Title:	CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

100

Patent #:	9754829	Issue Dt:	09/05/2017	Application #:	14939464	Filing Dt:	11/12/2015
Publication #:	US20170140985	Pub Dt:	05/18/2017
Title:	SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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