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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 134 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
9472558
Issue Dt:
10/18/2016
Application #:
14940499
Filing Dt:
11/13/2015
Title:
SEMICONDUCTOR STRUCTURES WITH STACKED NON-PLANAR FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE STRUCTURES
2
Patent #:
9799767
Issue Dt:
10/24/2017
Application #:
14940597
Filing Dt:
11/13/2015
Publication #:
US20170141226
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS AND NMOS FINFET DEVICES ON CMOS BASED INTEGRATED CIRCUIT PRODUCTS
3
Patent #:
9748387
Issue Dt:
08/29/2017
Application #:
14940655
Filing Dt:
11/13/2015
Publication #:
US20170141227
Pub Dt:
05/18/2017
Title:
METHODS OF FORMING PMOS FINFET DEVICES AND MULTIPLE NMOS FINFET DEVICES WITH DIFFERENT PERFORMANCE CHARACTERISTICS
4
Patent #:
9740101
Issue Dt:
08/22/2017
Application #:
14940857
Filing Dt:
11/13/2015
Publication #:
US20170139324
Pub Dt:
05/18/2017
Title:
ADDITIONS OF ORGANIC SPECIES TO FACILITATE CROSSLINKER REMOVAL DURING PSPI CURE
5
Patent #:
9601383
Issue Dt:
03/21/2017
Application #:
14941885
Filing Dt:
11/16/2015
Title:
FINFET FABRICATION BY FORMING ISOLATION TRENCHES PRIOR TO FIN FORMATION
6
Patent #:
9966182
Issue Dt:
05/08/2018
Application #:
14942311
Filing Dt:
11/16/2015
Publication #:
US20170140865
Pub Dt:
05/18/2017
Title:
MULTI-FREQUENCY INDUCTORS WITH LOW-K DIELECTRIC AREA
7
Patent #:
9412616
Issue Dt:
08/09/2016
Application #:
14942448
Filing Dt:
11/16/2015
Title:
METHODS OF FORMING SINGLE AND DOUBLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS
8
Patent #:
9798244
Issue Dt:
10/24/2017
Application #:
14943086
Filing Dt:
11/17/2015
Publication #:
US20170139330
Pub Dt:
05/18/2017
Title:
METHODS, APPARATUS, AND SYSTEMS FOR MINIMIZING DEFECTIVITY IN TOP-COAT-FREE LITHOGRAPHY AND IMPROVING RETICLE CD UNIFORMITY
9
Patent #:
9484306
Issue Dt:
11/01/2016
Application #:
14943663
Filing Dt:
11/17/2015
Title:
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
10
Patent #:
9502308
Issue Dt:
11/22/2016
Application #:
14944659
Filing Dt:
11/18/2015
Title:
METHODS FOR FORMING TRANSISTOR DEVICES WITH DIFFERENT SOURCE/DRAIN CONTACT LINERS AND THE RESULTING DEVICES
11
Patent #:
9484459
Issue Dt:
11/01/2016
Application #:
14944833
Filing Dt:
11/18/2015
Publication #:
US20160071978
Pub Dt:
03/10/2016
Title:
PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER
12
Patent #:
10191108
Issue Dt:
01/29/2019
Application #:
14945520
Filing Dt:
11/19/2015
Publication #:
US20170146592
Pub Dt:
05/25/2017
Title:
ON-CHIP SENSOR FOR MONITORING ACTIVE CIRCUITS ON INTEGRATED CIRCUIT (IC) CHIPS
13
Patent #:
9767240
Issue Dt:
09/19/2017
Application #:
14945530
Filing Dt:
11/19/2015
Publication #:
US20170147727
Pub Dt:
05/25/2017
Title:
TEMPERATURE-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS
14
Patent #:
9607973
Issue Dt:
03/28/2017
Application #:
14946162
Filing Dt:
11/19/2015
Title:
METHOD FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
15
Patent #:
9553061
Issue Dt:
01/24/2017
Application #:
14946208
Filing Dt:
11/19/2015
Title:
WIRING BOND PAD STRUCTURES
16
Patent #:
9679807
Issue Dt:
06/13/2017
Application #:
14948214
Filing Dt:
11/20/2015
Publication #:
US20170148669
Pub Dt:
05/25/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
17
Patent #:
9368453
Issue Dt:
06/14/2016
Application #:
14948476
Filing Dt:
11/23/2015
Publication #:
US20160079180
Pub Dt:
03/17/2016
Title:
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
18
Patent #:
9590028
Issue Dt:
03/07/2017
Application #:
14948587
Filing Dt:
11/23/2015
Publication #:
US20160079342
Pub Dt:
03/17/2016
Title:
METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
19
Patent #:
9520395
Issue Dt:
12/13/2016
Application #:
14949481
Filing Dt:
11/23/2015
Publication #:
US20160079242
Pub Dt:
03/17/2016
Title:
FINFET DEVICES COMPRISING A DIELECTRIC LAYER/CMP STOP LAYER/HARDMASK/ETCH STOP LAYER/GAP-FILL MATERIAL STACK
20
Patent #:
9606604
Issue Dt:
03/28/2017
Application #:
14951544
Filing Dt:
11/25/2015
Title:
ENERGY EFFICIENT HIGH-SPEED LINK AND METHOD TO MAXIMIZE ENERGY SAVINGS ON THE ENERGY EFFICIENT HIGH-SPEED LINK
21
Patent #:
9466538
Issue Dt:
10/11/2016
Application #:
14951634
Filing Dt:
11/25/2015
Title:
METHOD TO ACHIEVE ULTRA-HIGH CHIP-TO-CHIP ALIGNMENT ACCURACY FOR WAFER-TO-WAFER BONDING PROCESS
22
Patent #:
9535807
Issue Dt:
01/03/2017
Application #:
14951815
Filing Dt:
11/25/2015
Publication #:
US20160077939
Pub Dt:
03/17/2016
Title:
RECOVERING FROM UNCORRECTED MEMORY ERRORS
23
Patent #:
9660050
Issue Dt:
05/23/2017
Application #:
14952549
Filing Dt:
11/25/2015
Publication #:
US20170148894
Pub Dt:
05/25/2017
Title:
REPLACEMENT LOW-K SPACER
24
Patent #:
9767300
Issue Dt:
09/19/2017
Application #:
14953426
Filing Dt:
11/30/2015
Publication #:
US20160085983
Pub Dt:
03/24/2016
Title:
MANAGING RESTRICTED TAGGED CONTENT ELEMENTS WITHIN A PUBLISHED MESSAGE
25
Patent #:
9825094
Issue Dt:
11/21/2017
Application #:
14953702
Filing Dt:
11/30/2015
Publication #:
US20170054005
Pub Dt:
02/23/2017
Title:
FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS
26
Patent #:
9484300
Issue Dt:
11/01/2016
Application #:
14953864
Filing Dt:
11/30/2015
Publication #:
US20160093565
Pub Dt:
03/31/2016
Title:
DEVICE RESULTING FROM PRINTING MINIMUM WIDTH SEMICONDUCTOR FEATURES AT NON-MINIMUM PITCH
27
Patent #:
9741847
Issue Dt:
08/22/2017
Application #:
14953874
Filing Dt:
11/30/2015
Publication #:
US20170154994
Pub Dt:
06/01/2017
Title:
METHODS OF FORMING A CONTACT STRUCTURE FOR A VERTICAL CHANNEL SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
28
Patent #:
9520392
Issue Dt:
12/13/2016
Application #:
14954050
Filing Dt:
11/30/2015
Title:
SEMICONDUCTOR DEVICE INCLUDING FINFET AND FIN VARACTOR
29
Patent #:
NONE
Issue Dt:
Application #:
14954053
Filing Dt:
11/30/2015
Publication #:
US20170154763
Pub Dt:
06/01/2017
Title:
MASS SPECTROMETRY SYSTEM AND METHOD FOR CONTAMINANT IDENTIFICATION IN SEMICONDUCTOR FABRICATION
30
Patent #:
NONE
Issue Dt:
Application #:
14954112
Filing Dt:
11/30/2015
Publication #:
US20170154816
Pub Dt:
06/01/2017
Title:
AMORPHOUS METAL INTERCONNECTIONS BY SUBTRACTIVE ETCH
31
Patent #:
9761720
Issue Dt:
09/12/2017
Application #:
14954166
Filing Dt:
11/30/2015
Publication #:
US20170154995
Pub Dt:
06/01/2017
Title:
REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
32
Patent #:
9466567
Issue Dt:
10/11/2016
Application #:
14957842
Filing Dt:
12/03/2015
Publication #:
US20160086886
Pub Dt:
03/24/2016
Title:
NANOWIRE COMPATIBLE E-FUSE
33
Patent #:
9728506
Issue Dt:
08/08/2017
Application #:
14957860
Filing Dt:
12/03/2015
Publication #:
US20170162508
Pub Dt:
06/08/2017
Title:
STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS
34
Patent #:
9653566
Issue Dt:
05/16/2017
Application #:
14958345
Filing Dt:
12/03/2015
Publication #:
US20160087073
Pub Dt:
03/24/2016
Title:
BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION
35
Patent #:
9634017
Issue Dt:
04/25/2017
Application #:
14959382
Filing Dt:
12/04/2015
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF
36
Patent #:
9859382
Issue Dt:
01/02/2018
Application #:
14959825
Filing Dt:
12/04/2015
Publication #:
US20170162656
Pub Dt:
06/08/2017
Title:
INTEGRATED CMOS WAFERS
37
Patent #:
9425108
Issue Dt:
08/23/2016
Application #:
14960378
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
38
Patent #:
9590074
Issue Dt:
03/07/2017
Application #:
14960380
Filing Dt:
12/05/2015
Title:
METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES
39
Patent #:
9659604
Issue Dt:
05/23/2017
Application #:
14961484
Filing Dt:
12/07/2015
Publication #:
US20170162234
Pub Dt:
06/08/2017
Title:
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
40
Patent #:
9773867
Issue Dt:
09/26/2017
Application #:
14962015
Filing Dt:
12/08/2015
Publication #:
US20160093692
Pub Dt:
03/31/2016
Title:
FINFET SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
41
Patent #:
9704971
Issue Dt:
07/11/2017
Application #:
14963397
Filing Dt:
12/09/2015
Publication #:
US20170170291
Pub Dt:
06/15/2017
Title:
EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES
42
Patent #:
9461128
Issue Dt:
10/04/2016
Application #:
14963789
Filing Dt:
12/09/2015
Publication #:
US20160093704
Pub Dt:
03/31/2016
Title:
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
43
Patent #:
NONE
Issue Dt:
Application #:
14964228
Filing Dt:
12/09/2015
Publication #:
US20170170048
Pub Dt:
06/15/2017
Title:
WAFER HANDLER FOR INFRARED LASER RELEASE
44
Patent #:
9571111
Issue Dt:
02/14/2017
Application #:
14964327
Filing Dt:
12/09/2015
Title:
SYSTEM AND METHOD TO SPEED UP PLL LOCK TIME ON SUBSEQUENT CALIBRATIONS VIA STORED BAND VALUES
45
Patent #:
9589850
Issue Dt:
03/07/2017
Application #:
14964746
Filing Dt:
12/10/2015
Title:
METHOD FOR CONTROLLED RECESSING OF MATERIALS IN CAVITIES IN IC DEVICES
46
Patent #:
9570397
Issue Dt:
02/14/2017
Application #:
14964786
Filing Dt:
12/10/2015
Title:
LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
47
Patent #:
9520396
Issue Dt:
12/13/2016
Application #:
14965193
Filing Dt:
12/10/2015
Publication #:
US20160111422
Pub Dt:
04/21/2016
Title:
METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
48
Patent #:
9590082
Issue Dt:
03/07/2017
Application #:
14965267
Filing Dt:
12/10/2015
Title:
INTEGRATION OF HETEROJUNCTION BIPOLAR TRANSISTORS WITH DIFFERENT BASE PROFILES
49
Patent #:
9466651
Issue Dt:
10/11/2016
Application #:
14966161
Filing Dt:
12/11/2015
Publication #:
US20160099297
Pub Dt:
04/07/2016
Title:
FLEXIBLE ACTIVE MATRIX DISPLAY
50
Patent #:
10078183
Issue Dt:
09/18/2018
Application #:
14966781
Filing Dt:
12/11/2015
Publication #:
US20170168242
Pub Dt:
06/15/2017
Title:
WAVEGUIDE STRUCTURES USED IN PHONOTICS CHIP PACKAGING
51
Patent #:
9503106
Issue Dt:
11/22/2016
Application #:
14966881
Filing Dt:
12/11/2015
Title:
FREQUENCY-LOCKED VOLTAGE REGULATED LOOP
52
Patent #:
NONE
Issue Dt:
Application #:
14967755
Filing Dt:
12/14/2015
Publication #:
US20170170016
Pub Dt:
06/15/2017
Title:
MULTIPLE PATTERNING METHOD FOR SUBSTRATE
53
Patent #:
9548381
Issue Dt:
01/17/2017
Application #:
14967946
Filing Dt:
12/14/2015
Title:
METHOD AND STRUCTURE FOR III-V NANOWIRE TUNNEL FETS
54
Patent #:
9524924
Issue Dt:
12/20/2016
Application #:
14967965
Filing Dt:
12/14/2015
Publication #:
US20160111352
Pub Dt:
04/21/2016
Title:
DIELECTRIC COVER FOR A THROUGH SILICON VIA
55
Patent #:
9590056
Issue Dt:
03/07/2017
Application #:
14967983
Filing Dt:
12/14/2015
Publication #:
US20160099321
Pub Dt:
04/07/2016
Title:
SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS
56
Patent #:
9583569
Issue Dt:
02/28/2017
Application #:
14968286
Filing Dt:
12/14/2015
Publication #:
US20160104770
Pub Dt:
04/14/2016
Title:
PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR
57
Patent #:
9666476
Issue Dt:
05/30/2017
Application #:
14969154
Filing Dt:
12/15/2015
Publication #:
US20160099171
Pub Dt:
04/07/2016
Title:
DIMENSION-CONTROLLED VIA FORMATION PROCESSING
58
Patent #:
9595518
Issue Dt:
03/14/2017
Application #:
14969449
Filing Dt:
12/15/2015
Title:
FIN-TYPE METAL-SEMICONDUCTOR RESISTORS AND FABRICATION METHODS THEREOF
59
Patent #:
NONE
Issue Dt:
Application #:
14969772
Filing Dt:
12/15/2015
Publication #:
US20170169934
Pub Dt:
06/15/2017
Title:
PATTERNED MAGNETIC SHIELDS FOR INDUCTORS AND TRANSFORMERS
60
Patent #:
9704962
Issue Dt:
07/11/2017
Application #:
14970661
Filing Dt:
12/16/2015
Publication #:
US20170179248
Pub Dt:
06/22/2017
Title:
HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION
61
Patent #:
9941300
Issue Dt:
04/10/2018
Application #:
14970725
Filing Dt:
12/16/2015
Publication #:
US20170179156
Pub Dt:
06/22/2017
Title:
STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
62
Patent #:
9940986
Issue Dt:
04/10/2018
Application #:
14971644
Filing Dt:
12/16/2015
Publication #:
US20170178704
Pub Dt:
06/22/2017
Title:
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR EFUSES
63
Patent #:
9620380
Issue Dt:
04/11/2017
Application #:
14972804
Filing Dt:
12/17/2015
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING
64
Patent #:
NONE
Issue Dt:
Application #:
14974136
Filing Dt:
12/18/2015
Publication #:
US20170179127
Pub Dt:
06/22/2017
Title:
SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF FABRICATING SAME
65
Patent #:
9640633
Issue Dt:
05/02/2017
Application #:
14974589
Filing Dt:
12/18/2015
Title:
SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
66
Patent #:
10186482
Issue Dt:
01/22/2019
Application #:
14975726
Filing Dt:
12/19/2015
Publication #:
US20160104677
Pub Dt:
04/14/2016
Title:
SELF ALIGNED VIA FUSE
67
Patent #:
9559051
Issue Dt:
01/31/2017
Application #:
14976417
Filing Dt:
12/21/2015
Title:
METHOD FOR MANUFACTURING IN A SEMICONDUCTOR DEVICE A LOW RESISTANCE VIA WITHOUT A BOTTOM LINER
68
Patent #:
9712413
Issue Dt:
07/18/2017
Application #:
14976530
Filing Dt:
12/21/2015
Publication #:
US20160110244
Pub Dt:
04/21/2016
Title:
SYSTEMS AND METHODS FOR MANAGING COMPUTING SYSTEMS UTILIZING AUGMENTED REALITY
69
Patent #:
9793168
Issue Dt:
10/17/2017
Application #:
14977387
Filing Dt:
12/21/2015
Publication #:
US20160111335
Pub Dt:
04/21/2016
Title:
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS
70
Patent #:
9536870
Issue Dt:
01/03/2017
Application #:
14977737
Filing Dt:
12/22/2015
Publication #:
US20160111414
Pub Dt:
04/21/2016
Title:
SCR WITH FIN BODY REGIONS FOR ESD PROTECTION
71
Patent #:
9601513
Issue Dt:
03/21/2017
Application #:
14977899
Filing Dt:
12/22/2015
Title:
SUBSURFACE WIRES OF INTEGRATED CHIP AND METHODS OF FORMING
72
Patent #:
9691654
Issue Dt:
06/27/2017
Application #:
14978650
Filing Dt:
12/22/2015
Publication #:
US20170178953
Pub Dt:
06/22/2017
Title:
METHODS AND DEVICES FOR BACK END OF LINE VIA FORMATION
73
Patent #:
10020224
Issue Dt:
07/10/2018
Application #:
14980320
Filing Dt:
12/28/2015
Publication #:
US20170186682
Pub Dt:
06/29/2017
Title:
SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
74
Patent #:
9953978
Issue Dt:
04/24/2018
Application #:
14981574
Filing Dt:
12/28/2015
Publication #:
US20160118385
Pub Dt:
04/28/2016
Title:
REPLACEMENT GATE STRUCTURES FOR TRANSISTOR DEVICES
75
Patent #:
9583640
Issue Dt:
02/28/2017
Application #:
14982028
Filing Dt:
12/29/2015
Title:
METHOD INCLUDING A FORMATION OF A CONTROL GATE OF A NONVOLATILE MEMORY CELL AND SEMICONDUCTOR STRUCTURE
76
Patent #:
9806025
Issue Dt:
10/31/2017
Application #:
14982097
Filing Dt:
12/29/2015
Publication #:
US20170186693
Pub Dt:
06/29/2017
Title:
SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
77
Patent #:
9627409
Issue Dt:
04/18/2017
Application #:
14982112
Filing Dt:
12/29/2015
Publication #:
US20160300856
Pub Dt:
10/13/2016
Title:
Semiconductor device with thin-film resistor
78
Patent #:
9754951
Issue Dt:
09/05/2017
Application #:
14982228
Filing Dt:
12/29/2015
Publication #:
US20170125432
Pub Dt:
05/04/2017
Title:
SEMICONDUCTOR DEVICE WITH A MEMORY DEVICE AND A HIGH-K METAL GATE TRANSISTOR
79
Patent #:
9978849
Issue Dt:
05/22/2018
Application #:
14982459
Filing Dt:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Pub Dt:
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Title:
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Filing Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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