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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 135 of 146
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Patent #:	10083904	Issue Dt:	09/25/2018	Application #:	14993238	Filing Dt:	01/12/2016
Publication #:	US20170200674	Pub Dt:	07/13/2017
Title:	METHOLODOGY FOR PROFILE CONTROL AND CAPACITANCE REDUCTION

Patent #:	NONE	Issue Dt:		Application #:	14993320	Filing Dt:	01/12/2016
Publication #:	US20170199511	Pub Dt:	07/13/2017
Title:	SIGNAL DETECTION METHOLODOGY FOR FABRICATION CONTROL

Patent #:	10056458	Issue Dt:	08/21/2018	Application #:	14993537	Filing Dt:	01/12/2016
Publication #:	US20170200792	Pub Dt:	07/13/2017
Title:	SILOXANE AND ORGANIC-BASED MOL CONTACT PATTERNING

Patent #:	9741695	Issue Dt:	08/22/2017	Application #:	14994289	Filing Dt:	01/13/2016
Publication #:	US20170200698	Pub Dt:	07/13/2017
Title:	THREE-DIMENSIONAL HYBRID PACKAGING WITH THROUGH-SILICON-VIAS AND TAPE-AUTOMATED-BONDING

Patent #:	9583479	Issue Dt:	02/28/2017	Application #:	14995324	Filing Dt:	01/14/2016
Title:	SEMICONDUCTOR CHARGE PUMP WITH IMBEDDED CAPACITOR

Patent #:	NONE	Issue Dt:		Application #:	14995956	Filing Dt:	01/14/2016
Publication #:	US20160133716	Pub Dt:	05/12/2016
Title:	ALTERNATIVE GATE DIELECTRIC FILMS FOR SILICON GERMANIUM AND GERMANIUM CHANNEL MATERIALS

Patent #:	9520391	Issue Dt:	12/13/2016	Application #:	14996371	Filing Dt:	01/15/2016
Title:	FIELD EFFECT TRANSISTOR HAVING DELAY ELEMENT WITH BACK GATE

Patent #:	9711619	Issue Dt:	07/18/2017	Application #:	15000111	Filing Dt:	01/19/2016
Publication #:	US20170207090	Pub Dt:	07/20/2017
Title:	STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES

Patent #:	9515026	Issue Dt:	12/06/2016	Application #:	15001584	Filing Dt:	01/20/2016
Publication #:	US20160141252	Pub Dt:	05/19/2016
Title:	METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK

Patent #:	9967825	Issue Dt:	05/08/2018	Application #:	15001763	Filing Dt:	01/20/2016
Publication #:	US20170208544	Pub Dt:	07/20/2017
Title:	ENVIRONMENTALLY AWARE MOBILE COMPUTING DEVICES

Patent #:	10290634	Issue Dt:	05/14/2019	Application #:	15001903	Filing Dt:	01/20/2016
Publication #:	US20170207216	Pub Dt:	07/20/2017
Title:	MULTIPLE THRESHOLD VOLTAGES USING FIN PITCH AND PROFILE

Patent #:	9960118	Issue Dt:	05/01/2018	Application #:	15001956	Filing Dt:	01/20/2016
Publication #:	US20170207175	Pub Dt:	07/20/2017
Title:	CONTACT USING MULTILAYER LINER

Patent #:	9508794	Issue Dt:	11/29/2016	Application #:	15002000	Filing Dt:	01/20/2016
Publication #:	US20160155799	Pub Dt:	06/02/2016
Title:	INCREASED SURFACE AREA OF EPITAXIAL STRUCTURES IN A MIXED N/P TYPE SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS

Patent #:	9852259	Issue Dt:	12/26/2017	Application #:	15002550	Filing Dt:	01/21/2016
Publication #:	US20170212977	Pub Dt:	07/27/2017
Title:	AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF INTEGRATED CIRCUIT (IC) DESIGN BLOCKS

Patent #:	9721059	Issue Dt:	08/01/2017	Application #:	15002808	Filing Dt:	01/21/2016
Publication #:	US20170212978	Pub Dt:	07/27/2017
Title:	POST-LAYOUT THERMAL-AWARE INTEGRATED CIRCUIT PERFORMANCE MODELING

Patent #:	9627389	Issue Dt:	04/18/2017	Application #:	15003304	Filing Dt:	01/21/2016
Title:	METHODS TO FORM MERGED SPACERS FOR USE IN FIN GENERATION IN IC DEVICES

Patent #:	10163558	Issue Dt:	12/25/2018	Application #:	15003532	Filing Dt:	01/21/2016
Publication #:	US20170213637	Pub Dt:	07/27/2017
Title:	VERTICALLY STACKED INDUCTORS AND TRANSFORMERS

Patent #:	9787292	Issue Dt:	10/10/2017	Application #:	15003598	Filing Dt:	01/21/2016
Publication #:	US20170214394	Pub Dt:	07/27/2017
Title:	HIGH PERFORMANCE MULTIPLEXED LATCHES

Patent #:	9589965	Issue Dt:	03/07/2017	Application #:	15004216	Filing Dt:	01/22/2016
Title:	CONTROLLING EPITAXIAL GROWTH OVER EDRAM DEEP TRENCH AND EDRAM SO FORMED

Patent #:	10249502	Issue Dt:	04/02/2019	Application #:	15004751	Filing Dt:	01/22/2016
Publication #:	US20170213739	Pub Dt:	07/27/2017
Title:	LOW RESISTANCE SOURCE DRAIN CONTACT FORMATION WITH TRENCH METASTABLE ALLOYS AND LASER ANNEALING

Patent #:	9972682	Issue Dt:	05/15/2018	Application #:	15004756	Filing Dt:	01/22/2016
Publication #:	US20170213889	Pub Dt:	07/27/2017
Title:	Low Resistance Source Drain Contact Formation

Patent #:	NONE	Issue Dt:		Application #:	15005819	Filing Dt:	01/25/2016
Publication #:	US20170212165	Pub Dt:	07/27/2017
Title:	RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILITY ESTIMATION

Patent #:	9735060	Issue Dt:	08/15/2017	Application #:	15006304	Filing Dt:	01/26/2016
Publication #:	US20170213767	Pub Dt:	07/27/2017
Title:	HYBRID FIN CUT ETCHING PROCESSES FOR PRODUCTS COMPRISING TAPERED AND NON-TAPERED FINFET SEMICONDUCTOR DEVICES

Patent #:	9793216	Issue Dt:	10/17/2017	Application #:	15006426	Filing Dt:	01/26/2016
Publication #:	US20170213792	Pub Dt:	07/27/2017
Title:	FABRICATION OF IC STRUCTURE WITH METAL PLUG

Patent #:	9472460	Issue Dt:	10/18/2016	Application #:	15007494	Filing Dt:	01/27/2016
Title:	UNIFORM DEPTH FIN TRENCH FORMATION

Patent #:	9607993	Issue Dt:	03/28/2017	Application #:	15007937	Filing Dt:	01/27/2016
Title:	CAPACITOR-TRANSISTOR STRAP CONNECTIONS FOR A MEMORY CELL

Patent #:	9508420	Issue Dt:	11/29/2016	Application #:	15009132	Filing Dt:	01/28/2016
Title:	VOLTAGE-AWARE ADAPTIVE STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT

Patent #:	9728649	Issue Dt:	08/08/2017	Application #:	15009906	Filing Dt:	01/29/2016
Publication #:	US20160163879	Pub Dt:	06/09/2016
Title:	SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES, RELATED DESIGN STRUCTURE AND METHOD OF FABRICATION

Patent #:	9721949	Issue Dt:	08/01/2017	Application #:	15010189	Filing Dt:	01/29/2016
Publication #:	US20170221888	Pub Dt:	08/03/2017
Title:	METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET

Patent #:	10090255	Issue Dt:	10/02/2018	Application #:	15010868	Filing Dt:	01/29/2016
Publication #:	US20170221837	Pub Dt:	08/03/2017
Title:	DICING CHANNELS FOR GLASS INTERPOSERS

Patent #:	9841134	Issue Dt:	12/12/2017	Application #:	15011893	Filing Dt:	02/01/2016
Publication #:	US20170219157	Pub Dt:	08/03/2017
Title:	SYSTEM MANAGING MOBILE SENSORS FOR CONTINUOUS MONITORING OF PIPE NETWORKS

Patent #:	9502507	Issue Dt:	11/22/2016	Application #:	15012107	Filing Dt:	02/01/2016
Title:	METHODS OF FORMING STRAINED CHANNEL REGIONS ON FINFET DEVICES

Patent #:	9508848	Issue Dt:	11/29/2016	Application #:	15012184	Filing Dt:	02/01/2016
Title:	METHODS OF FORMING STRAINED CHANNEL REGIONS ON FINFET DEVICES BY PERFORMING A HEATING PROCESS ON A HEAT-EXPANDABLE MATERIAL

Patent #:	9760673	Issue Dt:	09/12/2017	Application #:	15012331	Filing Dt:	02/01/2016
Publication #:	US20170220727	Pub Dt:	08/03/2017
Title:	Application specific integrated circuit (ASIC) test screens and selection of such screens

Patent #:	9647145	Issue Dt:	05/09/2017	Application #:	15012563	Filing Dt:	02/01/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR INCREASING JUNCTION ELECTRIC FIELD OF HIGH CURRENT DIODE

Patent #:	9508850	Issue Dt:	11/29/2016	Application #:	15012760	Filing Dt:	02/01/2016
Publication #:	US20160163862	Pub Dt:	06/09/2016
Title:	EPITAXIAL BLOCK LAYER FOR A FIN FIELD EFFECT TRANSISTOR DEVICE

Patent #:	10429414	Issue Dt:	10/01/2019	Application #:	15013106	Filing Dt:	02/02/2016
Publication #:	US20170219631	Pub Dt:	08/03/2017
Title:	MULTIPLE CONTACT PROBE HEAD DISASSEMBLY METHOD AND SYSTEM

Patent #:	9748235	Issue Dt:	08/29/2017	Application #:	15013169	Filing Dt:	02/02/2016
Publication #:	US20170221889	Pub Dt:	08/03/2017
Title:	GATE STACK FOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING SAME

Patent #:	9812447	Issue Dt:	11/07/2017	Application #:	15013393	Filing Dt:	02/02/2016
Publication #:	US20170221887	Pub Dt:	08/03/2017
Title:	BIPOLAR JUNCTION TRANSISTORS WITH EXTRINSIC DEVICE REGIONS FREE OF TRENCH ISOLATION

Patent #:	9721948	Issue Dt:	08/01/2017	Application #:	15013411	Filing Dt:	02/02/2016
Publication #:	US20170221882	Pub Dt:	08/03/2017
Title:	SWITCH IMPROVEMENT USING LAYOUT OPTIMIZATION

Patent #:	10069490	Issue Dt:	09/04/2018	Application #:	15013956	Filing Dt:	02/02/2016
Publication #:	US20170222634	Pub Dt:	08/03/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICONDUCTOR WAFER

Patent #:	9735061	Issue Dt:	08/15/2017	Application #:	15014150	Filing Dt:	02/03/2016
Publication #:	US20170221764	Pub Dt:	08/03/2017
Title:	METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING

Patent #:	9673376	Issue Dt:	06/06/2017	Application #:	15014212	Filing Dt:	02/03/2016
Title:	METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE

Patent #:	10041976	Issue Dt:	08/07/2018	Application #:	15014479	Filing Dt:	02/03/2016
Publication #:	US20170219626	Pub Dt:	08/03/2017
Title:	GIMBAL ASSEMBLY TEST SYSTEM AND METHOD

Patent #:	9761526	Issue Dt:	09/12/2017	Application #:	15014759	Filing Dt:	02/03/2016
Publication #:	US20170221831	Pub Dt:	08/03/2017
Title:	INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING

Patent #:	9910124	Issue Dt:	03/06/2018	Application #:	15015176	Filing Dt:	02/04/2016
Publication #:	US20170227622	Pub Dt:	08/10/2017
Title:	APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS

Patent #:	10056306	Issue Dt:	08/21/2018	Application #:	15015478	Filing Dt:	02/04/2016
Publication #:	US20170229358	Pub Dt:	08/10/2017
Title:	TEST STRUCUTRE FOR MONITORING INTERFACE DELAMINATION

Patent #:	9653330	Issue Dt:	05/16/2017	Application #:	15015535	Filing Dt:	02/04/2016
Title:	THRESHOLD VOLTAGE (VT)-TYPE TRANSISTOR SENSITIVE AND/OR FAN-OUT SENSITIVE SELECTIVE VOLTAGE BINNING

Patent #:	9870936	Issue Dt:	01/16/2018	Application #:	15015578	Filing Dt:	02/04/2016
Publication #:	US20160155654	Pub Dt:	06/02/2016
Title:	WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION

Patent #:	9995692	Issue Dt:	06/12/2018	Application #:	15015614	Filing Dt:	02/04/2016
Publication #:	US20160239012	Pub Dt:	08/18/2016
Title:	SYSTEMS AND METHODS OF CONTROLLING A MANUFACTURING PROCESS FOR A MICROELECTRONIC COMPONENT

Patent #:	9852959	Issue Dt:	12/26/2017	Application #:	15017004	Filing Dt:	02/05/2016
Publication #:	US20170229362	Pub Dt:	08/10/2017
Title:	CORROSION RESISTANT CHIP SIDEWALL CONNECTION WITH CRACKSTOP AND HERMETIC SEAL

Patent #:	9947788	Issue Dt:	04/17/2018	Application #:	15019273	Filing Dt:	02/09/2016
Publication #:	US20170229578	Pub Dt:	08/10/2017
Title:	DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION

Patent #:	10490296	Issue Dt:	11/26/2019	Application #:	15019590	Filing Dt:	02/09/2016
Publication #:	US20170229191	Pub Dt:	08/10/2017
Title:	MEMORY BUILT-IN SELF-TEST (MBIST) TEST TIME REDUCTION

Patent #:	9510418	Issue Dt:	11/29/2016	Application #:	15024633	Filing Dt:	03/25/2016
Publication #:	US20160242253	Pub Dt:	08/18/2016
Title:	LIGHT EMITTING DIODE (LED) DIMMER CIRCUIT AND DIMMING METHOD FOR LEDS

Patent #:	9798852	Issue Dt:	10/24/2017	Application #:	15040235	Filing Dt:	02/10/2016
Publication #:	US20160378906	Pub Dt:	12/29/2016
Title:	METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS

Patent #:	9515088	Issue Dt:	12/06/2016	Application #:	15040278	Filing Dt:	02/10/2016
Title:	HIGH DENSITY AND MODULAR CMOS LOGIC BASED ON 3D STACKED, INDEPENDENT-GATE, JUNCTIONLESS FINFETS

Patent #:	9954002	Issue Dt:	04/24/2018	Application #:	15040307	Filing Dt:	02/10/2016
Publication #:	US20160163739	Pub Dt:	06/09/2016
Title:	MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY

Patent #:	9898573	Issue Dt:	02/20/2018	Application #:	15040453	Filing Dt:	02/10/2016
Publication #:	US20170228491	Pub Dt:	08/10/2017
Title:	DESIGN RULE AND PROCESS ASSUMPTION CO-OPTIMIZATION USING FEATURE-SPECIFIC LAYOUT-BASED STATISTICAL ANALYSES

Patent #:	9634084	Issue Dt:	04/25/2017	Application #:	15040477	Filing Dt:	02/10/2016
Title:	CONFORMAL BUFFER LAYER IN SOURCE AND DRAIN REGIONS OF FIN-TYPE TRANSISTORS

Patent #:	9601490	Issue Dt:	03/21/2017	Application #:	15040953	Filing Dt:	02/10/2016
Publication #:	US20160163705	Pub Dt:	06/09/2016
Title:	FINFET WORK FUNCTION METAL FORMATION

Patent #:	9703036	Issue Dt:	07/11/2017	Application #:	15041103	Filing Dt:	02/11/2016
Publication #:	US20160170140	Pub Dt:	06/16/2016
Title:	OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES

Patent #:	9679810	Issue Dt:	06/13/2017	Application #:	15041203	Filing Dt:	02/11/2016
Title:	INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME

Patent #:	9791771	Issue Dt:	10/17/2017	Application #:	15041476	Filing Dt:	02/11/2016
Publication #:	US20170235217	Pub Dt:	08/17/2017
Title:	A PHOTOMASK STRUCTURE WITH AN ETCH STOP LAYER THAT ENABLES REPAIRS OF DETECTED DEFECTS THEREIN AND EXTREME ULTRAVIOLET (EUV) PHOTOLITHOGRAPHY METHODS USING THE PHOTOMASK STRUCTURE

Patent #:	9536992	Issue Dt:	01/03/2017	Application #:	15041581	Filing Dt:	02/11/2016
Publication #:	US20160163821	Pub Dt:	06/09/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF

Patent #:	9698179	Issue Dt:	07/04/2017	Application #:	15042547	Filing Dt:	02/12/2016
Publication #:	US20170040354	Pub Dt:	02/09/2017
Title:	CAPACITOR STRUCTURE AND METHOD OF FORMING A CAPACITOR STRUCTURE

Patent #:	10114919	Issue Dt:	10/30/2018	Application #:	15042815	Filing Dt:	02/12/2016
Publication #:	US20170235865	Pub Dt:	08/17/2017
Title:	PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI

Patent #:	9536989	Issue Dt:	01/03/2017	Application #:	15043917	Filing Dt:	02/15/2016
Title:	FIELD-EFFECT TRANSISTORS WITH SOURCE/DRAIN REGIONS OF REDUCED TOPOGRAPHY

Patent #:	9455199	Issue Dt:	09/27/2016	Application #:	15044219	Filing Dt:	02/16/2016
Title:	METHODS OF FORMING STRAINED AND RELAXED GERMANIUM FINS FOR PMOS AND NMOS FINFET DEVICES, RESPECTIVELY

Patent #:	9786765	Issue Dt:	10/10/2017	Application #:	15044431	Filing Dt:	02/16/2016
Publication #:	US20170236917	Pub Dt:	08/17/2017
Title:	FINFET HAVING NOTCHED FINS AND METHOD OF FORMING SAME

Patent #:	9898572	Issue Dt:	02/20/2018	Application #:	15045466	Filing Dt:	02/17/2016
Publication #:	US20170235867	Pub Dt:	08/17/2017
Title:	METAL LINE LAYOUT BASED ON LINE SHIFTING

Patent #:	9663346	Issue Dt:	05/30/2017	Application #:	15046245	Filing Dt:	02/17/2016
Title:	MEMS-BASED RESONANT FINFET

Patent #:	10322493	Issue Dt:	06/18/2019	Application #:	15046496	Filing Dt:	02/18/2016
Publication #:	US20160158912	Pub Dt:	06/09/2016
Title:	CHEMICAL MECHANICAL POLISHING APPARATUS

Patent #:	9589847	Issue Dt:	03/07/2017	Application #:	15046916	Filing Dt:	02/18/2016
Title:	METAL LAYER TIP TO TIP SHORT

Patent #:	9601187	Issue Dt:	03/21/2017	Application #:	15046983	Filing Dt:	02/18/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF STABILITY-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9673301	Issue Dt:	06/06/2017	Application #:	15047018	Filing Dt:	02/18/2016
Title:	METHODS OF FORMING SPACERS ON FINFET DEVICES

Patent #:	9761480	Issue Dt:	09/12/2017	Application #:	15047137	Filing Dt:	02/18/2016
Publication #:	US20170243782	Pub Dt:	08/24/2017
Title:	METHODS OF FORMING FIELD EFFECT TRANSISTOR (FET) AND NON-FET CIRCUIT ELEMENTS ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

Patent #:	9601188	Issue Dt:	03/21/2017	Application #:	15047139	Filing Dt:	02/18/2016
Title:	METHOD, APPARATUS AND SYSTEM FOR TARGETED HEALING OF STABILITY FAILURES THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9704600	Issue Dt:	07/11/2017	Application #:	15047271	Filing Dt:	02/18/2016
Title:	METHOD, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9916212	Issue Dt:	03/13/2018	Application #:	15047395	Filing Dt:	02/18/2016
Publication #:	US20170242759	Pub Dt:	08/24/2017
Title:	METHOD, APPARATUS, AND SYSTEM FOR TARGETED HEALING OF WRITE FAILS THROUGH BIAS TEMPERATURE INSTABILITY

Patent #:	9842184	Issue Dt:	12/12/2017	Application #:	15047878	Filing Dt:	02/19/2016
Publication #:	US20170076031	Pub Dt:	03/16/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY

Patent #:	9754071	Issue Dt:	09/05/2017	Application #:	15048066	Filing Dt:	02/19/2016
Publication #:	US20170242952	Pub Dt:	08/24/2017
Title:	INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION

Patent #:	10177091	Issue Dt:	01/08/2019	Application #:	15048114	Filing Dt:	02/19/2016
Publication #:	US20170243827	Pub Dt:	08/24/2017
Title:	INTERCONNECT STRUCTURE AND METHOD OF FORMING

Patent #:	9530500	Issue Dt:	12/27/2016	Application #:	15048256	Filing Dt:	02/19/2016
Publication #:	US20160172038	Pub Dt:	06/16/2016
Title:	CONVERTING AN XY TCAM TO A VALUE TCAM

Patent #:	9530691	Issue Dt:	12/27/2016	Application #:	15048280	Filing Dt:	02/19/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR FORMING A DIELECTRIC FIELD FOR DUAL ORIENTATION SELF ALIGNED VIAS

Patent #:	10340177	Issue Dt:	07/02/2019	Application #:	15048493	Filing Dt:	02/19/2016
Publication #:	US20170243783	Pub Dt:	08/24/2017
Title:	DEVICES AND METHODS OF REDUCING DAMAGE DURING BEOL M1 INTEGRATION

Patent #:	9530488	Issue Dt:	12/27/2016	Application #:	15048583	Filing Dt:	02/19/2016
Title:	METHODS, APPARATUS AND SYSTEM DETERMINING DUAL PORT DC CONTENTION MARGIN

Patent #:	9817063	Issue Dt:	11/14/2017	Application #:	15048704	Filing Dt:	02/19/2016
Publication #:	US20170242067	Pub Dt:	08/24/2017
Title:	INTERCONNECT RELIABILITY STRUCTURES

Patent #:	9640402	Issue Dt:	05/02/2017	Application #:	15049351	Filing Dt:	02/22/2016
Title:	METHODS FOR GATE FORMATION IN CIRCUIT STRUCTURES

Patent #:	9773811	Issue Dt:	09/26/2017	Application #:	15049572	Filing Dt:	02/22/2016
Publication #:	US20170243894	Pub Dt:	08/24/2017
Title:	REDUCING ANTENNA EFFECTS IN SOI DEVICES

Patent #:	9761495	Issue Dt:	09/12/2017	Application #:	15050540	Filing Dt:	02/23/2016
Publication #:	US20170243790	Pub Dt:	08/24/2017
Title:	METHODS OF PERFORMING CONCURRENT FIN AND GATE CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

Patent #:	9847333	Issue Dt:	12/19/2017	Application #:	15051420	Filing Dt:	02/23/2016
Publication #:	US20160268260	Pub Dt:	09/15/2016
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Title:	INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME

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Title:	FINFET ELECTRICAL CHARACTERIZATION WITH ENHANCED HALL EFFECT AND PROBE

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Title:	FORMATION OF WORK-FUNCTION LAYERS FOR GATE ELECTRODE USING A GAS CLUSTER ION BEAM

100

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Title:	METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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