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Reel/Frame:	054636/0001			Pages:	911
		Recorded:	11/20/2020
Attorney Dkt #:	37188/13
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 14520
Page 136 of 146
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Patent #:	9577066	Issue Dt:	02/21/2017	Application #:	15054314	Filing Dt:	02/26/2016
Title:	METHODS OF FORMING FINS WITH DIFFERENT FIN HEIGHTS

Patent #:	9748236	Issue Dt:	08/29/2017	Application #:	15054355	Filing Dt:	02/26/2016
Publication #:	US20170250181	Pub Dt:	08/31/2017
Title:	FINFET DEVICE WITH ENLARGED CHANNEL REGIONS

Patent #:	9761285	Issue Dt:	09/12/2017	Application #:	15054553	Filing Dt:	02/26/2016
Publication #:	US20170249976	Pub Dt:	08/31/2017
Title:	SENSE AMPLIFIER AND LATCHING SCHEME

Patent #:	9466616	Issue Dt:	10/11/2016	Application #:	15054951	Filing Dt:	02/26/2016
Publication #:	US20160181285	Pub Dt:	06/23/2016
Title:	UNIFORM JUNCTION FORMATION IN FINFETS

Patent #:	10170482	Issue Dt:	01/01/2019	Application #:	15055571	Filing Dt:	02/27/2016
Publication #:	US20170162582	Pub Dt:	06/08/2017
Title:	STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES

Patent #:	9627535	Issue Dt:	04/18/2017	Application #:	15055805	Filing Dt:	02/29/2016
Publication #:	US20160181426	Pub Dt:	06/23/2016
Title:	Semiconductor Devices with an Etch Stop Layer on Gate End-Portions Located above an Isolation Region

Patent #:	9748145	Issue Dt:	08/29/2017	Application #:	15055826	Filing Dt:	02/29/2016
Publication #:	US20170250117	Pub Dt:	08/31/2017
Title:	SEMICONDUCTOR DEVICES WITH VARYING THRESHOLD VOLTAGE AND FABRICATION METHODS THEREOF

Patent #:	9685336	Issue Dt:	06/20/2017	Application #:	15055954	Filing Dt:	02/29/2016
Title:	PROCESS MONITORING FOR GATE CUT MASK

Patent #:	9754792	Issue Dt:	09/05/2017	Application #:	15056513	Filing Dt:	02/29/2016
Publication #:	US20170250088	Pub Dt:	08/31/2017
Title:	FIN CUTTING PROCESS FOR MANUFACTURING FINFET SEMICONDUCTOR DEVICES

Patent #:	9748335	Issue Dt:	08/29/2017	Application #:	15056966	Filing Dt:	02/29/2016
Publication #:	US20170250250	Pub Dt:	08/31/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

Patent #:	9633915	Issue Dt:	04/25/2017	Application #:	15057727	Filing Dt:	03/01/2016
Title:	METHOD OF USING DUMMY PATTERNS FOR OVERLAY TARGET DESIGN AND OVERLAY CONTROL

Patent #:	9905668	Issue Dt:	02/27/2018	Application #:	15057791	Filing Dt:	03/01/2016
Publication #:	US20160181393	Pub Dt:	06/23/2016
Title:	BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION

Patent #:	9576857	Issue Dt:	02/21/2017	Application #:	15058238	Filing Dt:	03/02/2016
Title:	METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION

Patent #:	9978588	Issue Dt:	05/22/2018	Application #:	15058669	Filing Dt:	03/02/2016
Publication #:	US20160181092	Pub Dt:	06/23/2016
Title:	NITRIDE SPACER FOR PROTECTING A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Patent #:	9698269	Issue Dt:	07/04/2017	Application #:	15059793	Filing Dt:	03/03/2016
Publication #:	US20160190324	Pub Dt:	06/30/2016
Title:	CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS

Patent #:	9514942	Issue Dt:	12/06/2016	Application #:	15060009	Filing Dt:	03/03/2016
Title:	METHOD OF FORMING A GATE MASK FOR FABRICATING A STRUCTURE OF GATE LINES

Patent #:	9595583	Issue Dt:	03/14/2017	Application #:	15060052	Filing Dt:	03/03/2016
Publication #:	US20160190255	Pub Dt:	06/30/2016
Title:	METHODS FOR FORMING FinFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE

Patent #:	9871057	Issue Dt:	01/16/2018	Application #:	15060067	Filing Dt:	03/03/2016
Publication #:	US20170256565	Pub Dt:	09/07/2017
Title:	FIELD-EFFECT TRANSISTORS WITH A NON-RELAXED STRAINED CHANNEL

Patent #:	9472464	Issue Dt:	10/18/2016	Application #:	15060691	Filing Dt:	03/04/2016
Title:	METHODS TO UTILIZE MERGED SPACERS FOR USE IN FIN GENERATION IN TAPERED IC DEVICES

Patent #:	9812543	Issue Dt:	11/07/2017	Application #:	15060761	Filing Dt:	03/04/2016
Publication #:	US20170256624	Pub Dt:	09/07/2017
Title:	COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIGHTS AND METHODS OF MANUFACTURING SAME

Patent #:	9647124	Issue Dt:	05/09/2017	Application #:	15060806	Filing Dt:	03/04/2016
Publication #:	US20160190344	Pub Dt:	06/30/2016
Title:	SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS

Patent #:	NONE	Issue Dt:		Application #:	15062257	Filing Dt:	03/07/2016
Publication #:	US20170252785	Pub Dt:	09/07/2017
Title:	IN-SITU EUV COLLECTOR CLEANING UTILIZING A CRYOGENIC PROCESS

Patent #:	NONE	Issue Dt:		Application #:	15062302	Filing Dt:	03/07/2016
Publication #:	US20170255471	Pub Dt:	09/07/2017
Title:	PROCESSOR WITH CONTENT ADDRESSABLE MEMORY (CAM) AND MONITOR COMPONENT

Patent #:	NONE	Issue Dt:		Application #:	15062328	Filing Dt:	03/07/2016
Publication #:	US20170256449	Pub Dt:	09/07/2017
Title:	METHODS OF FORMING CONDUCTIVE STRUCTURES WITH DIFFERENT MATERIAL COMPOSITIONS IN A METALLIZATION LAYER

Patent #:	9859177	Issue Dt:	01/02/2018	Application #:	15062484	Filing Dt:	03/07/2016
Publication #:	US20170256468	Pub Dt:	09/07/2017
Title:	TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE METALIZATION

Patent #:	9634003	Issue Dt:	04/25/2017	Application #:	15063563	Filing Dt:	03/08/2016
Publication #:	US20160225763	Pub Dt:	08/04/2016
Title:	SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS

Patent #:	9478662	Issue Dt:	10/25/2016	Application #:	15063604	Filing Dt:	03/08/2016
Publication #:	US20160268415	Pub Dt:	09/15/2016
Title:	GATE AND SOURCE/DRAIN CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE

Patent #:	10014279	Issue Dt:	07/03/2018	Application #:	15064755	Filing Dt:	03/09/2016
Publication #:	US20160190104	Pub Dt:	06/30/2016
Title:	METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES

Patent #:	9673220	Issue Dt:	06/06/2017	Application #:	15065331	Filing Dt:	03/09/2016
Title:	CHIP STRUCTURES WITH DISTRIBUTED WIRING

Patent #:	9786606	Issue Dt:	10/10/2017	Application #:	15066374	Filing Dt:	03/10/2016
Publication #:	US20160190067	Pub Dt:	06/30/2016
Title:	SEMICONDUCTOR STRUCTURES WITH ISOLATED OHMIC TRENCHES AND STAND-ALONE ISOLATION TRENCHES AND RELATED METHOD

Patent #:	9589836	Issue Dt:	03/07/2017	Application #:	15067365	Filing Dt:	03/11/2016
Title:	METHODS OF FORMING RUTHENIUM CONDUCTIVE STRUCTURES IN A METALLIZATION LAYER

Patent #:	9536991	Issue Dt:	01/03/2017	Application #:	15067435	Filing Dt:	03/11/2016
Title:	SINGLE DIFFUSION BREAK STRUCTURE

Patent #:	9543298	Issue Dt:	01/10/2017	Application #:	15067455	Filing Dt:	03/11/2016
Title:	SINGLE DIFFUSION BREAK STRUCTURE AND CUTS LATER METHOD OF MAKING

Patent #:	10236350	Issue Dt:	03/19/2019	Application #:	15067540	Filing Dt:	03/11/2016
Publication #:	US20170263715	Pub Dt:	09/14/2017
Title:	METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW

Patent #:	9818651	Issue Dt:	11/14/2017	Application #:	15067953	Filing Dt:	03/11/2016
Publication #:	US20170263506	Pub Dt:	09/14/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

Patent #:	9933577	Issue Dt:	04/03/2018	Application #:	15068059	Filing Dt:	03/11/2016
Publication #:	US20170261693	Pub Dt:	09/14/2017
Title:	PHOTONICS CHIP

Patent #:	9484258	Issue Dt:	11/01/2016	Application #:	15071247	Filing Dt:	03/16/2016
Title:	METHOD FOR PRODUCING SELF-ALIGNED VIAS

Patent #:	9478462	Issue Dt:	10/25/2016	Application #:	15071255	Filing Dt:	03/16/2016
Title:	SAV USING SELECTIVE SAQP/SADP

Patent #:	9698241	Issue Dt:	07/04/2017	Application #:	15071600	Filing Dt:	03/16/2016
Title:	INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATES AND METHODS FOR FABRICATING THE SAME

Patent #:	9716136	Issue Dt:	07/25/2017	Application #:	15071641	Filing Dt:	03/16/2016
Title:	EMBEDDED POLYSILICON RESISTORS WITH CRYSTALLIZATION BARRIERS

Patent #:	9864831	Issue Dt:	01/09/2018	Application #:	15071890	Filing Dt:	03/16/2016
Publication #:	US20160196381	Pub Dt:	07/07/2016
Title:	METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF

Patent #:	9698262	Issue Dt:	07/04/2017	Application #:	15072130	Filing Dt:	03/16/2016
Publication #:	US20160276478	Pub Dt:	09/22/2016
Title:	VERTICAL FIN FIELD-EFFECT SEMICONDUCTOR DEVICE

Patent #:	9859125	Issue Dt:	01/02/2018	Application #:	15072626	Filing Dt:	03/17/2016
Publication #:	US20170271163	Pub Dt:	09/21/2017
Title:	BLOCK PATTERNING METHOD ENABLING MERGED SPACE IN SRAM WITH HETEROGENEOUS MANDREL

Patent #:	NONE	Issue Dt:		Application #:	15072655	Filing Dt:	03/17/2016
Publication #:	US20170271285	Pub Dt:	09/21/2017
Title:	INTEGRATED CIRCUIT PACKAGE USING POLYMER-SOLDER BALL STRUCTURES AND FORMING METHODS

Patent #:	9406767	Issue Dt:	08/02/2016	Application #:	15073050	Filing Dt:	03/17/2016
Title:	POC PROCESS FLOW FOR CONFORMAL RECESS FILL

Patent #:	9647093	Issue Dt:	05/09/2017	Application #:	15073065	Filing Dt:	03/17/2016
Publication #:	US20170062590	Pub Dt:	03/02/2017
Title:	FIN CUT FOR TAPER DEVICE

Patent #:	9620505	Issue Dt:	04/11/2017	Application #:	15073100	Filing Dt:	03/17/2016
Publication #:	US20160197072	Pub Dt:	07/07/2016
Title:	SEMICONDUCTOR DEVICE WITH DIFFERENT FIN SETS

Patent #:	9966457	Issue Dt:	05/08/2018	Application #:	15073740	Filing Dt:	03/18/2016
Publication #:	US20170271483	Pub Dt:	09/21/2017
Title:	TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA

Patent #:	9508853	Issue Dt:	11/29/2016	Application #:	15073936	Filing Dt:	03/18/2016
Publication #:	US20160204261	Pub Dt:	07/14/2016
Title:	CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON A FINFET DEVICE HAVING A REDUCED SIZE FIN IN THE CHANNEL REGION

Patent #:	9711624	Issue Dt:	07/18/2017	Application #:	15074235	Filing Dt:	03/18/2016
Title:	METHODS FOR DIRECT MEASUREMENT OF PITCH-WALKING IN LITHOGRAPHIC MULTIPLE PATTERNING

Patent #:	9881841	Issue Dt:	01/30/2018	Application #:	15074483	Filing Dt:	03/18/2016
Publication #:	US20160204038	Pub Dt:	07/14/2016
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES

Patent #:	9666589	Issue Dt:	05/30/2017	Application #:	15075352	Filing Dt:	03/21/2016
Title:	FINFET BASED FLASH MEMORY CELL

Patent #:	9768084	Issue Dt:	09/19/2017	Application #:	15075378	Filing Dt:	03/21/2016
Publication #:	US20170271220	Pub Dt:	09/21/2017
Title:	INLINE MONITORING OF TRANSISTOR-TO-TRANSISTOR CRITICAL DIMENSION

Patent #:	9431306	Issue Dt:	08/30/2016	Application #:	15075437	Filing Dt:	03/21/2016
Publication #:	US20160225677	Pub Dt:	08/04/2016
Title:	METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES USING AN OXIDATION-BLOCKING LAYER OF MATERIAL AND BY PERFORMING A FIN-TRIMMING PROCESS

Patent #:	9722053	Issue Dt:	08/01/2017	Application #:	15075557	Filing Dt:	03/21/2016
Title:	METHODS, APPARATUS AND SYSTEM FOR LOCAL ISOLATION FORMATION FOR FINFET DEVICES

Patent #:	9793113	Issue Dt:	10/17/2017	Application #:	15075668	Filing Dt:	03/21/2016
Publication #:	US20170271146	Pub Dt:	09/21/2017
Title:	SEMICONDUCTOR STRUCTURE HAVING INSULATOR PILLARS AND SEMICONDUCTOR MATERIAL ON SUBSTRATE

Patent #:	9716138	Issue Dt:	07/25/2017	Application #:	15075890	Filing Dt:	03/21/2016
Title:	DEVICES AND METHODS FOR DYNAMICALLY TUNABLE BIASING TO BACKPLATES AND WELLS

Patent #:	10020047	Issue Dt:	07/10/2018	Application #:	15076139	Filing Dt:	03/21/2016
Publication #:	US20170270999	Pub Dt:	09/21/2017
Title:	STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH IMPROVED BOOST

Patent #:	9634142	Issue Dt:	04/25/2017	Application #:	15076699	Filing Dt:	03/22/2016
Title:	Method for Improving Boron Diffusion in a Germanium-rich Fin through Germanium Concentration Reduction in Fin S/D Regions by Thermal Mixing

Patent #:	9570552	Issue Dt:	02/14/2017	Application #:	15076842	Filing Dt:	03/22/2016
Title:	FORMING SYMMETRICAL STRESS LINERS FOR STRAINED CMOS VERTICAL NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	9564521	Issue Dt:	02/07/2017	Application #:	15076850	Filing Dt:	03/22/2016
Publication #:	US20160204219	Pub Dt:	07/14/2016
Title:	SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS

Patent #:	9437269	Issue Dt:	09/06/2016	Application #:	15076992	Filing Dt:	03/22/2016
Publication #:	US20160203851	Pub Dt:	07/14/2016
Title:	ANTIFERROMAGNETIC STORAGE DEVICE

Patent #:	9691626	Issue Dt:	06/27/2017	Application #:	15077384	Filing Dt:	03/22/2016
Title:	METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES IN AN INTEGRATED CIRCUIT WHEREIN THE PATTERN INCLUDES GAMMA AND BETA BLOCK MASK PORTIONS

Patent #:	9818623	Issue Dt:	11/14/2017	Application #:	15077480	Filing Dt:	03/22/2016
Publication #:	US20170278720	Pub Dt:	09/28/2017
Title:	METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND ASSOCIATED CONTINUITY BLOCKS IN AN INTEGRATED CIRCUIT

Patent #:	9679809	Issue Dt:	06/13/2017	Application #:	15077564	Filing Dt:	03/22/2016
Title:	METHOD OF FORMING SELF ALIGNED CONTINUITY BLOCKS FOR MANDREL AND NON-MANDREL INTERCONNECT LINES

Patent #:	9747401	Issue Dt:	08/29/2017	Application #:	15078032	Filing Dt:	03/23/2016
Publication #:	US20160314234	Pub Dt:	10/27/2016
Title:	METHODS FOR MODIFYING AN INTEGRATED CIRCUIT LAYOUT DESIGN

Patent #:	9966431	Issue Dt:	05/08/2018	Application #:	15078112	Filing Dt:	03/23/2016
Publication #:	US20170278927	Pub Dt:	09/28/2017
Title:	Nanowire-Based Vertical Memory Cell Array having a Back Plate and Nanowire Seeds Contacting a Bit Line

Patent #:	10056486	Issue Dt:	08/21/2018	Application #:	15079142	Filing Dt:	03/24/2016
Publication #:	US20170278965	Pub Dt:	09/28/2017
Title:	METHODS FOR FIN THINNING PROVIDING IMPROVED SCE AND S/D EPI GROWTH

Patent #:	9633925	Issue Dt:	04/25/2017	Application #:	15081403	Filing Dt:	03/25/2016
Title:	VISUALIZATION OF ALIGNMENT MARKS ON A CHIP COVERED BY A PRE-APPLIED UNDERFILL

Patent #:	10367083	Issue Dt:	07/30/2019	Application #:	15081443	Filing Dt:	03/25/2016
Publication #:	US20170278955	Pub Dt:	09/28/2017
Title:	COMPACT DEVICE STRUCTURES FOR A BIPOLAR JUNCTION TRANSISTOR

Patent #:	10388790	Issue Dt:	08/20/2019	Application #:	15082103	Filing Dt:	03/28/2016
Publication #:	US20160211375	Pub Dt:	07/21/2016
Title:	FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING

Patent #:	9837404	Issue Dt:	12/05/2017	Application #:	15082242	Filing Dt:	03/28/2016
Publication #:	US20170278844	Pub Dt:	09/28/2017
Title:	METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES

Patent #:	9865486	Issue Dt:	01/09/2018	Application #:	15083692	Filing Dt:	03/29/2016
Publication #:	US20170287756	Pub Dt:	10/05/2017
Title:	TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LINEAR VOLTAGE SLOPE

Patent #:	10732202	Issue Dt:	08/04/2020	Application #:	15083787	Filing Dt:	03/29/2016
Publication #:	US20170285068	Pub Dt:	10/05/2017
Title:	REPAIRABLE RIGID TEST PROBE CARD ASSEMBLY

Patent #:	9953900	Issue Dt:	04/24/2018	Application #:	15083914	Filing Dt:	03/29/2016
Publication #:	US20170287812	Pub Dt:	10/05/2017
Title:	TRANSISTOR STRUCTURES GATED USING A CONDUCTOR-FILLED VIA OR TRENCH

Patent #:	9640514	Issue Dt:	05/02/2017	Application #:	15084004	Filing Dt:	03/29/2016
Title:	WAFER BONDING USING BORON AND NITROGEN BASED BONDING STACK

Patent #:	9881122	Issue Dt:	01/30/2018	Application #:	15084576	Filing Dt:	03/30/2016
Publication #:	US20170286586	Pub Dt:	10/05/2017
Title:	OVERLAY SAMPLING REDUCTION

Patent #:	9853055	Issue Dt:	12/26/2017	Application #:	15084807	Filing Dt:	03/30/2016
Publication #:	US20170287942	Pub Dt:	10/05/2017
Title:	METHOD TO IMPROVE CRYSTALLINE REGROWTH

Patent #:	NONE	Issue Dt:		Application #:	15084893	Filing Dt:	03/30/2016
Publication #:	US20160211161	Pub Dt:	07/21/2016
Title:	CONSTRAINED DIE ADHESION CURE PROCESS

Patent #:	9991167	Issue Dt:	06/05/2018	Application #:	15085077	Filing Dt:	03/30/2016
Publication #:	US20170287829	Pub Dt:	10/05/2017
Title:	METHOD AND IC STRUCTURE FOR INCREASING PITCH BETWEEN GATES

Patent #:	9425292	Issue Dt:	08/23/2016	Application #:	15085112	Filing Dt:	03/30/2016
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9472670	Issue Dt:	10/18/2016	Application #:	15085376	Filing Dt:	03/30/2016
Title:	FIELD EFFECT TRANSISTOR DEVICE SPACERS

Patent #:	9711618	Issue Dt:	07/18/2017	Application #:	15087074	Filing Dt:	03/31/2016
Title:	FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH

Patent #:	9633857	Issue Dt:	04/25/2017	Application #:	15087392	Filing Dt:	03/31/2016
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER AND METHOD FOR THE FORMATION THEREOF

Patent #:	9755016	Issue Dt:	09/05/2017	Application #:	15088592	Filing Dt:	04/01/2016
Publication #:	US20160322458	Pub Dt:	11/03/2016
Title:	NOVEL INTEGRATION PROCESS TO FORM MICROELECTRONIC OR MICROMECHANICAL STRUCTURES

Patent #:	9935106	Issue Dt:	04/03/2018	Application #:	15088874	Filing Dt:	04/01/2016
Publication #:	US20170287911	Pub Dt:	10/05/2017
Title:	MULTI-FINGER DEVICES IN MUTLIPLE-GATE-CONTACTED-PITCH, INTEGRATED STRUCTURES

Patent #:	9660105	Issue Dt:	05/23/2017	Application #:	15089647	Filing Dt:	04/04/2016
Publication #:	US20160218222	Pub Dt:	07/28/2016
Title:	FINFET CROSSPOINT FLASH MEMORY

Patent #:	9824920	Issue Dt:	11/21/2017	Application #:	15089834	Filing Dt:	04/04/2016
Publication #:	US20170287780	Pub Dt:	10/05/2017
Title:	METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES BY WORK FUNCTION MATERIAL LAYER RECESSING AND THE RESULTING DEVICES

Patent #:	9786657	Issue Dt:	10/10/2017	Application #:	15089914	Filing Dt:	04/04/2016
Publication #:	US20170287901	Pub Dt:	10/05/2017
Title:	SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR INCLUDING A GATE ELECTRODE REGION PROVIDED IN A SUBSTRATE AND METHOD FOR THE FORMATION THEREOF

Patent #:	9876111	Issue Dt:	01/23/2018	Application #:	15091020	Filing Dt:	04/05/2016
Publication #:	US20170170317	Pub Dt:	06/15/2017
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE USING DIFFERING SPACER WIDTHS AND THE RESULTING SEMICONDUCTOR DEVICE STRUCTURE

Patent #:	9831123	Issue Dt:	11/28/2017	Application #:	15091138	Filing Dt:	04/05/2016
Publication #:	US20170287777	Pub Dt:	10/05/2017
Title:	METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES

Patent #:	9613855	Issue Dt:	04/04/2017	Application #:	15091196	Filing Dt:	04/05/2016
Title:	METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES IN CMOS APPLICATIONS

Patent #:	9991366	Issue Dt:	06/05/2018	Application #:	15092039	Filing Dt:	04/06/2016
Publication #:	US20160218198	Pub Dt:	07/28/2016
Title:	ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET

Patent #:	10347748	Issue Dt:	07/09/2019	Application #:	15092168	Filing Dt:	04/06/2016
Publication #:	US20170294522	Pub Dt:	10/12/2017
Title:	METHODS OF FORMING SOURCE/DRAIN REGIONS ON FINFET DEVICES

Patent #:	9553032	Issue Dt:	01/24/2017	Application #:	15092233	Filing Dt:	04/06/2016
Publication #:	US20160218043	Pub Dt:	07/28/2016
Title:	FIN FIELD EFFECT TRANSISTOR INCLUDING ASYMMETRIC RAISED ACTIVE REGIONS

Patent #:	9721834	Issue Dt:	08/01/2017	Application #:	15092272	Filing Dt:	04/06/2016
Publication #:	US20160380078	Pub Dt:	12/29/2016
Title:	HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

Patent #:	9806161	Issue Dt:	10/31/2017	Application #:	15092910	Filing Dt:	04/07/2016
Publication #:	US20170294519	Pub Dt:	10/12/2017
Title:	INTEGRATED CIRCUIT STRUCTURE HAVING THIN GATE DIELECTRIC DEVICE AND THICK GATE DIELECTRIC DEVICE

Patent #:	9852900	Issue Dt:	12/26/2017	Application #:	15093212	Filing Dt:	04/07/2016
Publication #:	US20170294304	Pub Dt:	10/12/2017
Title:	OXIDIZING FILLER MATERIAL LINES TO INCREASE WIDTH OF HARD MASK LINES

Patent #:	9799514	Issue Dt:	10/24/2017	Application #:	15093292	Filing Dt:	04/07/2016
Publication #:	US20170294308	Pub Dt:	10/12/2017
Title:	PROTECTING, OXIDIZING, AND ETCHING OF MATERIAL LINES FOR USE IN INCREASING OR DECREASING CRITICAL DIMENSIONS OF HARD MASK LINES

100

Patent #:	10068766	Issue Dt:	09/04/2018	Application #:	15093310	Filing Dt:	04/07/2016
Publication #:	US20170294309	Pub Dt:	10/12/2017
Title:	OXIDIZING AND ETCHING OF MATERIAL LINES FOR USE IN INCREASING OR DECREASING CRITICAL DIMENSIONS OF HARD MASK LINES

Assignor

WILMINGTON TRUST, NATIONAL ASSOCIATION

Exec Dt:

11/17/2020

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309, UGLAND HOUSE

MAPLES CORPORATE SERVICES LIMITED

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BENJAMIN PETERSEN
	1460 EL CAMINO REAL, 2ND FLOOR
	SHEARMAN & STERLING LLP
	MENLO PARK, CA 94025

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