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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 137 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
9685522
Issue Dt:
06/20/2017
Application #:
15093952
Filing Dt:
04/08/2016
Title:
FORMING UNIFORM WF METAL LAYERS IN GATE AREAS OF NANO-SHEET STRUCTURES
2
Patent #:
9659835
Issue Dt:
05/23/2017
Application #:
15094026
Filing Dt:
04/08/2016
Title:
TECHNIQUES FOR INTEGRATING THERMAL VIA STRUCTURES IN INTEGRATED CIRCUITS
3
Patent #:
9916415
Issue Dt:
03/13/2018
Application #:
15095239
Filing Dt:
04/11/2016
Publication #:
US20170293709
Pub Dt:
10/12/2017
Title:
INTEGRATED CIRCUIT PERFORMANCE MODELING THAT INCLUDES SUBSTRATE-GENERATED SIGNAL DISTORTIONS
4
Patent #:
9698226
Issue Dt:
07/04/2017
Application #:
15095376
Filing Dt:
04/11/2016
Title:
RECESS LINER FOR SILICON GERMANIUM FIN FORMATION
5
Patent #:
9666488
Issue Dt:
05/30/2017
Application #:
15095612
Filing Dt:
04/11/2016
Title:
PASS-THROUGH CONTACT USING SILICIDE
6
Patent #:
10311186
Issue Dt:
06/04/2019
Application #:
15096551
Filing Dt:
04/12/2016
Publication #:
US20170293704
Pub Dt:
10/12/2017
Title:
THREE-DIMENSIONAL PATTERN RISK SCORING
7
Patent #:
9966374
Issue Dt:
05/08/2018
Application #:
15096681
Filing Dt:
04/12/2016
Publication #:
US20160225766
Pub Dt:
08/04/2016
Title:
Semiconductor Device with Gate Structures having Low-K Spacers on Sidewalls and Electrical Contacts therebetween
8
Patent #:
9786557
Issue Dt:
10/10/2017
Application #:
15096818
Filing Dt:
04/12/2016
Publication #:
US20170294347
Pub Dt:
10/12/2017
Title:
TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
9
Patent #:
9530863
Issue Dt:
12/27/2016
Application #:
15097574
Filing Dt:
04/13/2016
Title:
METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH SELF-ALIGNED REPLACEMENT GATE STRUCTURES
10
Patent #:
9530866
Issue Dt:
12/27/2016
Application #:
15097621
Filing Dt:
04/13/2016
Title:
METHODS OF FORMING VERTICAL TRANSISTOR DEVICES WITH SELF-ALIGNED TOP SOURCE/DRAIN CONDUCTIVE CONTACTS
11
Patent #:
10276390
Issue Dt:
04/30/2019
Application #:
15097861
Filing Dt:
04/13/2016
Publication #:
US20170301544
Pub Dt:
10/19/2017
Title:
METHOD AND APPARATUS FOR REDUCING THRESHOLD VOLTAGE MISMATCH IN AN INTEGRATED CIRCUIT
12
Patent #:
10068920
Issue Dt:
09/04/2018
Application #:
15098722
Filing Dt:
04/14/2016
Publication #:
US20170301697
Pub Dt:
10/19/2017
Title:
SILICON GERMANIUM FINS ON INSULATOR FORMED BY LATERAL RECRYSTALLIZATION
13
Patent #:
10020202
Issue Dt:
07/10/2018
Application #:
15099641
Filing Dt:
04/15/2016
Publication #:
US20170301551
Pub Dt:
10/19/2017
Title:
FABRICATION OF MULTI THRESHOLD-VOLTAGE DEVICES
14
Patent #:
NONE
Issue Dt:
Application #:
15120692
Filing Dt:
08/22/2016
Publication #:
US20170018069
Pub Dt:
01/19/2017
Title:
HYBRID METROLOGY TECHNIQUE
15
Patent #:
10516767
Issue Dt:
12/24/2019
Application #:
15131174
Filing Dt:
04/18/2016
Publication #:
US20170302764
Pub Dt:
10/19/2017
Title:
UNIFYING REALTIME AND STATIC DATA FOR PRESENTING OVER A WEB SERVICE
16
Patent #:
9799751
Issue Dt:
10/24/2017
Application #:
15132383
Filing Dt:
04/19/2016
Publication #:
US20170301776
Pub Dt:
10/19/2017
Title:
METHODS OF FORMING A GATE STRUCTURE ON A VERTICAL TRANSISTOR DEVICE
17
Patent #:
9698018
Issue Dt:
07/04/2017
Application #:
15132589
Filing Dt:
04/19/2016
Title:
INTRODUCING SELF-ALIGNED DOPANTS IN SEMICONDUCTOR FINS
18
Patent #:
9679972
Issue Dt:
06/13/2017
Application #:
15133683
Filing Dt:
04/20/2016
Title:
THIN STRAIN RELAXED BUFFERS WITH MULTILAYER FILM STACKS
19
Patent #:
9685334
Issue Dt:
06/20/2017
Application #:
15134917
Filing Dt:
04/21/2016
Title:
METHODS OF FORMING SEMICONDUCTOR FIN WITH CARBON DOPANT FOR DIFFUSION CONTROL
20
Patent #:
10115718
Issue Dt:
10/30/2018
Application #:
15134942
Filing Dt:
04/21/2016
Publication #:
US20170309615
Pub Dt:
10/26/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION
21
Patent #:
NONE
Issue Dt:
Application #:
15135358
Filing Dt:
04/21/2016
Publication #:
US20170309623
Pub Dt:
10/26/2017
Title:
METHOD, APPARATUS, AND SYSTEM FOR INCREASING DRIVE CURRENT OF FINFET DEVICE
22
Patent #:
9536793
Issue Dt:
01/03/2017
Application #:
15135917
Filing Dt:
04/22/2016
Title:
SELF-ALIGNED GATE-FIRST VFETs USING A GATE SPACER RECESS
23
Patent #:
10262941
Issue Dt:
04/16/2019
Application #:
15136384
Filing Dt:
04/22/2016
Publication #:
US20170309560
Pub Dt:
10/26/2017
Title:
DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS
24
Patent #:
10014074
Issue Dt:
07/03/2018
Application #:
15136404
Filing Dt:
04/22/2016
Publication #:
US20170309349
Pub Dt:
10/26/2017
Title:
FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST
25
Patent #:
9741845
Issue Dt:
08/22/2017
Application #:
15137018
Filing Dt:
04/25/2016
Publication #:
US20160315188
Pub Dt:
10/27/2016
Title:
LATERAL HIGH VOLTAGE TRANSISTOR
26
Patent #:
9818689
Issue Dt:
11/14/2017
Application #:
15137362
Filing Dt:
04/25/2016
Publication #:
US20170309563
Pub Dt:
10/26/2017
Title:
METAL-INSULATOR-METAL CAPACITOR AND METHODS OF FABRICATION
27
Patent #:
9627317
Issue Dt:
04/18/2017
Application #:
15137740
Filing Dt:
04/25/2016
Publication #:
US20160240473
Pub Dt:
08/18/2016
Title:
WAFER WITH IMPROVED PLATING CURRENT DISTRIBUTION
28
Patent #:
9613817
Issue Dt:
04/04/2017
Application #:
15138311
Filing Dt:
04/26/2016
Title:
METHOD OF ENHANCING SURFACE DOPING CONCENTRATION OF SOURCE/DRAIN REGIONS
29
Patent #:
9741713
Issue Dt:
08/22/2017
Application #:
15138954
Filing Dt:
04/26/2016
Title:
PARASITIC LATERAL BIPOLAR TRANSISTOR WITH IMPROVED IDEALITY AND LEAKAGE CURRENTS
30
Patent #:
9793262
Issue Dt:
10/17/2017
Application #:
15139644
Filing Dt:
04/27/2016
Publication #:
US20170317071
Pub Dt:
11/02/2017
Title:
FIN DIODE WITH INCREASED JUNCTION AREA
31
Patent #:
9946152
Issue Dt:
04/17/2018
Application #:
15139994
Filing Dt:
04/27/2016
Publication #:
US20170315438
Pub Dt:
11/02/2017
Title:
EXTREME ULTRAVIOLET LITHOGRAPHY PHOTOMASKS
32
Patent #:
9870163
Issue Dt:
01/16/2018
Application #:
15140016
Filing Dt:
04/27/2016
Publication #:
US20170315738
Pub Dt:
11/02/2017
Title:
DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
33
Patent #:
9818652
Issue Dt:
11/14/2017
Application #:
15140025
Filing Dt:
04/27/2016
Publication #:
US20170316986
Pub Dt:
11/02/2017
Title:
COMMONLY-BODIED FIELD-EFFECT TRANSISTORS
34
Patent #:
9633946
Issue Dt:
04/25/2017
Application #:
15140121
Filing Dt:
04/27/2016
Title:
SEAMLESS METALLIZATION CONTACTS
35
Patent #:
10108771
Issue Dt:
10/23/2018
Application #:
15140183
Filing Dt:
04/27/2016
Publication #:
US20170316140
Pub Dt:
11/02/2017
Title:
METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS WITH TRIPLE PATTERNED METAL LAYER STRUCTURES
36
Patent #:
9704852
Issue Dt:
07/11/2017
Application #:
15140516
Filing Dt:
04/28/2016
Publication #:
US20160379972
Pub Dt:
12/29/2016
Title:
ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERTICAL GATE FIN-TYPE FIELD EFFECT DIODE
37
Patent #:
9530780
Issue Dt:
12/27/2016
Application #:
15140548
Filing Dt:
04/28/2016
Publication #:
US20160322367
Pub Dt:
11/03/2016
Title:
MEMORY BIT CELL FOR REDUCED LAYOUT AREA
38
Patent #:
NONE
Issue Dt:
Application #:
15140618
Filing Dt:
04/28/2016
Publication #:
US20160322348
Pub Dt:
11/03/2016
Title:
GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING
39
Patent #:
9570394
Issue Dt:
02/14/2017
Application #:
15140808
Filing Dt:
04/28/2016
Title:
FORMATION OF IC STRUCTURE WITH PAIR OF UNITARY METAL FINS
40
Patent #:
9691775
Issue Dt:
06/27/2017
Application #:
15141087
Filing Dt:
04/28/2016
Title:
COMBINED SADP FINS FOR SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
41
Patent #:
9508604
Issue Dt:
11/29/2016
Application #:
15142052
Filing Dt:
04/29/2016
Title:
METHODS OF FORMING PUNCH THROUGH STOP REGIONS ON FINFET DEVICES ON CMOS-BASED IC PRODUCTS USING DOPED SPACERS
42
Patent #:
9941348
Issue Dt:
04/10/2018
Application #:
15142332
Filing Dt:
04/29/2016
Publication #:
US20170317161
Pub Dt:
11/02/2017
Title:
METHOD OF FORMING A CAPACITOR STRUCTURE AND CAPACITOR STRUCTURE
43
Patent #:
9996648
Issue Dt:
06/12/2018
Application #:
15142511
Filing Dt:
04/29/2016
Publication #:
US20170316136
Pub Dt:
11/02/2017
Title:
NETLIST EDITING OF GRAPHICAL DATA
44
Patent #:
9761525
Issue Dt:
09/12/2017
Application #:
15142525
Filing Dt:
04/29/2016
Title:
MULTIPLE BACK GATE TRANSISTOR
45
Patent #:
9548306
Issue Dt:
01/17/2017
Application #:
15144924
Filing Dt:
05/03/2016
Publication #:
US20160247805
Pub Dt:
08/25/2016
Title:
METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES
46
Patent #:
10049926
Issue Dt:
08/14/2018
Application #:
15146510
Filing Dt:
05/04/2016
Publication #:
US20160247716
Pub Dt:
08/25/2016
Title:
METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT
47
Patent #:
9728509
Issue Dt:
08/08/2017
Application #:
15147525
Filing Dt:
05/05/2016
Title:
LASER SCRIBE STRUCTURES FOR A WAFER
48
Patent #:
10043962
Issue Dt:
08/07/2018
Application #:
15147595
Filing Dt:
05/05/2016
Publication #:
US20170324015
Pub Dt:
11/09/2017
Title:
THERMOELECTRIC COOLING USING THROUGH-SILICON VIAS
49
Patent #:
9466570
Issue Dt:
10/11/2016
Application #:
15149286
Filing Dt:
05/09/2016
Title:
MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT
50
Patent #:
9755015
Issue Dt:
09/05/2017
Application #:
15150977
Filing Dt:
05/10/2016
Title:
AIR GAPS FORMED BY POROUS SILICON REMOVAL
51
Patent #:
9806170
Issue Dt:
10/31/2017
Application #:
15151550
Filing Dt:
05/11/2016
Publication #:
US20170330953
Pub Dt:
11/16/2017
Title:
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPACER WIDTHS & DUAL RAISED SOURCE DRAIN EXPITAXIAL SILICON AND TRIPLE-NITRIDE SPACER INTEGRATION ENABLING HIGH-VOLTAGE EG DEVICE ON FDSOI
52
Patent #:
9799660
Issue Dt:
10/24/2017
Application #:
15151622
Filing Dt:
05/11/2016
Publication #:
US20170330883
Pub Dt:
11/16/2017
Title:
STABLE AND RELIABLE FINFET SRAM WITH IMPROVED BETA RATIO
53
Patent #:
9583397
Issue Dt:
02/28/2017
Application #:
15151720
Filing Dt:
05/11/2016
Title:
SOURCE/DRAIN TERMINAL CONTACT AND METHOD OF FORMING SAME
54
Patent #:
9472509
Issue Dt:
10/18/2016
Application #:
15152600
Filing Dt:
05/12/2016
Publication #:
US20160254234
Pub Dt:
09/01/2016
Title:
DUMMY METAL STRUCTURE AND METHOD OF FORMING DUMMY METAL STRUCTURE
55
Patent #:
10211146
Issue Dt:
02/19/2019
Application #:
15152794
Filing Dt:
05/12/2016
Publication #:
US20170330832
Pub Dt:
11/16/2017
Title:
AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD
56
Patent #:
10157777
Issue Dt:
12/18/2018
Application #:
15152797
Filing Dt:
05/12/2016
Publication #:
US20170330790
Pub Dt:
11/16/2017
Title:
AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD
57
Patent #:
9614047
Issue Dt:
04/04/2017
Application #:
15153249
Filing Dt:
05/12/2016
Publication #:
US20160260812
Pub Dt:
09/08/2016
Title:
GATE CONTACT WITH VERTICAL ISOLATION FROM SOURCE-DRAIN
58
Patent #:
9812573
Issue Dt:
11/07/2017
Application #:
15153831
Filing Dt:
05/13/2016
Publication #:
US20170330970
Pub Dt:
11/16/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING STRESS CREATING REGIONS AND METHOD FOR THE FORMATION THEREOF
59
Patent #:
10115621
Issue Dt:
10/30/2018
Application #:
15153936
Filing Dt:
05/13/2016
Publication #:
US20170330782
Pub Dt:
11/16/2017
Title:
METHOD FOR IN-DIE OVERLAY CONTROL USING FEOL DUMMY FILL LAYER
60
Patent #:
10062689
Issue Dt:
08/28/2018
Application #:
15154087
Filing Dt:
05/13/2016
Publication #:
US20170330878
Pub Dt:
11/16/2017
Title:
NOVEL METHOD TO FABRICATE VERTICAL FIN FIELD-EFFECT-TRANSISTORS
61
Patent #:
9812400
Issue Dt:
11/07/2017
Application #:
15154367
Filing Dt:
05/13/2016
Publication #:
US20170330834
Pub Dt:
11/16/2017
Title:
CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME
62
Patent #:
9837268
Issue Dt:
12/05/2017
Application #:
15154444
Filing Dt:
05/13/2016
Publication #:
US20160260605
Pub Dt:
09/08/2016
Title:
RAISED FIN STRUCTURES AND METHODS OF FABRICATION
63
Patent #:
9875334
Issue Dt:
01/23/2018
Application #:
15155425
Filing Dt:
05/16/2016
Publication #:
US20170329886
Pub Dt:
11/16/2017
Title:
GENERATING MANUFACTURABLE SUB-RESOLUTION ASSIST FEATURE SHAPES FROM A USEFULNESS MAP
64
Patent #:
9922986
Issue Dt:
03/20/2018
Application #:
15155483
Filing Dt:
05/16/2016
Publication #:
US20170330889
Pub Dt:
11/16/2017
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL AND METHOD FOR THE FORMATION THEREOF
65
Patent #:
9842801
Issue Dt:
12/12/2017
Application #:
15155569
Filing Dt:
05/16/2016
Publication #:
US20160260666
Pub Dt:
09/08/2016
Title:
SELF-ALIGNED VIA AND AIR GAP
66
Patent #:
10388729
Issue Dt:
08/20/2019
Application #:
15155761
Filing Dt:
05/16/2016
Publication #:
US20170330934
Pub Dt:
11/16/2017
Title:
DEVICES AND METHODS OF FORMING SELF-ALIGNED, UNIFORM NANO SHEET SPACERS
67
Patent #:
NONE
Issue Dt:
Application #:
15156487
Filing Dt:
05/17/2016
Publication #:
US20170335501
Pub Dt:
11/23/2017
Title:
Vertical Axis Washing Machine Appliance
68
Patent #:
9673222
Issue Dt:
06/06/2017
Application #:
15156506
Filing Dt:
05/17/2016
Publication #:
US20160260742
Pub Dt:
09/08/2016
Title:
FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES
69
Patent #:
9837276
Issue Dt:
12/05/2017
Application #:
15156651
Filing Dt:
05/17/2016
Publication #:
US20170018628
Pub Dt:
01/19/2017
Title:
GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER
70
Patent #:
9601486
Issue Dt:
03/21/2017
Application #:
15156750
Filing Dt:
05/17/2016
Publication #:
US20160260701
Pub Dt:
09/08/2016
Title:
ESD SNAPBACK BASED CLAMP FOR FINFET
71
Patent #:
9805982
Issue Dt:
10/31/2017
Application #:
15156767
Filing Dt:
05/17/2016
Publication #:
US20170338156
Pub Dt:
11/23/2017
Title:
APPARATUS AND METHOD OF ADJUSTING WORK-FUNCTION METAL THICKNESS TO PROVIDE VARIABLE THRESHOLD VOLTAGES IN FINFETS
72
Patent #:
9620425
Issue Dt:
04/11/2017
Application #:
15156822
Filing Dt:
05/17/2016
Title:
METHOD OF ADJUSTING SPACER THICKNESS TO PROVIDE VARIABLE THRESHOLD VOLTAGES IN FINFETS
73
Patent #:
NONE
Issue Dt:
Application #:
15157582
Filing Dt:
05/18/2016
Publication #:
US20170338180
Pub Dt:
11/23/2017
Title:
METHOD OF MAKING VERTICAL AND BOTTOM BIAS E-FUSES AND RELATED DEVICES
74
Patent #:
10068921
Issue Dt:
09/04/2018
Application #:
15157786
Filing Dt:
05/18/2016
Publication #:
US20160260743
Pub Dt:
09/08/2016
Title:
INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACT STRUCTURES FOR IMPROVED WINDOWS AND FABRICATION METHODS
75
Patent #:
9576956
Issue Dt:
02/21/2017
Application #:
15157861
Filing Dt:
05/18/2016
Publication #:
US20170012042
Pub Dt:
01/12/2017
Title:
METHOD AND STRUCTURE OF FORMING CONTROLLABLE UNMERGED EPITAXIAL MATERIAL
76
Patent #:
9842913
Issue Dt:
12/12/2017
Application #:
15157868
Filing Dt:
05/18/2016
Publication #:
US20170338329
Pub Dt:
11/23/2017
Title:
INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER
77
Patent #:
9799559
Issue Dt:
10/24/2017
Application #:
15158827
Filing Dt:
05/19/2016
Title:
METHODS EMPLOYING SACRIFICIAL BARRIER LAYER FOR PROTECTION OF VIAS DURING TRENCH FORMATION
78
Patent #:
9691658
Issue Dt:
06/27/2017
Application #:
15159186
Filing Dt:
05/19/2016
Title:
CONTACT FILL IN AN INTEGRATED CIRCUIT
79
Patent #:
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Pub Dt:
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Title:
SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
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Issue Dt:
09/05/2017
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Filing Dt:
05/20/2016
Title:
CONTROLLING WITHIN-DIE UNIFORMITY USING DOPED POLISHING MATERIAL
81
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12/04/2018
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Pub Dt:
11/23/2017
Title:
FINFET CIRCUIT STRUCTURES WITH VERTICALLY SPACED TRANSISTORS AND FABRICATION METHODS
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Pub Dt:
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Title:
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Title:
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Pub Dt:
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Title:
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Title:
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Pub Dt:
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Title:
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Title:
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88
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Title:
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89
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Title:
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90
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11/30/2017
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02/28/2017
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Title:
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93
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Title:
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94
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06/05/2018
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Title:
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01/29/2019
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METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT
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100
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Publication #:
US20170040325
Pub Dt:
02/09/2017
Title:
FIELD EFFECT TRANSISTOR DEVICE SPACERS
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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