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Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 14520
Page 141 of 146
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
1
Patent #:
9793157
Issue Dt:
10/17/2017
Application #:
15342440
Filing Dt:
11/03/2016
Publication #:
US20170125284
Pub Dt:
05/04/2017
Title:
ETCH STOP FOR AIRGAP PROTECTION
2
Patent #:
9876010
Issue Dt:
01/23/2018
Application #:
15342464
Filing Dt:
11/03/2016
Title:
RESISTOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE
3
Patent #:
9773781
Issue Dt:
09/26/2017
Application #:
15342498
Filing Dt:
11/03/2016
Title:
RESISTOR AND CAPACITOR DISPOSED DIRECTLY UPON A SAC CAP OF A GATE STRUCTURE OF A SEMICONDUCTOR STRUCTURE
4
Patent #:
9842741
Issue Dt:
12/12/2017
Application #:
15342794
Filing Dt:
11/03/2016
Publication #:
US20170076954
Pub Dt:
03/16/2017
Title:
REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS
5
Patent #:
9929057
Issue Dt:
03/27/2018
Application #:
15342801
Filing Dt:
11/03/2016
Publication #:
US20170076987
Pub Dt:
03/16/2017
Title:
HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
6
Patent #:
10134903
Issue Dt:
11/20/2018
Application #:
15343021
Filing Dt:
11/03/2016
Publication #:
US20170077306
Pub Dt:
03/16/2017
Title:
VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE
7
Patent #:
10164104
Issue Dt:
12/25/2018
Application #:
15343590
Filing Dt:
11/04/2016
Publication #:
US20180130899
Pub Dt:
05/10/2018
Title:
METHOD TO FORM AIR-GAP SPACERS AND AIR-GAP SPACER-CONTAINING STRUCTURES
8
Patent #:
10388754
Issue Dt:
08/20/2019
Application #:
15343776
Filing Dt:
11/04/2016
Publication #:
US20170117276
Pub Dt:
04/27/2017
Title:
UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING
9
Patent #:
10115807
Issue Dt:
10/30/2018
Application #:
15343821
Filing Dt:
11/04/2016
Publication #:
US20170141214
Pub Dt:
05/18/2017
Title:
METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES
10
Patent #:
9847347
Issue Dt:
12/19/2017
Application #:
15344856
Filing Dt:
11/07/2016
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AT A SEMICONDUCTOR-ON-INSULATOR REGION AND A SECOND TRANSISTOR AT A BULK REGION AND METHOD FOR THE FORMATION THEREOF
11
Patent #:
9978836
Issue Dt:
05/22/2018
Application #:
15344862
Filing Dt:
11/07/2016
Publication #:
US20180130878
Pub Dt:
05/10/2018
Title:
NANOSTRUCTURE FIELD-EFFECT TRANSISTORS WITH ENHANCED MOBILITY SOURCE/DRAIN REGIONS
12
Patent #:
10002932
Issue Dt:
06/19/2018
Application #:
15345137
Filing Dt:
11/07/2016
Publication #:
US20180130889
Pub Dt:
05/10/2018
Title:
SELF-ALIGNED CONTACT PROTECTION USING REINFORCED GATE CAP AND SPACER PORTIONS
13
Patent #:
10217507
Issue Dt:
02/26/2019
Application #:
15345544
Filing Dt:
11/08/2016
Publication #:
US20180130521
Pub Dt:
05/10/2018
Title:
BENDING CIRCUIT FOR STATIC RANDOM ACCESS MEMORY (SRAM) SELF-TIMER
14
Patent #:
10256204
Issue Dt:
04/09/2019
Application #:
15345608
Filing Dt:
11/08/2016
Publication #:
US20180130733
Pub Dt:
05/10/2018
Title:
SEPARATION OF INTEGRATED CIRCUIT STRUCTURE FROM ADJACENT CHIP
15
Patent #:
9984932
Issue Dt:
05/29/2018
Application #:
15345612
Filing Dt:
11/08/2016
Publication #:
US20180130711
Pub Dt:
05/10/2018
Title:
SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK
16
Patent #:
9966456
Issue Dt:
05/08/2018
Application #:
15345644
Filing Dt:
11/08/2016
Publication #:
US20180130895
Pub Dt:
05/10/2018
Title:
METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE
17
Patent #:
10262892
Issue Dt:
04/16/2019
Application #:
15345882
Filing Dt:
11/08/2016
Publication #:
US20180130699
Pub Dt:
05/10/2018
Title:
SKIP VIA STRUCTURES
18
Patent #:
NONE
Issue Dt:
Application #:
15346504
Filing Dt:
11/08/2016
Publication #:
US20170300608
Pub Dt:
10/19/2017
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR SADP-FRIENDLY INTERCONNECT STRUCTURE TRACK GENERATION
19
Patent #:
10043708
Issue Dt:
08/07/2018
Application #:
15347119
Filing Dt:
11/09/2016
Publication #:
US20180130703
Pub Dt:
05/10/2018
Title:
STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS
20
Patent #:
9875936
Issue Dt:
01/23/2018
Application #:
15348109
Filing Dt:
11/10/2016
Title:
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
21
Patent #:
NONE
Issue Dt:
Application #:
15348356
Filing Dt:
11/10/2016
Publication #:
US20180130891
Pub Dt:
05/10/2018
Title:
GATE STRUCTURES
22
Patent #:
9842762
Issue Dt:
12/12/2017
Application #:
15349306
Filing Dt:
11/11/2016
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER HAVING AN SOI CONFIGURATION
23
Patent #:
9818876
Issue Dt:
11/14/2017
Application #:
15349358
Filing Dt:
11/11/2016
Title:
METHOD FOR FABRICATING A FINFET METALLIZATION ARCHITECTURE USING A SELF-ALIGNED CONTACT ETCH
24
Patent #:
9847416
Issue Dt:
12/19/2017
Application #:
15351597
Filing Dt:
11/15/2016
Title:
PERFORMANCE-ENHANCED VERTICAL DEVICE AND METHOD OF FORMING THEREOF
25
Patent #:
NONE
Issue Dt:
Application #:
15351678
Filing Dt:
11/15/2016
Publication #:
US20180138209
Pub Dt:
05/17/2018
Title:
SEMICONDUCTOR SUBSTRATE WITH METALLIC DOPED BURIED OXIDE
26
Patent #:
9972494
Issue Dt:
05/15/2018
Application #:
15351747
Filing Dt:
11/15/2016
Publication #:
US20180138046
Pub Dt:
05/17/2018
Title:
METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE
27
Patent #:
10446653
Issue Dt:
10/15/2019
Application #:
15351893
Filing Dt:
11/15/2016
Publication #:
US20180138279
Pub Dt:
05/17/2018
Title:
TRANSISTOR-BASED SEMICONDUCTOR DEVICE WITH AIR-GAP SPACERS AND GATE CONTACT OVER ACTIVE AREA
28
Patent #:
9748251
Issue Dt:
08/29/2017
Application #:
15352102
Filing Dt:
11/15/2016
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING
29
Patent #:
9865473
Issue Dt:
01/09/2018
Application #:
15352139
Filing Dt:
11/15/2016
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES USING SEMI-BIDIRECTIONAL PATTERNING AND ISLANDS
30
Patent #:
9893086
Issue Dt:
02/13/2018
Application #:
15352654
Filing Dt:
11/16/2016
Title:
CONTACT PUNCH THROUGH MITIGATION IN SOI SUBSTRATE
31
Patent #:
NONE
Issue Dt:
Application #:
15352963
Filing Dt:
11/16/2016
Publication #:
US20180138177
Pub Dt:
05/17/2018
Title:
FORMATION OF BAND-EDGE CONTACTS
32
Patent #:
9917162
Issue Dt:
03/13/2018
Application #:
15353352
Filing Dt:
11/16/2016
Publication #:
US20170288030
Pub Dt:
10/05/2017
Title:
FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
33
Patent #:
NONE
Issue Dt:
Application #:
15353771
Filing Dt:
11/17/2016
Publication #:
US20180138285
Pub Dt:
05/17/2018
Title:
METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE WITH SILICIDE REIGON
34
Patent #:
NONE
Issue Dt:
Application #:
15354047
Filing Dt:
11/17/2016
Publication #:
US20180138307
Pub Dt:
05/17/2018
Title:
TUNNEL FINFET WITH SELF-ALIGNED GATE
35
Patent #:
10115738
Issue Dt:
10/30/2018
Application #:
15354205
Filing Dt:
11/17/2016
Publication #:
US20180138203
Pub Dt:
05/17/2018
Title:
SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE
36
Patent #:
9941162
Issue Dt:
04/10/2018
Application #:
15354212
Filing Dt:
11/17/2016
Title:
SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
37
Patent #:
10079248
Issue Dt:
09/18/2018
Application #:
15355231
Filing Dt:
11/18/2016
Publication #:
US20180145088
Pub Dt:
05/24/2018
Title:
FIELD-EFFECT TRANSISTORS WITH A BURIED BODY CONTACT
38
Patent #:
10191112
Issue Dt:
01/29/2019
Application #:
15355256
Filing Dt:
11/18/2016
Publication #:
US20180143248
Pub Dt:
05/24/2018
Title:
EARLY DEVELOPMENT OF A DATABASE OF FAIL SIGNATURES FOR SYSTEMATIC DEFECTS IN INTEGRATED CIRCUIT (IC) CHIPS
39
Patent #:
10553353
Issue Dt:
02/04/2020
Application #:
15355584
Filing Dt:
11/18/2016
Publication #:
US20180144857
Pub Dt:
05/24/2018
Title:
Parallel Stacked Inductor for High-Q and High Current Handling and Method of Making the Same
40
Patent #:
10090202
Issue Dt:
10/02/2018
Application #:
15357287
Filing Dt:
11/21/2016
Publication #:
US20170125299
Pub Dt:
05/04/2017
Title:
SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
41
Patent #:
10056292
Issue Dt:
08/21/2018
Application #:
15359037
Filing Dt:
11/22/2016
Publication #:
US20180144979
Pub Dt:
05/24/2018
Title:
SELF-ALIGNED LITHOGRAPHIC PATTERNING
42
Patent #:
10505016
Issue Dt:
12/10/2019
Application #:
15359953
Filing Dt:
11/23/2016
Publication #:
US20170178967
Pub Dt:
06/22/2017
Title:
SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
43
Patent #:
10056291
Issue Dt:
08/21/2018
Application #:
15360255
Filing Dt:
11/23/2016
Publication #:
US20180144976
Pub Dt:
05/24/2018
Title:
POST SPACER SELF-ALIGNED CUTS
44
Patent #:
10153361
Issue Dt:
12/11/2018
Application #:
15360295
Filing Dt:
11/23/2016
Publication #:
US20180145160
Pub Dt:
05/24/2018
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER
45
Patent #:
9825032
Issue Dt:
11/21/2017
Application #:
15360537
Filing Dt:
11/23/2016
Title:
METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
46
Patent #:
10008582
Issue Dt:
06/26/2018
Application #:
15361790
Filing Dt:
11/28/2016
Publication #:
US20180151689
Pub Dt:
05/31/2018
Title:
SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
47
Patent #:
10121706
Issue Dt:
11/06/2018
Application #:
15361809
Filing Dt:
11/28/2016
Publication #:
US20180151449
Pub Dt:
05/31/2018
Title:
SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSIONAL BONDING MATERIALS
48
Patent #:
9935012
Issue Dt:
04/03/2018
Application #:
15361824
Filing Dt:
11/28/2016
Title:
METHODS FOR FORMING DIFFERENT SHAPES IN DIFFERENT REGIONS OF THE SAME LAYER
49
Patent #:
9882024
Issue Dt:
01/30/2018
Application #:
15361994
Filing Dt:
11/28/2016
Publication #:
US20170077266
Pub Dt:
03/16/2017
Title:
EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
50
Patent #:
9852986
Issue Dt:
12/26/2017
Application #:
15362035
Filing Dt:
11/28/2016
Title:
METHOD OF PATTERNING PILLARS TO FORM VARIABLE CONTINUITY CUTS IN INTERCONNECTION LINES OF AN INTEGRATED CIRCUIT
51
Patent #:
9899324
Issue Dt:
02/20/2018
Application #:
15362499
Filing Dt:
11/28/2016
Title:
STRUCTURE AND METHOD OF CONDUCTIVE BUS BAR FOR RESISTIVE SEED SUBSTRATE PLATING
52
Patent #:
9721673
Issue Dt:
08/01/2017
Application #:
15363056
Filing Dt:
11/29/2016
Title:
DISTRIBUTED CURRENT SOURCE/SINK USING INACTIVE MEMORY ELEMENTS
53
Patent #:
NONE
Issue Dt:
Application #:
15363267
Filing Dt:
11/29/2016
Publication #:
US20180151461
Pub Dt:
05/31/2018
Title:
STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING
54
Patent #:
9947769
Issue Dt:
04/17/2018
Application #:
15363461
Filing Dt:
11/29/2016
Title:
MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
55
Patent #:
9922929
Issue Dt:
03/20/2018
Application #:
15363513
Filing Dt:
11/29/2016
Title:
SELF ALIGNED INTERCONNECT STRUCTURES
56
Patent #:
10002940
Issue Dt:
06/19/2018
Application #:
15363563
Filing Dt:
11/29/2016
Publication #:
US20170077259
Pub Dt:
03/16/2017
Title:
SPACER CHAMFERING GATE STACK SCHEME
57
Patent #:
9929020
Issue Dt:
03/27/2018
Application #:
15363596
Filing Dt:
11/29/2016
Publication #:
US20170092507
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
58
Patent #:
10475660
Issue Dt:
11/12/2019
Application #:
15363607
Filing Dt:
11/29/2016
Publication #:
US20170092721
Pub Dt:
03/30/2017
Title:
METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
59
Patent #:
9929059
Issue Dt:
03/27/2018
Application #:
15366223
Filing Dt:
12/01/2016
Publication #:
US20170084500
Pub Dt:
03/23/2017
Title:
DUAL LINER SILICIDE
60
Patent #:
10079242
Issue Dt:
09/18/2018
Application #:
15366425
Filing Dt:
12/01/2016
Publication #:
US20180158835
Pub Dt:
06/07/2018
Title:
LOGIC AND FLASH FIELD-EFFECT TRANSISTORS
61
Patent #:
9805988
Issue Dt:
10/31/2017
Application #:
15366514
Filing Dt:
12/01/2016
Title:
METHOD OF FORMING SEMICONDUCTOR STRUCTURE INCLUDING SUSPENDED SEMICONDUCTOR LAYER AND RESULTING STRUCTURE
62
Patent #:
10347740
Issue Dt:
07/09/2019
Application #:
15367366
Filing Dt:
12/02/2016
Publication #:
US20170084718
Pub Dt:
03/23/2017
Title:
FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM
63
Patent #:
10062445
Issue Dt:
08/28/2018
Application #:
15367815
Filing Dt:
12/02/2016
Publication #:
US20180158532
Pub Dt:
06/07/2018
Title:
PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME
64
Patent #:
10014234
Issue Dt:
07/03/2018
Application #:
15367888
Filing Dt:
12/02/2016
Publication #:
US20180158745
Pub Dt:
06/07/2018
Title:
SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES
65
Patent #:
10332960
Issue Dt:
06/25/2019
Application #:
15370004
Filing Dt:
12/06/2016
Publication #:
US20180159471
Pub Dt:
06/07/2018
Title:
DIGITALLY CONTROLLED VARACTOR STRUCTURE FOR HIGH RESOLUTION DCO
66
Patent #:
9761491
Issue Dt:
09/12/2017
Application #:
15370404
Filing Dt:
12/06/2016
Title:
SELF-ALIGNED DEEP CONTACT FOR VERTICAL FET
67
Patent #:
NONE
Issue Dt:
Application #:
15370555
Filing Dt:
12/06/2016
Publication #:
US20180158821
Pub Dt:
06/07/2018
Title:
GATE STRUCTURES WITH LOW RESISTANCE
68
Patent #:
10497610
Issue Dt:
12/03/2019
Application #:
15370585
Filing Dt:
12/06/2016
Publication #:
US20180158723
Pub Dt:
06/07/2018
Title:
DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDUCTION
69
Patent #:
10643790
Issue Dt:
05/05/2020
Application #:
15370757
Filing Dt:
12/06/2016
Publication #:
US20170084390
Pub Dt:
03/23/2017
Title:
Manufacturing Method for 3D Multipath Inductor
70
Patent #:
10243047
Issue Dt:
03/26/2019
Application #:
15372929
Filing Dt:
12/08/2016
Publication #:
US20180166536
Pub Dt:
06/14/2018
Title:
ACTIVE AND PASSIVE COMPONENTS WITH DEEP TRENCH ISOLATION STRUCTURES
71
Patent #:
9875939
Issue Dt:
01/23/2018
Application #:
15373129
Filing Dt:
12/08/2016
Title:
METHODS OF FORMING UNIFORM AND PITCH INDEPENDENT FIN RECESS
72
Patent #:
9899321
Issue Dt:
02/20/2018
Application #:
15373691
Filing Dt:
12/09/2016
Title:
METHODS OF FORMING A GATE CONTACT FOR A SEMICONDUCTOR DEVICE ABOVE THE ACTIVE REGION
73
Patent #:
9806701
Issue Dt:
10/31/2017
Application #:
15373791
Filing Dt:
12/09/2016
Title:
DIGITAL FREQUENCY MULTIPLIER TO GENERATE A LOCAL OSCILLATOR SIGNAL IN FDSOI TECHNOLOGY
74
Patent #:
10062617
Issue Dt:
08/28/2018
Application #:
15373852
Filing Dt:
12/09/2016
Publication #:
US20170256462
Pub Dt:
09/07/2017
Title:
METHOD AND STRUCTURE FOR SRB ELASTIC RELAXATION
75
Patent #:
NONE
Issue Dt:
Application #:
15373898
Filing Dt:
12/09/2016
Publication #:
US20180166402
Pub Dt:
06/14/2018
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING AN INTEGRATED EFUSE HAVING DIELECTRIC LAYERS OF DIFFERENTIAL THICKNESS
76
Patent #:
10241502
Issue Dt:
03/26/2019
Application #:
15374453
Filing Dt:
12/09/2016
Publication #:
US20170097635
Pub Dt:
04/06/2017
Title:
METHODS OF ERROR DETECTION IN FABRICATION PROCESSES
77
Patent #:
10168612
Issue Dt:
01/01/2019
Application #:
15375623
Filing Dt:
12/12/2016
Publication #:
US20180164674
Pub Dt:
06/14/2018
Title:
PHOTOMASK BLANK INCLUDING A THIN CHROMIUM HARDMASK
78
Patent #:
10068918
Issue Dt:
09/04/2018
Application #:
15375890
Filing Dt:
12/12/2016
Publication #:
US20170104005
Pub Dt:
04/13/2017
Title:
CONTACTING SOI SUBSTRATES
79
Patent #:
9847290
Issue Dt:
12/19/2017
Application #:
15375924
Filing Dt:
12/12/2016
Title:
THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
80
Patent #:
10319627
Issue Dt:
06/11/2019
Application #:
15376831
Filing Dt:
12/13/2016
Publication #:
US20180166319
Pub Dt:
06/14/2018
Title:
AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS
81
Patent #:
9859120
Issue Dt:
01/02/2018
Application #:
15377125
Filing Dt:
12/13/2016
Title:
METHOD OF MAKING SELF-ALIGNED CONTINUITY CUTS IN MANDREL AND NON-MANDREL METAL LINES
82
Patent #:
NONE
Issue Dt:
Application #:
15377473
Filing Dt:
12/13/2016
Publication #:
US20170092585
Pub Dt:
03/30/2017
Title:
SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER
83
Patent #:
NONE
Issue Dt:
Application #:
15377496
Filing Dt:
12/13/2016
Publication #:
US20180166356
Pub Dt:
06/14/2018
Title:
FAN-OUT CIRCUIT PACKAGING WITH INTEGRATED LID
84
Patent #:
9773680
Issue Dt:
09/26/2017
Application #:
15377503
Filing Dt:
12/13/2016
Title:
ADVANCED METHOD FOR SCALED SRAM WITH FLEXIBLE ACTIVE PITCH
85
Patent #:
10038413
Issue Dt:
07/31/2018
Application #:
15377580
Filing Dt:
12/13/2016
Publication #:
US20180167038
Pub Dt:
06/14/2018
Title:
FULLY DEPLETED SILICON ON INSULATOR POWER AMPLIFIER
86
Patent #:
10043753
Issue Dt:
08/07/2018
Application #:
15377592
Filing Dt:
12/13/2016
Publication #:
US20180166383
Pub Dt:
06/14/2018
Title:
AIRGAPS TO ISOLATE METALLIZATION FEATURES
87
Patent #:
10296698
Issue Dt:
05/21/2019
Application #:
15378122
Filing Dt:
12/14/2016
Publication #:
US20180165402
Pub Dt:
06/14/2018
Title:
FORMING MULTI-SIZED THROUGH-SILICON-VIA (TSV) STRUCTURES
88
Patent #:
9780197
Issue Dt:
10/03/2017
Application #:
15378596
Filing Dt:
12/14/2016
Title:
METHOD OF CONTROLLING VFET CHANNEL LENGTH
89
Patent #:
10424664
Issue Dt:
09/24/2019
Application #:
15378990
Filing Dt:
12/14/2016
Publication #:
US20180166566
Pub Dt:
06/14/2018
Title:
POLY GATE EXTENSION SOURCE TO BODY CONTACT
90
Patent #:
10043703
Issue Dt:
08/07/2018
Application #:
15379605
Filing Dt:
12/15/2016
Publication #:
US20180174894
Pub Dt:
06/21/2018
Title:
APPARATUS AND METHOD FOR FORMING INTERCONNECTION LINES HAVING VARIABLE PITCH AND VARIABLE WIDTHS
91
Patent #:
9812351
Issue Dt:
11/07/2017
Application #:
15379645
Filing Dt:
12/15/2016
Title:
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED CONTINUITY CUTS
92
Patent #:
10002786
Issue Dt:
06/19/2018
Application #:
15379707
Filing Dt:
12/15/2016
Publication #:
US20180174895
Pub Dt:
06/21/2018
Title:
INTERCONNECTION CELLS HAVING VARIABLE WIDTH METAL LINES AND FULLY-SELF ALIGNED VARIABLE LENGTH CONTINUITY CUTS
93
Patent #:
9887127
Issue Dt:
02/06/2018
Application #:
15379740
Filing Dt:
12/15/2016
Title:
INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
94
Patent #:
10128151
Issue Dt:
11/13/2018
Application #:
15381826
Filing Dt:
12/16/2016
Publication #:
US20180174965
Pub Dt:
06/21/2018
Title:
DEVICES AND METHODS OF COBALT FILL METALLIZATION
95
Patent #:
10014397
Issue Dt:
07/03/2018
Application #:
15383171
Filing Dt:
12/19/2016
Publication #:
US20180175180
Pub Dt:
06/21/2018
Title:
BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE
96
Patent #:
9916982
Issue Dt:
03/13/2018
Application #:
15383461
Filing Dt:
12/19/2016
Title:
DIELECTRIC PRESERVATION IN A REPLACEMENT GATE PROCESS
97
Patent #:
9806032
Issue Dt:
10/31/2017
Application #:
15384741
Filing Dt:
12/20/2016
Title:
INTEGRATED CIRCUIT STRUCTURE WITH REFRACTORY METAL ALIGNMENT MARKER AND METHODS OF FORMING SAME
98
Patent #:
10026883
Issue Dt:
07/17/2018
Application #:
15385068
Filing Dt:
12/20/2016
Publication #:
US20180175266
Pub Dt:
06/21/2018
Title:
WAFER BOND INTERCONNECT STRUCTURES
99
Patent #:
9953831
Issue Dt:
04/24/2018
Application #:
15385949
Filing Dt:
12/21/2016
Title:
DEVICE STRUCTURES WITH MULTIPLE NITRIDED LAYERS
100
Patent #:
10446442
Issue Dt:
10/15/2019
Application #:
15386097
Filing Dt:
12/21/2016
Publication #:
US20180174948
Pub Dt:
06/21/2018
Title:
INTEGRATED CIRCUIT CHIP WITH MOLDING COMPOUND HANDLER SUBSTRATE AND METHOD
Assignor
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
Exec Dt:
11/17/2020
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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