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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/07/2003
Application #:
09844773
Filing Dt:
04/27/2001
Title:
MOSFET WITH DIFFERENTIAL HALO IMPLANT AND ANNEALING STRATEGY
2
Patent #:
Issue Dt:
07/01/2003
Application #:
09844814
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
10/31/2002
Title:
PRINTED CIRCUIT BOARD WITH MIXED METALLURGY PADS OXIDE LAYER AND SOLDER MASK
3
Patent #:
Issue Dt:
03/18/2003
Application #:
09844848
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
12/05/2002
Title:
RESIST COMPOSITIONS WITH POLYMERS HAVING PENDANT GROUPS CONTAINING PLURAL ACID LABILE MOIETIES
4
Patent #:
Issue Dt:
03/18/2003
Application #:
09845266
Filing Dt:
04/30/2001
Title:
DEVICE AND METHOD FOR TESTING PERFORMANCE OF SILICON STRUCTURES
5
Patent #:
Issue Dt:
05/30/2006
Application #:
09845454
Filing Dt:
04/30/2001
Title:
SYSTEM AND METHOD FOR ACTIVE CONTROL OF ETCH PROCESS
6
Patent #:
Issue Dt:
06/22/2004
Application #:
09845654
Filing Dt:
04/30/2001
Title:
METHOD OF ENHANCING GATE PATTERNING PROPERTIES WITH REFLECTIVE HARD MASK
7
Patent #:
Issue Dt:
08/27/2002
Application #:
09845859
Filing Dt:
04/30/2001
Title:
METHOD FOR PRODUCING METAL-SEMICONDUCTOR COMPOUND REGIONS ON SEMICONDUCTOR DEVICES
8
Patent #:
Issue Dt:
10/01/2002
Application #:
09845980
Filing Dt:
04/30/2001
Title:
INVERSE INTEGRATED CIRCUIT FABRICATION PROCESS
9
Patent #:
Issue Dt:
01/14/2003
Application #:
09846186
Filing Dt:
05/02/2001
Title:
METHOD OF FORMING CAPPED COPPER INTERCONNECTS WITH REDUCED HILLOCK FORMATION AND IMPROVED ELECTROMIGRATION RESISTANCE
10
Patent #:
Issue Dt:
05/13/2003
Application #:
09846187
Filing Dt:
05/02/2001
Publication #:
Pub Dt:
11/07/2002
Title:
METHOD OF FORMING LOW RESISTANCE VIAS
11
Patent #:
Issue Dt:
08/26/2003
Application #:
09846502
Filing Dt:
05/01/2001
Title:
FIELD EFFECT TRANSISTOR WITH SELF ALLIGNED DOUBLE GATE AND METHOD OF FORMING SAME
12
Patent #:
Issue Dt:
08/13/2002
Application #:
09846611
Filing Dt:
05/02/2001
Title:
METHOD OF IMPROVING ELECTROMIGRATION RESISTANCE OF CAPPED CU
13
Patent #:
Issue Dt:
09/16/2003
Application #:
09846813
Filing Dt:
05/01/2001
Title:
METHOD OF FABRICATING TRANSISTOR HAVING A SINGLE CRYSTALLINE GATE CONDUCTOR
14
Patent #:
Issue Dt:
09/10/2002
Application #:
09846958
Filing Dt:
05/01/2001
Title:
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH MINIMIZED PARASITIC MILLER CAPACITANCE
15
Patent #:
Issue Dt:
09/28/2004
Application #:
09847622
Filing Dt:
05/02/2001
Publication #:
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH REDUCED GATE DELAY AND METHOD OF FABRICATING THE SAME
16
Patent #:
Issue Dt:
07/15/2003
Application #:
09847803
Filing Dt:
05/02/2001
Title:
EUV MASK OR RETICLE HAVING REDUCED REFLECTIONS
17
Patent #:
Issue Dt:
05/20/2003
Application #:
09848085
Filing Dt:
05/03/2001
Publication #:
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH AN IMPROVED GATE CONTACT
18
Patent #:
Issue Dt:
08/24/2004
Application #:
09848153
Filing Dt:
05/03/2001
Publication #:
Pub Dt:
11/07/2002
Title:
ORDERED TWO-PHASE DIELECTRIC FILM, AND SEMICONDUCTOR DEVICE CONTAINING THE SAME
19
Patent #:
Issue Dt:
06/10/2003
Application #:
09848454
Filing Dt:
05/03/2001
Publication #:
Pub Dt:
11/07/2002
Title:
CONSTANT IMPEDANCE DRIVER FOR HIGH SPEED INTERFACE
20
Patent #:
Issue Dt:
02/18/2003
Application #:
09848508
Filing Dt:
05/03/2001
Publication #:
Pub Dt:
11/07/2002
Title:
SOI TRANSISTOR WITH POLYSILICON SEED
21
Patent #:
Issue Dt:
12/24/2002
Application #:
09848979
Filing Dt:
05/04/2001
Title:
SEED LAYER WITH ANNEALED REGION FOR INTEGRATED CIRCUIT INTERCONNECTS
22
Patent #:
Issue Dt:
06/25/2002
Application #:
09849357
Filing Dt:
05/07/2001
Title:
METHOD OF DEPOSITING SION WITH REDUCED DEFECTS
23
Patent #:
Issue Dt:
01/21/2003
Application #:
09849494
Filing Dt:
05/04/2001
Title:
SELF-ALIGNED FLOATING BODY CONTROL FOR SOI DEVICE THROUGH LEAKAGE ENHANCED BURIED OXIDE
24
Patent #:
Issue Dt:
11/23/2004
Application #:
09849530
Filing Dt:
05/07/2001
Publication #:
Pub Dt:
09/27/2001
Title:
METHOD FOR IMPROVING ADHESION TO COPPER
25
Patent #:
Issue Dt:
01/28/2003
Application #:
09850392
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
26
Patent #:
Issue Dt:
10/17/2006
Application #:
09850393
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
27
Patent #:
Issue Dt:
07/15/2003
Application #:
09851199
Filing Dt:
05/08/2001
Title:
METHOD AND APPARATUS FOR PLANARIZING SURFACES OF SEMICONDUCTOR DEVICE CONDUCTIVE LAYERS
28
Patent #:
Issue Dt:
06/20/2006
Application #:
09852372
Filing Dt:
05/10/2001
Title:
SECURE EXECUTION BOX
29
Patent #:
Issue Dt:
06/25/2002
Application #:
09852535
Filing Dt:
05/10/2001
Publication #:
Pub Dt:
05/23/2002
Title:
METHOD OF FORMING LIGHTLY DOPED REGIONS IN A SEMICONDUCTOR DEVICE
30
Patent #:
Issue Dt:
03/01/2005
Application #:
09853234
Filing Dt:
05/11/2001
Title:
INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE
31
Patent #:
Issue Dt:
11/23/2004
Application #:
09853345
Filing Dt:
05/10/2001
Publication #:
Pub Dt:
11/14/2002
Title:
FULLY UNDERCUT RESIST SYSTEMS USING E-BEAM LITHOGRAPHY FOR THE FABRICATION OF HIGH RESOLUTION MR SENSORS
32
Patent #:
Issue Dt:
05/08/2007
Application #:
09853395
Filing Dt:
05/11/2001
Title:
ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM
33
Patent #:
Issue Dt:
12/14/2004
Application #:
09853437
Filing Dt:
05/11/2001
Title:
PERSONAL COMPUTER SECURITY MECHANSIM
34
Patent #:
Issue Dt:
11/23/2004
Application #:
09853447
Filing Dt:
05/11/2001
Title:
INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY
35
Patent #:
Issue Dt:
10/22/2002
Application #:
09854049
Filing Dt:
05/11/2001
Publication #:
Pub Dt:
11/14/2002
Title:
FUSE LATCH ARRAY SYSTEM FOR AN EMBEDDED DRAM HAVING A MICRO-CELL ARCHITECTURE
36
Patent #:
Issue Dt:
04/25/2006
Application #:
09854586
Filing Dt:
05/11/2001
Title:
TRANSPORT STREAM PARSER
37
Patent #:
Issue Dt:
12/31/2002
Application #:
09854987
Filing Dt:
05/14/2001
Publication #:
Pub Dt:
11/28/2002
Title:
ALTERNATING REFERENCE WORDLINE SCHEME FOR FAST DRAM
38
Patent #:
Issue Dt:
09/06/2005
Application #:
09855240
Filing Dt:
05/15/2001
Publication #:
Pub Dt:
11/21/2002
Title:
HIGH SPEED EMBEDDED DRAM WITH SRAM-LIKE INTERFACE
39
Patent #:
Issue Dt:
11/23/2004
Application #:
09855871
Filing Dt:
05/15/2001
Title:
PARALLEL EDGE FILTERS IN VIDEO CODEC
40
Patent #:
Issue Dt:
04/27/2004
Application #:
09858687
Filing Dt:
05/16/2001
Publication #:
Pub Dt:
11/21/2002
Title:
LAMINATED DIFFUSION BARRIER
41
Patent #:
Issue Dt:
01/06/2004
Application #:
09858919
Filing Dt:
05/16/2001
Publication #:
Pub Dt:
11/21/2002
Title:
VAPOR PHASE SURFACE MODIFICATION OF COMPOSITE SUBSTRATES TO FORM A MOLECULARLY THIN RELEASE LAYER
42
Patent #:
Issue Dt:
10/26/2004
Application #:
09859021
Filing Dt:
05/15/2001
Publication #:
Pub Dt:
11/21/2002
Title:
CMOS STRUCTURE WITH MAXIMIZED POLYSILICON GATE ACTIVATION AND A METHOD FOR SELECTIVELY MAXIMIZING DOPING ACTIVATION IN GATE, EXTENSION, AND SOURCE/DRAIN REGIONS
43
Patent #:
Issue Dt:
02/11/2003
Application #:
09859145
Filing Dt:
05/16/2001
Publication #:
Pub Dt:
11/21/2002
Title:
EARLY WRITE DRAM ARCHITECTURE WITH VERTICALLY FOLDED BITLINES
44
Patent #:
Issue Dt:
12/10/2002
Application #:
09859252
Filing Dt:
05/17/2001
Publication #:
Pub Dt:
11/29/2001
Title:
INTERPOSER FOR CONNECTING TWO SUBSTRATES AND RESULTING ASSEMBLY
45
Patent #:
Issue Dt:
04/20/2004
Application #:
09859290
Filing Dt:
05/16/2001
Title:
METHOD AND SYSTEM FOR SPECULATIVELY INVALIDATING LINES IN A CACHE
46
Patent #:
Issue Dt:
06/04/2002
Application #:
09860141
Filing Dt:
05/17/2001
Title:
METHOD OF SILICIDE FORMATION BY SILICON PRETREATMENT
47
Patent #:
Issue Dt:
10/15/2002
Application #:
09860226
Filing Dt:
05/18/2001
Title:
METHOD AND APPARATUS FOR DETECTING DISHING IN A POLISHED LAYER
48
Patent #:
Issue Dt:
04/27/2004
Application #:
09860264
Filing Dt:
05/18/2001
Publication #:
Pub Dt:
11/21/2002
Title:
REFLECTIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS
49
Patent #:
Issue Dt:
01/20/2004
Application #:
09860265
Filing Dt:
05/18/2001
Publication #:
Pub Dt:
11/21/2002
Title:
TRANSMISSIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS
50
Patent #:
Issue Dt:
05/13/2003
Application #:
09860736
Filing Dt:
05/18/2001
Publication #:
Pub Dt:
11/21/2002
Title:
FLASH MEMORY STRUCTURE HAVING DOUBLE CELLED ELEMENTS AND METHOD FOR FABRICATING THE SAME
51
Patent #:
Issue Dt:
06/22/2004
Application #:
09861253
Filing Dt:
05/18/2001
Publication #:
Pub Dt:
11/21/2002
Title:
CONTACT PLUG FORMATION FOR DEVICES WITH STACKED CAPACITORS
52
Patent #:
Issue Dt:
11/26/2002
Application #:
09861593
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
10/25/2001
Title:
CONTROL OF BURIED OXIDE QUALITY IN LOW DOSE SIMOX
53
Patent #:
Issue Dt:
08/05/2003
Application #:
09861594
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/21/2002
Title:
SELF-ADJUSTING THICKNESS UNIFORMITY IN SOI BY HIGH-TEMPERATURE OXIDATION OF SIMOX AND BONDED SOI
54
Patent #:
Issue Dt:
04/01/2003
Application #:
09861596
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/21/2002
Title:
THE ULTIMATE SIMOX
55
Patent #:
Issue Dt:
04/29/2003
Application #:
09861788
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/21/2002
Title:
INTEGRATED CHIP HAVING SRAM, DRAM AND FLASH MEMORY AND METHOD FOR FABRICATING THE SAME
56
Patent #:
Issue Dt:
06/29/2004
Application #:
09862372
Filing Dt:
05/22/2001
Publication #:
Pub Dt:
10/09/2003
Title:
OXYNITRIDE GATE DIELECTRIC AND METHOD OF FORMING
57
Patent #:
Issue Dt:
12/14/2004
Application #:
09862427
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/21/2002
Title:
SYSTEM AND METHOD FOR ANALYZING POWER DISTRIBUTION USING STATIC TIMING ANALYSIS
58
Patent #:
Issue Dt:
04/15/2003
Application #:
09862687
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
11/01/2001
Title:
STORE TO LOAD FORWARDING USING A DEPENDENCY LINK FILE
59
Patent #:
Issue Dt:
08/17/2004
Application #:
09862827
Filing Dt:
05/22/2001
Publication #:
Pub Dt:
05/09/2002
Title:
METHOD FOR FORMING DUAL WORKFUNCTION HIGH-PERFORMANCE SUPPORT MOSFETS IN EDRAM ARRAYS
60
Patent #:
Issue Dt:
01/13/2004
Application #:
09863596
Filing Dt:
05/23/2001
Title:
METHOD FOR DETERMINING PROCESS LAYER THICKNESS USING SCATTEROMETRY MEASUREMENTS
61
Patent #:
Issue Dt:
12/02/2003
Application #:
09863598
Filing Dt:
05/23/2001
Title:
METHOD AND APPARATUS FOR DETECTING NECKING OVER FIELD/ACTIVE TRANSITIONS
62
Patent #:
Issue Dt:
01/22/2002
Application #:
09863848
Filing Dt:
05/23/2001
Title:
Content addressable memory device
63
Patent #:
Issue Dt:
04/27/2004
Application #:
09863952
Filing Dt:
05/23/2001
Publication #:
Pub Dt:
11/28/2002
Title:
HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN
64
Patent #:
Issue Dt:
12/24/2002
Application #:
09863980
Filing Dt:
05/23/2001
Publication #:
Pub Dt:
11/28/2002
Title:
OXYNITRIDE SHALLOW TRENCH ISOLATION AND METHOD OF FORMATION
65
Patent #:
Issue Dt:
04/20/2004
Application #:
09864692
Filing Dt:
05/24/2001
Title:
METHOD AND APPARATUS FOR USING A DYNAMIC CONTROL MODEL TO COMPENSATE FOR A PROCESS INTERRUPT
66
Patent #:
Issue Dt:
11/11/2003
Application #:
09864974
Filing Dt:
05/24/2001
Publication #:
Pub Dt:
11/28/2002
Title:
STRUCTURE AND METHOD TO PRESERVE STI DURING ETCHING
67
Patent #:
Issue Dt:
07/22/2003
Application #:
09865830
Filing Dt:
05/25/2001
Publication #:
Pub Dt:
11/28/2002
Title:
DIFFERENTIAL SCSI DRIVER RISE TIME AND AMPLITUDE CONTROL CIRCUIT
68
Patent #:
Issue Dt:
10/29/2002
Application #:
09867902
Filing Dt:
05/30/2001
Title:
SELF-SUPPORTING AIR BRIDGE INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS
69
Patent #:
Issue Dt:
08/20/2002
Application #:
09870559
Filing Dt:
05/31/2001
Title:
STABILIZED DIRECT SENSING MEMORY ARCHITECTURE
70
Patent #:
Issue Dt:
08/23/2005
Application #:
09870623
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
METHOD AND APPARATUS FOR INTERFACE SIGNALING USING SINGLE-ENDED AND DIFFERENTIAL DATA SIGNALS
71
Patent #:
Issue Dt:
04/22/2003
Application #:
09870755
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
SINGLE BITLINE DIRECT SENSING ARCHITECTURE FOR HIGH SPEED MEMORY DEVICE
72
Patent #:
Issue Dt:
10/01/2002
Application #:
09871015
Filing Dt:
05/31/2001
Title:
METHOD AND APPARATUS FOR OPTICAL FILM STACK FAULT DETECTION
73
Patent #:
Issue Dt:
03/04/2003
Application #:
09871191
Filing Dt:
05/31/2001
Title:
POST-SILICIDATION IMPLANT FOR INTRODUCING RECOMBINATION CENTER IN BODY OF SOI MOSFET
74
Patent #:
Issue Dt:
04/08/2003
Application #:
09871556
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
PRINTED WIRING BOARD INTERPOSER SUB-ASSEMBLY
75
Patent #:
Issue Dt:
06/08/2004
Application #:
09871557
Filing Dt:
05/31/2001
Publication #:
Pub Dt:
12/05/2002
Title:
SELECTIVE SHIELD/MATERIAL FLOW MECHANISM
76
Patent #:
Issue Dt:
05/29/2007
Application #:
09871883
Filing Dt:
06/01/2001
Publication #:
Pub Dt:
12/05/2002
Title:
DUAL-DAMASCENE METALLIZATION INTERCONNECTION
77
Patent #:
Issue Dt:
03/04/2003
Application #:
09872328
Filing Dt:
06/01/2001
Title:
CONFORMAL ATOMIC LINER LAYER IN AN INTERGRATED CIRCUIT INTERCONNECT
78
Patent #:
Issue Dt:
11/19/2002
Application #:
09873667
Filing Dt:
06/04/2001
Title:
METHOD OF ELECTROCHEMICAL FORMATION OF HIGH TC SUPERCONDUCTING DAMASCENE INTERCONNECT FOR INTEGRATED CIRCUIT
79
Patent #:
Issue Dt:
03/04/2003
Application #:
09874196
Filing Dt:
06/05/2001
Publication #:
Pub Dt:
12/05/2002
Title:
LAND GRID ARRAY STIFFENER USE WITH FLEXIBLE CHIP CARRIERS
80
Patent #:
Issue Dt:
07/15/2003
Application #:
09875596
Filing Dt:
06/06/2001
Title:
SYSTEM FOR AND METHOD OF USING DEVELOPER AS A SOLVENT TO SPREAD PHOTORESIST FASTER AND REDUCE PHOTORESIST CONSUMPTION
81
Patent #:
Issue Dt:
04/20/2004
Application #:
09876631
Filing Dt:
06/07/2001
Publication #:
Pub Dt:
12/12/2002
Title:
LOGIC CIRCUIT FOR TRUE AND COMPLEMENT SIGNAL GENERATOR
82
Patent #:
Issue Dt:
08/30/2011
Application #:
09877120
Filing Dt:
06/11/2001
Title:
SYSTEM AND METHOD FOR IMPLEMENTING AN IRC ACROSS MULTIPLE NETWORK DEVICES
83
Patent #:
Issue Dt:
12/02/2003
Application #:
09878474
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
12/26/2002
Title:
STRUCTURE AND METHOD FOR IMPROVED ADHESION BETWEEN TWO POLYMER FILMS
84
Patent #:
Issue Dt:
01/28/2003
Application #:
09878525
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
12/26/2002
Title:
CONTENT ADDRESSABLE MEMORY HAVING CASCADED SUB-ENTRY ARCHITECTURE
85
Patent #:
Issue Dt:
12/10/2002
Application #:
09878681
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
04/18/2002
Title:
SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
86
Patent #:
Issue Dt:
02/03/2004
Application #:
09878804
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
10/18/2001
Title:
SEMICONDUCTOR CHIP HAVING BOTH COMPACT MEMORY AND HIGH PERFORMANCE LOGIC
87
Patent #:
Issue Dt:
06/03/2003
Application #:
09878930
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
02/21/2002
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR WITH SILICON-GERMANIUM BASE
88
Patent #:
Issue Dt:
05/10/2005
Application #:
09879105
Filing Dt:
06/13/2001
Publication #:
Pub Dt:
12/19/2002
Title:
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) GATE STACK WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRIC AND INTEGRATED DIFFUSION BARRIER
89
Patent #:
Issue Dt:
03/04/2003
Application #:
09879338
Filing Dt:
06/11/2001
Title:
METHOD OF CONTROLLING PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF PHOTORESIST THICKNESS, AND SYSTEM FOR ACCOMPLISHING SAME
90
Patent #:
Issue Dt:
07/06/2004
Application #:
09879530
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
12/12/2002
Title:
METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
91
Patent #:
Issue Dt:
10/21/2003
Application #:
09879579
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
12/12/2002
Title:
COMPACT BODY FOR SILICON-ON-INSULATOR TRANSISTORS REQUIRING NO ADDITIONAL LAYOUT AREA
92
Patent #:
Issue Dt:
04/05/2005
Application #:
09879653
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
12/12/2002
Title:
UNIFIED SRAM CACHE SYSTEM FOR AN EMBEDDED DRAM SYSTEM HAVING A MICRO-CELL ARCHITECTURE
93
Patent #:
Issue Dt:
04/06/2004
Application #:
09879724
Filing Dt:
06/12/2001
Publication #:
Pub Dt:
12/12/2002
Title:
LEAKY, THERMALLY CONDUCTIVE INSULATOR MATERIAL (LTCIM) IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE
94
Patent #:
Issue Dt:
03/18/2003
Application #:
09880219
Filing Dt:
06/12/2001
Title:
METHOD OF ENHANCED FILL OF VIAS AND TRENCHES
95
Patent #:
Issue Dt:
07/22/2003
Application #:
09880591
Filing Dt:
06/13/2001
Title:
SYSTEM TO DETERMINE SUITABILITY OF SION ARC SURFACE FOR DUV RESIST PATTERNING
96
Patent #:
Issue Dt:
03/25/2003
Application #:
09880598
Filing Dt:
06/13/2001
Publication #:
Pub Dt:
12/19/2002
Title:
TIMING CIRCUIT AND METHOD FOR A COMPILABLE DRAM
97
Patent #:
Issue Dt:
10/07/2003
Application #:
09880990
Filing Dt:
06/13/2001
Title:
METHOD AND APPARATUS FOR PERFORMING TRENCH DEPTH ANALYSIS
98
Patent #:
Issue Dt:
07/15/2003
Application #:
09881817
Filing Dt:
06/18/2001
Publication #:
Pub Dt:
01/02/2003
Title:
METHOD OF CONTROLLING ADDITIVES IN COPPER PLATING BATHS
99
Patent #:
Issue Dt:
12/10/2002
Application #:
09881831
Filing Dt:
06/14/2001
Title:
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25MM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
100
Patent #:
Issue Dt:
08/27/2002
Application #:
09882095
Filing Dt:
06/15/2001
Title:
SURFACE ENGINEERING TO PREVENT EPI GROWTH ON GATE POLY DURING SELECTIVE EPI PROCESSING
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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