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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
07/06/2004
Application #:
10050471
Filing Dt:
01/16/2002
Title:
SYSTEM AND METHOD FOR DEVELOPER ENDPOINT DETECTION BY REFLECTOMETRY OR SCATTEROMETRY
2
Patent #:
Issue Dt:
06/08/2004
Application #:
10050484
Filing Dt:
01/16/2002
Title:
USE OF SURFACE COUPLING AGENT TO IMPROVE ADHESION
3
Patent #:
NONE
Issue Dt:
Application #:
10050572
Filing Dt:
01/18/2002
Publication #:
Pub Dt:
08/15/2002
Title:
Electric fan
4
Patent #:
Issue Dt:
09/17/2002
Application #:
10050732
Filing Dt:
01/16/2002
Title:
USING SCATTEROMETRY TO MEASURE RESIST THICKNESS AND CONTROL IMPLANT
5
Patent #:
Issue Dt:
06/01/2004
Application #:
10051135
Filing Dt:
01/18/2002
Publication #:
Pub Dt:
06/06/2002
Title:
CHEMICAL-MECHANICAL PLANARIZATION OF BARRIERS OR LINERS FOR COPPER METALLURGY
6
Patent #:
Issue Dt:
05/06/2003
Application #:
10051549
Filing Dt:
01/18/2002
Title:
METHOD OF TOPOGRAPHY MANAGEMENT IN SEMICONDUCTOR FORMATION
7
Patent #:
Issue Dt:
11/11/2003
Application #:
10051790
Filing Dt:
01/17/2002
Title:
PREPARATION OF COMPOSITE HIGH-K / STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES
8
Patent #:
Issue Dt:
10/14/2003
Application #:
10052142
Filing Dt:
01/17/2002
Title:
X-RAY REFLECTANCE SYSTEM TO DETERMINE SUITABILITY OF SION ARC LAYER
9
Patent #:
Issue Dt:
12/30/2003
Application #:
10052146
Filing Dt:
01/17/2002
Title:
GROWING A DUAL DAMASCENE STRUCTURE USING A COPPER SEED LAYER AND A DAMASCENE RESIST STRUCTURE
10
Patent #:
Issue Dt:
09/16/2003
Application #:
10053033
Filing Dt:
11/07/2001
Publication #:
Pub Dt:
05/08/2003
Title:
PHASE LOCKED LOOP RECONFIGURATION
11
Patent #:
Issue Dt:
06/01/2004
Application #:
10054409
Filing Dt:
11/13/2001
Publication #:
Pub Dt:
05/15/2003
Title:
RESONANT OPERATION OF MEMS SWITCH
12
Patent #:
Issue Dt:
10/19/2004
Application #:
10055138
Filing Dt:
01/23/2002
Publication #:
Pub Dt:
07/24/2003
Title:
METHOD OF CREATING HIGH-QUALITY RELAXED SIGE-ON-INSULATOR FOR STRAINED SI CMOS APPLICATIONS
13
Patent #:
Issue Dt:
12/17/2002
Application #:
10055139
Filing Dt:
01/23/2002
Title:
CONTROLLING INTERNAL THERMAL OXIDATION AND ELIMINATING DEEP DIVOTS IN SIMOX BY CHLORINE-BASED ANNEALING
14
Patent #:
Issue Dt:
11/22/2005
Application #:
10055275
Filing Dt:
01/23/2002
Publication #:
Pub Dt:
07/24/2003
Title:
PSEUDO RANDOM OPTIMIZED BUILT-IN SELF-TEST
15
Patent #:
Issue Dt:
02/25/2003
Application #:
10055704
Filing Dt:
01/22/2002
Publication #:
Pub Dt:
06/06/2002
Title:
BEOL DECOUPLING CAPACITOR
16
Patent #:
Issue Dt:
01/27/2004
Application #:
10056245
Filing Dt:
01/22/2002
Publication #:
Pub Dt:
07/24/2003
Title:
UV-CURABLE COMPOSITIONS AND METHOD OF USE THEREOF IN MICROELECTRONICS
17
Patent #:
Issue Dt:
07/29/2003
Application #:
10056531
Filing Dt:
01/24/2002
Publication #:
Pub Dt:
07/18/2002
Title:
NANOPARTICLES FORMED WITH RIGID CONNECTOR COMPOUNDS
18
Patent #:
Issue Dt:
11/30/2004
Application #:
10057024
Filing Dt:
01/25/2002
Publication #:
Pub Dt:
06/13/2002
Title:
SYNTHESIS OF SOLUBLE DERIVATIVES OF SEXITHIOPHENE AND THEIR USE AS THE SEMICONDUCTING CHANNELS IN THIN-FILM FIELD-EFFECT TRANSISTORS
19
Patent #:
Issue Dt:
02/07/2006
Application #:
10057185
Filing Dt:
01/25/2002
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD OF FABRICATING A CAPACITOR HAVING SIDEWALL SPACER PROTECTING THE DIELECTRIC LAYER
20
Patent #:
Issue Dt:
06/01/2004
Application #:
10058999
Filing Dt:
01/29/2002
Publication #:
Pub Dt:
07/31/2003
Title:
MODULE WITH ADHESIVELY ATTACHED HEAT SINK
21
Patent #:
Issue Dt:
03/30/2004
Application #:
10059268
Filing Dt:
01/31/2002
Title:
VAPOR TREATMENT FOR REPAIRING DAMAGE OF LOW-K DIELECTRIC
22
Patent #:
Issue Dt:
08/23/2005
Application #:
10059422
Filing Dt:
01/31/2002
Publication #:
Pub Dt:
01/09/2003
Title:
METHOD OF FORMING LATTICE-MATCHED STRUCTURE ON SILICON AND STRUCTURE FORMED THEREBY
23
Patent #:
Issue Dt:
01/07/2003
Application #:
10059713
Filing Dt:
01/29/2002
Title:
ACCESSING FIRST CACHE WITH RETURN STACK TOP ENTRY AND SECOND CACHE WITH NESXT ENTRY UPON RETURN INSTRUCTION
24
Patent #:
Issue Dt:
09/16/2003
Application #:
10059775
Filing Dt:
01/30/2002
Publication #:
Pub Dt:
07/31/2003
Title:
APPARATUS AND METHOD FOR FRONT SIDE CHEMICAL MECHANICAL PLANARIZATION (CMP) OF SEMICONDUCTOR WORKPIECES
25
Patent #:
Issue Dt:
11/18/2003
Application #:
10059863
Filing Dt:
01/30/2002
Publication #:
Pub Dt:
07/31/2003
Title:
HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-ADDRESSABLE MEMORY
26
Patent #:
Issue Dt:
09/02/2003
Application #:
10060422
Filing Dt:
01/30/2002
Title:
TRANSISTOR HAVING A GATE STACK COMPRISED OF A METAL, AND A METHOD OF MAKING SAME
27
Patent #:
Issue Dt:
01/13/2004
Application #:
10061263
Filing Dt:
01/31/2002
Publication #:
Pub Dt:
07/31/2003
Title:
BODY CONTACT MOSFET
28
Patent #:
Issue Dt:
08/10/2004
Application #:
10062812
Filing Dt:
01/31/2002
Publication #:
Pub Dt:
07/31/2003
Title:
EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL
29
Patent #:
Issue Dt:
08/17/2004
Application #:
10062972
Filing Dt:
01/31/2002
Publication #:
Pub Dt:
07/31/2003
Title:
EMBEDDED DRAM SYSTEM HAVING WIDE DATA BANDWIDTH AND DATA TRANSFER DATA PROTOCOL
30
Patent #:
Issue Dt:
12/02/2003
Application #:
10063095
Filing Dt:
03/19/2002
Publication #:
Pub Dt:
09/25/2003
Title:
FINFET CMOS WITH NVRAM CAPABILITY
31
Patent #:
Issue Dt:
08/17/2004
Application #:
10063212
Filing Dt:
03/29/2002
Publication #:
Pub Dt:
10/02/2003
Title:
COMPLEMENTARY TWO TRANSISTOR ROM CELL
32
Patent #:
Issue Dt:
05/04/2004
Application #:
10063225
Filing Dt:
04/01/2002
Publication #:
Pub Dt:
10/02/2003
Title:
DUAL EMITTER TRANSISTOR WITH ESD PROTECTION
33
Patent #:
Issue Dt:
06/15/2004
Application #:
10063323
Filing Dt:
04/11/2002
Publication #:
Pub Dt:
10/16/2003
Title:
DUAL DOUBLE GATE TRANSISTOR AND METHOD FOR FORMING
34
Patent #:
Issue Dt:
02/24/2004
Application #:
10063329
Filing Dt:
04/12/2002
Publication #:
Pub Dt:
10/16/2003
Title:
LOCALIZED DIRECT SENSE ARCHITECTURE
35
Patent #:
Issue Dt:
12/16/2003
Application #:
10063330
Filing Dt:
04/12/2002
Publication #:
Pub Dt:
10/23/2003
Title:
FIN MEMORY CELL AND METHOD OF FABRICATION
36
Patent #:
Issue Dt:
09/21/2004
Application #:
10063376
Filing Dt:
04/17/2002
Publication #:
Pub Dt:
10/30/2003
Title:
MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
37
Patent #:
Issue Dt:
01/24/2006
Application #:
10063394
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER
38
Patent #:
Issue Dt:
11/23/2004
Application #:
10063427
Filing Dt:
04/23/2002
Publication #:
Pub Dt:
10/23/2003
Title:
PHYSICAL DESIGN CHARACTERIZATION SYSTEM
39
Patent #:
Issue Dt:
12/11/2007
Application #:
10063495
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
10/30/2003
Title:
TESTING OF ECC MEMORIES
40
Patent #:
Issue Dt:
12/12/2006
Application #:
10063497
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
10/30/2003
Title:
OPTIMIZED ECC/REDUNDANCY FAULT RECOVERY
41
Patent #:
Issue Dt:
05/04/2004
Application #:
10063504
Filing Dt:
05/01/2002
Publication #:
Pub Dt:
11/06/2003
Title:
GLOBAL VOLTAGE BUFFER FOR VOLTAGE ISLANDS
42
Patent #:
Issue Dt:
08/10/2004
Application #:
10063846
Filing Dt:
05/17/2002
Publication #:
Pub Dt:
11/20/2003
Title:
INCORPORATION OF AN IMPURITY INTO A THIN FILM
43
Patent #:
Issue Dt:
07/13/2004
Application #:
10063858
Filing Dt:
05/20/2002
Publication #:
Pub Dt:
11/20/2003
Title:
FAULT FREE FUSE NETWORK
44
Patent #:
Issue Dt:
03/28/2006
Application #:
10063859
Filing Dt:
05/20/2002
Publication #:
Pub Dt:
11/20/2003
Title:
METHOD AND APPARATUS FOR PROVIDING NOISE SUPPRESSION IN AN INTEGRATED CIRCUIT
45
Patent #:
Issue Dt:
11/04/2003
Application #:
10063994
Filing Dt:
06/03/2002
Title:
FIN FET DEVICES FROM BULK SEMICONDUCTOR AND METHOD FOR FORMING
46
Patent #:
Issue Dt:
10/28/2003
Application #:
10064303
Filing Dt:
07/01/2002
Title:
MONOLITHICALLY INTEGRATED SOLID-STATE SIGE THERMOELECTRIC ENERGY CONVERTER FOR HIGH SPEED AND LOW POWER CIRCUITS
47
Patent #:
Issue Dt:
03/23/2004
Application #:
10064306
Filing Dt:
07/01/2002
Publication #:
Pub Dt:
01/01/2004
Title:
WRITEBACK AND REFRESH CIRCUITRY FOR DIRECT SENSED DRAM MACRO
48
Patent #:
Issue Dt:
06/22/2004
Application #:
10064375
Filing Dt:
07/08/2002
Publication #:
Pub Dt:
01/08/2004
Title:
HIGH IMPEDANCE ANTIFUSE
49
Patent #:
Issue Dt:
06/03/2008
Application #:
10064451
Filing Dt:
07/16/2002
Publication #:
Pub Dt:
01/22/2004
Title:
SUSCEPTOR POCKET WITH BEVELED PROJECTION SIDEWALL
50
Patent #:
Issue Dt:
11/14/2006
Application #:
10064486
Filing Dt:
07/19/2002
Publication #:
Pub Dt:
01/22/2004
Title:
METHOD AND APPARATUS TO MANAGE MULTI-COMPUTER DEMAND
51
Patent #:
Issue Dt:
09/21/2004
Application #:
10064493
Filing Dt:
07/22/2002
Publication #:
Pub Dt:
01/22/2004
Title:
APPLICATIONS OF SPACE-CHARGE-LIMITED CONDUCTION INDUCED CURRENT INCREASE IN NITRIDE-OXIDE DIELECTRIC CAPACITORS: VOLTAGE REGULATOR FOR POWER SUPPLY SYSTEM AND OTHERS
52
Patent #:
Issue Dt:
01/06/2004
Application #:
10064867
Filing Dt:
08/26/2002
Title:
COLUMN REDUNDANCY SYSTEM AND METHOD FOR A MICRO-CELL EMBEDDED DRAM (E-DRAM) ARCHITECTURE
53
Patent #:
Issue Dt:
09/21/2004
Application #:
10064921
Filing Dt:
08/29/2002
Publication #:
Pub Dt:
03/04/2004
Title:
APPARATUS FOR REDUCING SOFT ERRORS IN DYNAMIC CIRCUITS
54
Patent #:
Issue Dt:
11/16/2004
Application #:
10065201
Filing Dt:
09/25/2002
Publication #:
Pub Dt:
03/25/2004
Title:
VOLTAGE ISLAND CHIP IMPLEMENTATION
55
Patent #:
Issue Dt:
06/10/2003
Application #:
10065223
Filing Dt:
09/26/2002
Title:
SELF TIMING INTERLOCK CIRCUIT FOR EMBEDDED DRAM
56
Patent #:
Issue Dt:
08/16/2005
Application #:
10065475
Filing Dt:
10/22/2002
Publication #:
Pub Dt:
04/22/2004
Title:
TERMINATING RESISTOR DRIVER FOR HIGH SPEED DATA COMMUNICATION
57
Patent #:
Issue Dt:
02/08/2005
Application #:
10065839
Filing Dt:
11/25/2002
Publication #:
Pub Dt:
05/27/2004
Title:
DRAM-BASED SEPARATE I/O MEMORY SOLUTION FOR COMMUNICATION APPLICATIONS
58
Patent #:
Issue Dt:
05/11/2004
Application #:
10065884
Filing Dt:
11/27/2002
Title:
THINNING OF FUSE PASSIVATION AFTER C4 FORMATION
59
Patent #:
Issue Dt:
08/28/2007
Application #:
10066948
Filing Dt:
02/04/2002
Title:
REMOTE MANAGEMENT MECHANISM TO PREVENT ILLEGAL SYSTEM COMMANDS
60
Patent #:
Issue Dt:
12/30/2003
Application #:
10068396
Filing Dt:
02/05/2002
Title:
INERT ATOM IMPLANTATION METHOD FOR SOI GETTERING
61
Patent #:
Issue Dt:
05/13/2003
Application #:
10072330
Filing Dt:
02/07/2002
Title:
MICRO-STRUCTURES AND METHODS FOR THEIR MANUFACTURE
62
Patent #:
Issue Dt:
06/13/2006
Application #:
10072346
Filing Dt:
02/06/2002
Publication #:
Pub Dt:
08/08/2002
Title:
ADDRESS WRAP FUNCTION FOR ADDRESSABLE MEMORY DEVICES
63
Patent #:
Issue Dt:
08/10/2004
Application #:
10072486
Filing Dt:
02/07/2002
Publication #:
Pub Dt:
08/07/2003
Title:
NONINVASIVE OPTICAL METHOD AND SYSTEM FOR INSPECTING OR TESTING CMOS CIRCUITS
64
Patent #:
Issue Dt:
08/31/2004
Application #:
10073066
Filing Dt:
02/12/2002
Title:
PHOSPHINE TREATMENT OF LOW DIELECTRIC CONSTANT MATERIALS IN SEMICONDUCTOR DEVICE MANUFACTURING
65
Patent #:
Issue Dt:
06/24/2008
Application #:
10073630
Filing Dt:
02/11/2002
Publication #:
Pub Dt:
10/24/2002
Title:
PROGRAM COMPONENTS HAVING MULTIPLE SELECTABLE IMPLEMENTATIONS
66
Patent #:
Issue Dt:
05/25/2004
Application #:
10073695
Filing Dt:
02/11/2002
Publication #:
Pub Dt:
11/14/2002
Title:
ENHANCED INTERFACE THERMOELECTRIC COOLERS WITH ALL-METAL TIPS
67
Patent #:
Issue Dt:
05/24/2005
Application #:
10073755
Filing Dt:
02/11/2002
Publication #:
Pub Dt:
08/14/2003
Title:
MAGNETIC-FIELD SENSOR DEVICE
68
Patent #:
Issue Dt:
11/18/2003
Application #:
10078174
Filing Dt:
02/15/2002
Publication #:
Pub Dt:
08/21/2003
Title:
UNIQUE FEATURE DESIGN ENABLING STRUCTURAL INTEGRITY FOR ADVANCED LOW K SEMICONDUCTOR CHIPS
69
Patent #:
Issue Dt:
05/13/2003
Application #:
10078779
Filing Dt:
02/19/2002
Title:
METHOD OF PROTECTING SEMICONDUCTOR AREAS WHILE EXPOSING A GATE
70
Patent #:
Issue Dt:
09/23/2003
Application #:
10078948
Filing Dt:
02/19/2002
Publication #:
Pub Dt:
08/21/2003
Title:
SACRIFICIAL SEED LAYER PROCESS FOR FORMING C4 SOLDER BUMPS
71
Patent #:
Issue Dt:
08/28/2007
Application #:
10079289
Filing Dt:
02/19/2002
Publication #:
Pub Dt:
07/11/2002
Title:
FLUORINATED SILSESQUIOXANE POLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
72
Patent #:
Issue Dt:
06/10/2003
Application #:
10079861
Filing Dt:
02/22/2002
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH RELIABLE CONTACTS/VIAS
73
Patent #:
Issue Dt:
05/13/2003
Application #:
10082766
Filing Dt:
02/25/2002
Title:
NON-COHERENT CACHE BUFFER FOR READ ACCESSES TO SYSTEM MEMORY
74
Patent #:
Issue Dt:
04/14/2009
Application #:
10083149
Filing Dt:
02/27/2002
Title:
ARRANGEMENT IN A CHANNEL ADAPTER FOR TRANSMITTING DATA ACCORDING TO LINK WIDTHS SELECTED BASED ON RECEIVED LINK MANAGEMENT PACKETS
75
Patent #:
Issue Dt:
11/04/2003
Application #:
10083699
Filing Dt:
02/26/2002
Title:
METHOD OF DETECTING DEGRADATION IN PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF GRATING STRUCTURES, AND A DEVICE COMPRISING SUCH STRUCTURES
76
Patent #:
Issue Dt:
12/09/2003
Application #:
10083809
Filing Dt:
02/26/2002
Title:
METHOD OF REDUCING ELECTOMIGRATION IN A COPPER LINE BY ELECTROPLATING AN INTERIM COPPER-ZINC ALLOY THIN FILM ON A COPPER SURFACE AND A SEMICONDUCTOR DEVICE THEREBY FORMED
77
Patent #:
Issue Dt:
07/20/2004
Application #:
10083914
Filing Dt:
02/27/2002
Publication #:
Pub Dt:
08/28/2003
Title:
SELF-ALIGNED PATTERN FORMATION USING DUAL WAVELENGTHS
78
Patent #:
Issue Dt:
07/20/2004
Application #:
10084321
Filing Dt:
02/28/2002
Title:
METHOD FOR FORMING NITRIDE CAPPED CU LINES WITH REDUCED HILLOCK FORMATION
79
Patent #:
Issue Dt:
04/06/2004
Application #:
10084563
Filing Dt:
02/26/2002
Title:
METHOD OF REDUCING ELECTROMIGRATION BY FORMING AN ELECTROPLATED COPPER-ZINC INTERCONNECT AND A SEMICONDUCTOR DEVICE THEREBY FORMED
80
Patent #:
Issue Dt:
02/17/2004
Application #:
10085318
Filing Dt:
02/27/2002
Title:
INTERFACIAL BARRIER LAYER IN SEMICONDUCTOR DEVICES WITH HIGH-K GATE DIELECTRIC MATERIAL
81
Patent #:
Issue Dt:
09/17/2002
Application #:
10085348
Filing Dt:
02/27/2002
Title:
NON-REDUCING PROCESS FOR DEPOSITION OF POLYSILICON GATE ELECTRODE OVER HIGH-K GATE DIELECTRIC MATERIAL
82
Patent #:
Issue Dt:
02/24/2004
Application #:
10085938
Filing Dt:
02/28/2002
Title:
METHOD AND APPARATUS FOR MODELING OF BATCH DYNAMICS BASED UPON INTEGRATED METROLOGY
83
Patent #:
Issue Dt:
11/30/2004
Application #:
10085956
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
ASSOCIATION OF PROCESS CONTEXT WITH CONFIGURATION DOCUMENT FOR MANUFACTURING PROCESS
84
Patent #:
Issue Dt:
01/11/2011
Application #:
10085965
Filing Dt:
02/28/2002
Title:
COMMUNICATION SCHEME-INDEPENDENT INFRASTRUCTURE
85
Patent #:
Issue Dt:
04/18/2006
Application #:
10090507
Filing Dt:
03/04/2002
Title:
COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
86
Patent #:
Issue Dt:
12/13/2005
Application #:
10090589
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
07/03/2003
Title:
OPTICAL APERTURE FOR DATA RECORDING HAVING TRANSMISSION ENHANCED BY WAVEGUIDE MODE RESONANCE
87
Patent #:
Issue Dt:
08/24/2004
Application #:
10091193
Filing Dt:
03/05/2002
Publication #:
Pub Dt:
11/07/2002
Title:
SEMICONDUCTOR HIGH DIELECTRIC CONSTANT DECOUPLING CAPACITOR STRUCTURES AND PROCESS FOR FABRICATION
88
Patent #:
Issue Dt:
04/15/2008
Application #:
10091373
Filing Dt:
03/04/2002
Publication #:
Pub Dt:
10/02/2003
Title:
COPOLYMER FOR USE IN CHEMICAL AMPLIFICATION RESISTS
89
Patent #:
Issue Dt:
08/05/2003
Application #:
10091663
Filing Dt:
03/06/2002
Title:
LOW-POWER STATIC COLUMN REDUNDANCY SCHEME FOR SEMICONDUCTOR MEMORIES
90
Patent #:
Issue Dt:
06/06/2006
Application #:
10091766
Filing Dt:
03/05/2002
Title:
COMPUTER SYSTEM INITIALIZATION VIA BOOT CODE STORED IN A NON-VOLATILE MEMORY HAVING AN INTERFACE COMPATIBLE WITH SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
91
Patent #:
Issue Dt:
12/21/2004
Application #:
10093055
Filing Dt:
03/07/2002
Title:
METHOD AND APPARATUS FOR REORDERING PACKET TRANSACTIONS WITHIN A PERIPHERAL INTERFACE CIRCUIT
92
Patent #:
Issue Dt:
07/06/2004
Application #:
10093125
Filing Dt:
03/07/2002
Title:
BUFFER CIRCUIT FOR A PERIPHERAL INTERFACE CIRCUIT IN AN I/O NODE OF A COMPUTER SYSTEM
93
Patent #:
Issue Dt:
04/20/2004
Application #:
10093146
Filing Dt:
03/07/2002
Title:
PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM
94
Patent #:
Issue Dt:
07/06/2004
Application #:
10093270
Filing Dt:
03/07/2002
Title:
BUFFER CIRCUIT FOR ROTATING OUTSTANDING TRANSACTIONS
95
Patent #:
Issue Dt:
06/29/2004
Application #:
10093346
Filing Dt:
03/07/2002
Publication #:
Pub Dt:
04/17/2003
Title:
PERIPHERAL INTERFACE CIRCUIT FOR HANDLING GRAPHICS RESPONSES IN AN I/O NODE OF A COMPUTER SYSTEM
96
Patent #:
Issue Dt:
11/23/2004
Application #:
10093349
Filing Dt:
03/07/2002
Title:
METHOD AND APPARATUS FOR INITIATING PARTIAL TRANSACTIONS IN A PERIPHERAL INTERFACE CIRCUIT FOR AN I/O NODE OF A COMPUTER SYSTEM
97
Patent #:
Issue Dt:
03/04/2003
Application #:
10094061
Filing Dt:
03/08/2002
Title:
METHOD FOR IDENTIFYING AND CONTROLLING IMPACT OF AMBIENT CONDITIONS ON PHOTOLITHOGRAPHY PROCESSES
98
Patent #:
Issue Dt:
03/04/2003
Application #:
10094533
Filing Dt:
03/08/2002
Title:
LOW POWER STATIC MEMORY
99
Patent #:
Issue Dt:
05/15/2012
Application #:
10094550
Filing Dt:
03/08/2002
Publication #:
Pub Dt:
09/11/2003
Title:
SYSTEM FOR BROKERING FAULT DETECTION DATA
100
Patent #:
Issue Dt:
12/23/2003
Application #:
10095019
Filing Dt:
03/11/2002
Publication #:
Pub Dt:
07/11/2002
Title:
SYSTEM AND METHOD FOR INITIATING A SERIAL DATA TRANSFER BETWEEN TWO CLOCK DOMAINS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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