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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:054636/0001   Pages: 911
Recorded: 11/20/2020
Attorney Dkt #:37188/13
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
08/05/2008
Application #:
10867094
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
2
Patent #:
Issue Dt:
08/05/2008
Application #:
10867302
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/02/2004
Title:
SYSTEM FOR FACILITATING COVERAGE FEEDBACK TESTCASE GENERATION REPRODUCIBILITY
3
Patent #:
Issue Dt:
09/04/2007
Application #:
10867772
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
01/06/2005
Title:
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
4
Patent #:
Issue Dt:
12/05/2006
Application #:
10868791
Filing Dt:
06/17/2004
Publication #:
Pub Dt:
11/25/2004
Title:
METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
5
Patent #:
Issue Dt:
06/20/2006
Application #:
10869624
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
11/11/2004
Title:
IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
6
Patent #:
Issue Dt:
10/09/2007
Application #:
10869658
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
12/22/2005
Title:
HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE
7
Patent #:
Issue Dt:
01/08/2013
Application #:
10870318
Filing Dt:
06/17/2004
Title:
NETWORK INTERFACE SYSTEMS AND METHODS FOR OFFLOADING SEGMENTATION AND/OR CHECKSUMMING WITH SECURITY PROCESSING
8
Patent #:
Issue Dt:
06/20/2006
Application #:
10872173
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
11/18/2004
Title:
MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
9
Patent #:
Issue Dt:
01/30/2007
Application #:
10872707
Filing Dt:
06/21/2004
Title:
STRAINED SILICON MOSFET HAVING IMPROVED SOURCE/DRAIN EXTENSION DOPANT DIFFUSION RESISTANCE AND METHOD FOR ITS FABRICATION
10
Patent #:
Issue Dt:
05/29/2007
Application #:
10873240
Filing Dt:
06/23/2004
Title:
MULTI-CHANNEL TRANSISTOR WITH TUNABLE HOT CARRIER EFFECT
11
Patent #:
Issue Dt:
07/29/2008
Application #:
10873672
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
12
Patent #:
Issue Dt:
10/03/2006
Application #:
10873733
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
13
Patent #:
Issue Dt:
10/09/2007
Application #:
10875699
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMMON CARRIER
14
Patent #:
Issue Dt:
03/06/2007
Application #:
10875727
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
15
Patent #:
Issue Dt:
11/29/2005
Application #:
10879833
Filing Dt:
06/29/2004
Title:
DUAL GATED FINFET GAIN CELL
16
Patent #:
Issue Dt:
09/16/2008
Application #:
10880853
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
17
Patent #:
Issue Dt:
12/27/2011
Application #:
10881932
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD OF IMPROVING THE WAFER-TO-WAFER THICKNESS UNIFORMITY OF SILICON NITRIDE LAYERS
18
Patent #:
Issue Dt:
11/21/2006
Application #:
10883392
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
19
Patent #:
Issue Dt:
02/06/2007
Application #:
10883887
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/05/2006
Title:
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
20
Patent #:
Issue Dt:
04/27/2010
Application #:
10885462
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
21
Patent #:
Issue Dt:
11/02/2010
Application #:
10887069
Filing Dt:
07/08/2004
Title:
DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
22
Patent #:
Issue Dt:
10/10/2006
Application #:
10887087
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
01/12/2006
Title:
COPPER CONDUCTOR
23
Patent #:
Issue Dt:
12/13/2005
Application #:
10887983
Filing Dt:
07/08/2004
Title:
QUASI-STATIC RANDOM ACCESS MEMORY
24
Patent #:
Issue Dt:
08/06/2013
Application #:
10890649
Filing Dt:
07/14/2004
Title:
Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus
25
Patent #:
Issue Dt:
03/25/2008
Application #:
10892211
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
26
Patent #:
Issue Dt:
10/31/2006
Application #:
10896504
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD AND APPARATUS FOR MINIMIZING THRESHOLD VARIATION FROM BODY CHARGE IN SILICON-ON-INSULATOR CIRCUITRY
27
Patent #:
Issue Dt:
02/17/2009
Application #:
10896812
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CONTROL OF BURIED OXIDE IN SIMOX
28
Patent #:
Issue Dt:
03/17/2009
Application #:
10899199
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
09/01/2005
Title:
ON-THE-FLY ENCRYPTION/DECRYPTION FOR WLAN COMMUNICATIONS
29
Patent #:
Issue Dt:
08/19/2014
Application #:
10899200
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
08/04/2005
Title:
FAST CIPHERING KEY SEARCH FOR WLAN RECEIVERS
30
Patent #:
Issue Dt:
02/13/2007
Application #:
10899768
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
31
Patent #:
Issue Dt:
10/02/2007
Application #:
10899937
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DRAM ACCESS COMMAND QUEUING STRUCTURE
32
Patent #:
Issue Dt:
07/03/2007
Application #:
10900487
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
01/13/2005
Title:
TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
33
Patent #:
Issue Dt:
11/14/2006
Application #:
10901868
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/03/2005
Title:
RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
34
Patent #:
Issue Dt:
04/27/2010
Application #:
10902601
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
35
Patent #:
Issue Dt:
05/29/2007
Application #:
10902653
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
02/02/2006
Title:
ESD DISSIPATIVE COATING ON CABLES
36
Patent #:
Issue Dt:
07/31/2007
Application #:
10904056
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
37
Patent #:
Issue Dt:
08/29/2006
Application #:
10904059
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
05/11/2006
Title:
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
38
Patent #:
Issue Dt:
11/27/2007
Application #:
10904225
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/11/2006
Title:
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
39
Patent #:
Issue Dt:
07/15/2008
Application #:
10904309
Filing Dt:
11/03/2004
Publication #:
Pub Dt:
05/11/2006
Title:
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
40
Patent #:
Issue Dt:
04/01/2008
Application #:
10904323
Filing Dt:
11/04/2004
Publication #:
Pub Dt:
05/04/2006
Title:
MULTIPLE LAYER RESIST SCHEME IMPLEMENTING ETCH RECIPE PARTICULAR TO EACH LAYER
41
Patent #:
Issue Dt:
03/25/2008
Application #:
10904355
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
42
Patent #:
Issue Dt:
09/25/2007
Application #:
10904357
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
43
Patent #:
Issue Dt:
06/12/2007
Application #:
10904391
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
SELF-ALIGNED LOW-K GATE CAP
44
Patent #:
Issue Dt:
08/14/2007
Application #:
10904397
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
45
Patent #:
Issue Dt:
09/26/2006
Application #:
10904435
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
46
Patent #:
Issue Dt:
10/10/2006
Application #:
10904438
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
47
Patent #:
Issue Dt:
09/12/2006
Application #:
10904460
Filing Dt:
11/11/2004
Publication #:
Pub Dt:
05/11/2006
Title:
CIRCUIT AND METHOD OF CONTROLLING INTEGRATED CIRCUIT POWER CONSUMPTION USING PHASE CHANGE SWITCHES
48
Patent #:
Issue Dt:
01/15/2008
Application #:
10904528
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/18/2006
Title:
STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
49
Patent #:
Issue Dt:
07/18/2006
Application #:
10904555
Filing Dt:
11/16/2004
Publication #:
Pub Dt:
05/18/2006
Title:
FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
50
Patent #:
Issue Dt:
10/17/2006
Application #:
10904582
Filing Dt:
11/17/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR
51
Patent #:
Issue Dt:
04/22/2008
Application #:
10904601
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
52
Patent #:
Issue Dt:
09/19/2006
Application #:
10904680
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
DENDRITE GROWTH CONTROL CIRCUIT
53
Patent #:
Issue Dt:
07/10/2007
Application #:
10904681
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
54
Patent #:
Issue Dt:
03/20/2007
Application #:
10904808
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
55
Patent #:
Issue Dt:
11/21/2006
Application #:
10904827
Filing Dt:
12/01/2004
Publication #:
Pub Dt:
06/01/2006
Title:
IMPROVED HDP-BASED ILD CAPPING LAYER
56
Patent #:
Issue Dt:
07/03/2007
Application #:
10904950
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR EVALUATING A CIRCUIT
57
Patent #:
Issue Dt:
08/14/2007
Application #:
10905008
Filing Dt:
12/09/2004
Publication #:
Pub Dt:
05/11/2006
Title:
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
58
Patent #:
Issue Dt:
12/11/2007
Application #:
10905024
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE
59
Patent #:
Issue Dt:
03/25/2008
Application #:
10905025
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
60
Patent #:
Issue Dt:
11/04/2008
Application #:
10905027
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
61
Patent #:
Issue Dt:
07/08/2008
Application #:
10905041
Filing Dt:
12/13/2004
Publication #:
Pub Dt:
06/15/2006
Title:
SIDEWALL SEMICONDUCTOR TRANSISTORS
62
Patent #:
Issue Dt:
08/28/2007
Application #:
10905062
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DUAL STRESSED SOI SUBSTRATES
63
Patent #:
Issue Dt:
02/05/2008
Application #:
10905068
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
04/14/2005
Title:
METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL
64
Patent #:
Issue Dt:
03/20/2007
Application #:
10905094
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/15/2006
Title:
LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE
65
Patent #:
Issue Dt:
08/07/2007
Application #:
10905230
Filing Dt:
12/22/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MANUFACTURABLE COWP METAL CAP PROCESS FOR COPPER INTERCONNECTS
66
Patent #:
Issue Dt:
09/11/2007
Application #:
10905474
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES
67
Patent #:
Issue Dt:
01/13/2009
Application #:
10905475
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ERASABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
68
Patent #:
Issue Dt:
10/30/2007
Application #:
10905480
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION
69
Patent #:
Issue Dt:
04/14/2009
Application #:
10905486
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT
70
Patent #:
Issue Dt:
09/18/2007
Application #:
10905586
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS
71
Patent #:
Issue Dt:
09/25/2007
Application #:
10905589
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
ENHANCED PFET USING SHEAR STRESS
72
Patent #:
Issue Dt:
03/18/2008
Application #:
10905590
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING
73
Patent #:
Issue Dt:
12/26/2006
Application #:
10905684
Filing Dt:
01/17/2005
Publication #:
Pub Dt:
07/20/2006
Title:
SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION
74
Patent #:
Issue Dt:
04/08/2008
Application #:
10905816
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
07/27/2006
Title:
DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD
75
Patent #:
Issue Dt:
02/13/2007
Application #:
10905874
Filing Dt:
01/25/2005
Publication #:
Pub Dt:
07/27/2006
Title:
DUAL GATE FINFET RADIO FREQUENCY SWITCH AND MIXER
76
Patent #:
Issue Dt:
09/13/2011
Application #:
10905905
Filing Dt:
01/26/2005
Publication #:
Pub Dt:
07/27/2006
Title:
THERMO-MECHANICAL CLEAVABLE STRUCTURE
77
Patent #:
Issue Dt:
07/04/2006
Application #:
10905934
Filing Dt:
01/27/2005
Publication #:
Pub Dt:
07/27/2006
Title:
MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION
78
Patent #:
Issue Dt:
05/29/2007
Application #:
10905970
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/24/2006
Title:
CLOCK TREE DISTRIBUTION GENERATION BY DETERMINING ALLOWED PLACEMENT REGIONS FOR CLOCKED ELEMENTS
79
Patent #:
Issue Dt:
08/15/2006
Application #:
10905973
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/03/2006
Title:
METHOD OF FORMING A MIM CAPACITOR FOR CU BEOL APPLICATION
80
Patent #:
Issue Dt:
07/29/2008
Application #:
10906013
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
08/03/2006
Title:
REDUCING WIRE EROSION DURING DAMASCENE PROCESSING
81
Patent #:
Issue Dt:
05/19/2009
Application #:
10906016
Filing Dt:
01/31/2005
Publication #:
Pub Dt:
08/03/2006
Title:
VERTICAL CARBON NANOTUBE TRANSISTOR INTEGRATION
82
Patent #:
Issue Dt:
01/08/2008
Application #:
10906111
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/03/2006
Title:
COMPLIANT ELECTRICAL CONTACTS
83
Patent #:
Issue Dt:
04/08/2008
Application #:
10906112
Filing Dt:
02/03/2005
Publication #:
Pub Dt:
08/03/2006
Title:
ETCH PROCESS FOR IMPROVING YIELD OF DIELECTRIC CONTACTS ON NICKEL SILICIDES
84
Patent #:
Issue Dt:
07/22/2008
Application #:
10906147
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
08/10/2006
Title:
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
85
Patent #:
Issue Dt:
10/21/2008
Application #:
10906238
Filing Dt:
02/10/2005
Publication #:
Pub Dt:
08/10/2006
Title:
VERTICAL BODY-CONTACTED SOI TRANSISTOR
86
Patent #:
Issue Dt:
05/12/2009
Application #:
10906267
Filing Dt:
02/11/2005
Publication #:
Pub Dt:
08/17/2006
Title:
METHOD TO CREATE AIR GAPS USING NON-PLASMA PROCESSES TO DAMAGE ILD MATERIALS
87
Patent #:
Issue Dt:
07/12/2011
Application #:
10906268
Filing Dt:
02/11/2005
Publication #:
Pub Dt:
08/17/2006
Title:
METHOD TO CREATE REGION SPECIFIC EXPOSURE IN A LAYER
88
Patent #:
Issue Dt:
05/29/2007
Application #:
10906335
Filing Dt:
02/15/2005
Publication #:
Pub Dt:
08/17/2006
Title:
STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET
89
Patent #:
Issue Dt:
07/22/2008
Application #:
10906343
Filing Dt:
02/15/2005
Publication #:
Pub Dt:
08/17/2006
Title:
SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT
90
Patent #:
Issue Dt:
09/18/2007
Application #:
10906365
Filing Dt:
02/16/2005
Publication #:
Pub Dt:
08/17/2006
Title:
THIN FILM RESISTOR WITH CURRENT DENSITY ENHANCING LAYER (CDEL)
91
Patent #:
Issue Dt:
07/03/2007
Application #:
10906407
Filing Dt:
02/18/2005
Publication #:
Pub Dt:
08/24/2006
Title:
CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST
92
Patent #:
Issue Dt:
11/26/2013
Application #:
10906508
Filing Dt:
02/23/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD AND APPARATUS FOR VERIFYING MEMORY TESTING SOFTWARE
93
Patent #:
Issue Dt:
04/17/2007
Application #:
10906510
Filing Dt:
02/23/2005
Publication #:
Pub Dt:
08/24/2006
Title:
IMAGE SENSOR CELLS
94
Patent #:
Issue Dt:
10/30/2007
Application #:
10906547
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
09/07/2006
Title:
IMPROVED DOUBLE GATE ISOLATION
95
Patent #:
Issue Dt:
07/03/2007
Application #:
10906553
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
08/24/2006
Title:
INTEGRATED CIRCUIT LAYOUT CRITICAL AREA DETERMINATION USING VORONOI DIAGRAMS AND SHAPE BIASING
96
Patent #:
Issue Dt:
03/29/2011
Application #:
10906564
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD FOR TESTING A PHOTOMASK
97
Patent #:
Issue Dt:
10/02/2007
Application #:
10906625
Filing Dt:
02/28/2005
Publication #:
Pub Dt:
08/31/2006
Title:
BODY POTENTIAL IMAGER CELL
98
Patent #:
Issue Dt:
06/05/2007
Application #:
10906718
Filing Dt:
03/03/2005
Publication #:
Pub Dt:
09/07/2006
Title:
DENSE SEMICONDUCTOR FUSE ARRAY
99
Patent #:
Issue Dt:
11/08/2011
Application #:
10906808
Filing Dt:
03/08/2005
Publication #:
Pub Dt:
09/14/2006
Title:
SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP
100
Patent #:
Issue Dt:
11/02/2010
Application #:
10906826
Filing Dt:
03/08/2005
Publication #:
Pub Dt:
09/14/2006
Title:
METHOD OF DETERMINING N-WELL SCATTERING EFFECTS ON FETS
Assignor
1
Exec Dt:
11/17/2020
Assignee
1
PO BOX 309, UGLAND HOUSE
MAPLES CORPORATE SERVICES LIMITED
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BENJAMIN PETERSEN
1460 EL CAMINO REAL, 2ND FLOOR
SHEARMAN & STERLING LLP
MENLO PARK, CA 94025

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